CN110660420B - MRAM memory cell - Google Patents
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- CN110660420B CN110660420B CN201810687717.6A CN201810687717A CN110660420B CN 110660420 B CN110660420 B CN 110660420B CN 201810687717 A CN201810687717 A CN 201810687717A CN 110660420 B CN110660420 B CN 110660420B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/165—Auxiliary circuits
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
- H10B61/20—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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Abstract
The present invention provides an MRAM memory cell, comprising: the magnetic tunnel junction comprises two magnetic tunnel junctions and a spin orbit torque providing line, wherein the two magnetic tunnel junctions are respectively located on the same side surface of the spin orbit torque providing line, a free layer of each magnetic tunnel junction is close to the spin orbit torque providing line, the magnetization directions of reference layers of the two magnetic tunnel junctions are the same, and the spin orbit torque providing line is used for applying spin magnetic torques with opposite directions to the two magnetic tunnel junctions so that the free layers of the two magnetic tunnel junctions have opposite magnetization directions. The MRAM memory cell can store complementary resistance states, forms differential signals during state reading, reduces the reading error rate, and can remarkably improve the data reading speed.
Description
Technical Field
The present invention relates to the field of magnetic memory technology, and more particularly, to an MRAM memory cell.
Background
The core of a Memory cell of a conventional Magnetic Memory (MRAM) is a Magnetic tunnel junction MTJ, which is a two-port structure device composed of a multilayer film, the core is mainly composed of three films, two ferromagnetic layers are separated by a tunneling barrier layer, the magnetization direction of one of the ferromagnetic layers is fixed and is called a fixed layer or a reference layer, the magnetization direction of the other ferromagnetic layer can be changed and is called a free layer, and the magnetization direction of the free layer can be Parallel (Parallel, P for short) to the magnetization direction of the reference layer or Anti-Parallel (Anti-Parallel, AP for short) to the magnetization direction of the reference layer. When the magnetization directions of the two ferromagnetic layers are parallel, the MTJ assumes a low resistance state, whereas when the magnetization directions of the two ferromagnetic layers are anti-parallel, the MTJ assumes a high resistance state.
In order to improve the lifetime of MTJ, a magnetic memory based on spin orbit torque is developed, and by adding a heavy metal film under the free layer of MTJ, the current flowing through the heavy metal film can induce torque to drive magnetization reversal of the free layer.
In the process of implementing the invention, the inventor finds that at least the following technical problems exist in the prior art:
the existing magnetic memory based on spin orbit torque can only store low resistance state or high resistance state, and because the low resistance state and the high resistance state of the devices in the memory array are distributed, the read window is small or the distribution curves are overlapped, errors are easy to occur during reading, and the reading speed is low.
Disclosure of Invention
To solve the above problems, the present invention provides an MRAM memory cell capable of storing complementary resistance states, forming a differential signal during state reading, reducing a read error rate, and increasing a read speed.
The present invention provides an MRAM memory cell, comprising: the magnetic tunnel junction comprises two magnetic tunnel junctions and a spin orbit torque providing line, wherein the two magnetic tunnel junctions are respectively located on the same side surface of the spin orbit torque providing line, a free layer of each magnetic tunnel junction is close to the spin orbit torque providing line, the magnetization directions of reference layers of the two magnetic tunnel junctions are the same, and the spin orbit torque providing line is used for applying spin magnetic torques with opposite directions to the two magnetic tunnel junctions so that the free layers of the two magnetic tunnel junctions have opposite magnetization directions.
Optionally, the spin orbit torque providing line is of a linear structure, the two magnetic tunnel junctions are respectively located on the same side surface of the spin orbit torque providing line of the linear structure, and a gap is left between the two magnetic tunnel junctions;
correspondingly, the MRAM memory cell also comprises a transistor,
two ends of the spin orbit torque providing line of the linear structure are respectively led out to form an end point, and the two end points are connected to one point and connected to the write bit line;
the position of the spin orbit torque providing line of the linear structure between the two magnetic tunnel junctions leads out an end point which is connected to the drain electrode of the transistor;
the grid electrode of the transistor is connected with a word line; the source of the transistor is connected to a source line.
Optionally, the MRAM memory cell further includes a selector having two ends respectively connected to the write bit line and two ends of the spin orbit torque supply line of the line type structure for reducing a leakage current during a read operation.
Optionally, the spin orbit torque providing line is of a U-shaped bending line structure, and the two magnetic tunnel junctions are respectively located on two arms of the spin orbit torque providing line of the U-shaped bending line structure;
correspondingly, the MRAM memory cell also comprises two transistors,
two ends of the spin orbit torque providing line of the U-shaped bent line structure are respectively led out to form an end point, wherein one end point is connected to the drain electrode of the first transistor, and the other end point is connected to the write bit line;
the spin orbit torque providing line of the U-shaped bent line structure is positioned between the two magnetic tunnel junctions, and an end point is led out and connected to the drain electrode of the second transistor;
the grid electrode of the first transistor is connected with a writing word line, and the source electrode of the first transistor is connected with a source line;
the grid electrode of the second transistor is connected with the reading word line, and the source electrode of the second transistor is connected with the source line.
Optionally, two end points are respectively led out from the reference layers of the two magnetic tunnel junctions, and the two end points are respectively connected with one corresponding read bit line.
Optionally, the material of the spin orbit torque providing wire is a material having a spin orbit torque effect, comprising: heavy metals, topological insulators, or antiferromagnetic alloys.
Optionally, the spin orbit torque supply line has a multi-segment structure, the portions at two locations of the magnetic tunnel junctions are made of a material having a spin orbit torque effect, and the portions at other locations are made of a low-resistance metal material.
Optionally, both of the magnetic tunnel junctions are in-plane magnetization MTJs or out-of-plane perpendicular magnetization MTJs.
Optionally, the in-plane magnetization MTJ includes a reference layer, a barrier layer, a free layer, and an isolation layer between the free layer and the spin-orbit torque providing line for providing a growth substrate condition for the free layer crystalline structure.
Optionally, the out-of-plane perpendicular magnetization MTJ includes a bias magnetic field providing layer, a reference layer, a barrier layer, a free layer, a first isolation layer, and a second isolation layer, wherein,
the first isolation layer is positioned between the free layer and the spin orbit torque providing line and is used for providing a growth substrate condition of the crystal structure of the free layer;
the second isolation layer is positioned between the bias magnetic field providing layer and the reference layer and used for avoiding the bias magnetic field providing layer and the reference layer from generating direct exchange coupling effect.
The MRAM storage unit provided by the invention comprises two magnetic tunnel junctions and a spin orbit torque providing line, wherein the spin orbit torque providing line provides spin magnetic moments with opposite directions for two MTJs, so that the magnetization directions of free layers of the two MTJs are overturned to opposite directions, namely one of the two MTJs is in a high resistance state after being overturned, and the other one of the two MTJ is in a low resistance state, and the MRAM storage unit can store complementary resistance states. Compared with the prior art, when the state of the MRAM storage unit is read, the current flowing through the two MTJs can form a differential signal, so that reading errors are not easy to occur, and the reading error rate of the MRAM storage unit can be reduced.
Drawings
FIG. 1 is a schematic diagram of an embodiment of an MRAM memory cell of the invention;
FIG. 2 is a schematic diagram of another embodiment of an MRAM memory cell of the invention;
FIG. 3 is a schematic diagram of the current and magnetization directions for writing state 1 in the MRAM memory cell of FIG. 1;
FIG. 4 is a schematic diagram of the current flow and magnetization direction for writing state 2 in the MRAM memory cell of FIG. 1;
FIG. 5 is a block diagram illustrating a state read operation of the MRAM memory cell of FIG. 1;
FIG. 6 is a schematic diagram of an MRAM memory cell according to yet another embodiment of the invention;
FIG. 7 is a schematic diagram of the current flow and magnetization direction for writing state 1 in the MRAM memory cell of FIG. 6;
FIG. 8 is a schematic diagram showing the current and magnetization directions for writing state 2 in the MRAM memory cell of FIG. 6;
FIG. 9 is a block diagram illustrating a state read operation of the MRAM memory cell of FIG. 6;
FIG. 10 is an MRAM memory cell in the form of an in-plane magnetized dual MTJ differential complementary structure;
FIG. 11 is an MRAM memory cell in the form of an in-plane magnetized dual MTJ differential complementary structure with spacers;
FIG. 12 is an MRAM memory cell in the form of an out-of-plane perpendicular magnetization dual MTJ differential complementary structure;
FIG. 13 is an MRAM memory cell in the form of an out-of-plane perpendicular magnetization dual MTJ differential complementary structure with spacers.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
An embodiment of the present invention provides an MRAM memory cell, including: the magnetic tunnel junction comprises two magnetic tunnel junctions and a spin orbit torque providing line, wherein the two magnetic tunnel junctions are respectively positioned on the same side surface of the spin orbit torque providing line, a free layer of each magnetic tunnel junction is close to the spin orbit torque providing line, the magnetization directions of reference layers of the two magnetic tunnel junctions are the same, and the spin orbit torque providing line is used for applying spin magnetic torques with opposite directions to the two magnetic tunnel junctions so that the free layers of the two magnetic tunnel junctions have opposite magnetization directions.
For simplicity, the magnetic tunnel junction will be abbreviated as MTJ hereinafter. In the MRAM memory cell according to an embodiment of the present invention, the magnetization directions of the reference layers of the two MTJs are the same, the magnetization direction of the free layer is parallel or antiparallel to the magnetization direction of the reference layer, and the magnetization direction of the free layer is determined according to the direction of a current flowing through the portions of the spin orbit torque supply line located at the two MTJs. In a write operation of the MRAM memory cell, the spin orbit torque provides that the portions of the line at the two MTJ locations flow opposite currents to apply opposite spin magnetic moments to the two MTJs so that the free layer magnetizations of the two MTJs are opposite.
Specifically, during the writing operation of the MRAM memory cell, a current flowing through the spin orbit torque supply line forms a spin current on the surface, the spin current applies a spin magnetic moment to the MTJ free layer to flip the magnetization direction of the MTJ free layer, the current flowing through the spin orbit torque supply line below the two MTJs has an opposite direction, and the spin magnetic moments generated by the current have an opposite direction, so that the magnetization directions of the free layers of the two MTJs are flipped to opposite directions, that is, the two MTJs are flipped to have one in a high resistance state and the other in a low resistance state. When the state of the MRAM memory cell is read, the current flowing through the two MTJs can form a differential signal, so that reading errors are not easy to occur, and the reading error rate of the memory cell can be reduced. In addition, free layer overturning of the two MTJs can be achieved simultaneously by one-time current application, the current utilization rate is improved, and the circuit design is more concise.
Further, the material of the spin orbit torque supply wire is a material having a spin orbit torque effect, and a heavy metal such as Pt, Ta, W, Ir, Hf, Ru, Tl, Bi, Au, Os may be used, or a topological insulator such as a BiSe alloy, a BiTe alloy such as Bi2Se3, a BiSeTe alloy, TlBiSe may be used, or an antiferromagnetic alloy such as PtMn, IrMn, or the like may be used. The spin orbit torque providing line can also adopt a multi-section structure, and the parts which are positioned at the two MTJ positions and are in contact with the two MTJ are made of materials with spin orbit torque effect, such as BiSe and the like, and can provide certain spin magnetic torque of the free layer through the spin orbit torque effect, but the resistance is larger; the parts at other positions are low-resistance metal, such as Ta and the like, and the resistance of the spin-orbit torque supply line can be reduced by introducing the low-resistance metal, so that the energy consumption of the device is reduced.
Alternatively, as shown in fig. 1, the spin orbit torque supply line is a linear structure, the two magnetic tunnel junctions MTJA and MTJB are respectively located on the same side surface of the spin orbit torque supply line of the linear structure, a gap is left between the MTJA and MTJB, the free layers of the MTJA and MTJB are in direct contact with the spin orbit torque supply line, and the MRAM memory cell can normally read and write only by one transistor at this time. The transistors are used to control the writing and reading of the state of the MRAM memory cells.
Two ends of the spin orbit torque providing line of the linear structure are respectively led out to form an end point, and the two end points are connected to one point and connected to a writing bit line WBL; the position of the spin orbit torque providing line of the linear structure, which is positioned between the two magnetic tunnel junctions MTJA and MTJB, leads out an end point, and the end point is connected to the drain electrode of the transistor; the grid of the transistor is connected with a word line WL; the source of the transistor is connected to a source line SL. An end point is respectively led out from the reference layers of the MTJA and the MTJB, and the two end points are respectively corresponding to a read bit line RBLAAnd RBLBAnd (4) connecting.
Further, as shown in fig. 2, the MRAM further includes a selector electrically connected between the write bit line WBL and both ends of the spin orbit torque supply line of the line type structure, the selector having a specific turn-on voltage, and leakage during reading can be reduced by the selector.
With the MRAM memory cell of the above-described embodiment, since the spin orbit torque supply line passes current in two ways, two states can be written to the memory cell. The specific status writing and reading processes are as follows:
writing state 1: as shown in FIG. 3, WL stress turns on the transistor, SL stress, current flows from the transistor to both ends of the spin-orbit torque supply line, the current direction at the two MTJ contacts is opposite, the corresponding electron flow direction and the free layer magnetization direction are opposite, so that MTJ A and MTJB are low resistance and high resistance, respectively.
Writing state 2: as shown in fig. 4, WL voltage turns on the transistor, WBL voltage, current sinking into the transistor from both ends of the spin orbit torque supply line, current direction at the two MTJ contacts are opposite, corresponding electron flow direction and free layer magnetization direction are opposite, so that MTJ a and MTJB have high and low resistance, respectively.
The memory cell states written are as follows:
reading the state: as shown in FIG. 5, two read bit lines RBLAAnd RBLBAnd accessing a differential signal amplifier, and reading the data of the MRAM memory cell through the differential signal amplifier. WL is pressed to open the transistor, a differential signal amplifier applies reading voltage VR, currents respectively pass through MTJA and MTJB, the magnitude of the currents is related to the state of the MTJ, and the differential signal amplifier outputs data according to the magnitude relation of the currents. Defining two MTJ current difference sign (I)A-IB)>0 is data 1, sign (I) is definedA-IB)<0 is data 2.
Here, the differential signal amplifier may be a current-type sense amplifier, and may also be a voltage-type sense amplifier to implement the state reading of the MRAM memory cell.
The memory cell state data read is as follows:
optionally, the embodiment of the present invention further provides another type of MRAM memory cell. As shown in fig. 6, the spin orbit torque providing line is of a U-shaped bent line structure, the spin orbit torque providing line is bent into a U-shape, the MTJA and the MTJB are respectively located on two arms of the spin orbit torque providing line of the U-shaped bent line structure, the free layers of the MTJA and the MTJB are in direct contact with the spin orbit torque providing line, and the MRAM memory cell needs two transistors to implement reading and writing.
Correspondingly, the MRAM memory cell includes two transistors T1 and T2, which are used to control the reading and writing of the state of the MRAM memory cell.
Two ends of the spin orbit torque providing line with the U-shaped bent line structure are respectively led out to form an endpoint, wherein one endpoint is connected to the first transistor T1, the other terminal is connected to a write bit line WBL; the position of the spin orbit torque providing line of the U-shaped meander line structure between the two MTJs leads out a terminal which is connected to the drain of the second transistor T2; the gate of the first transistor T1 is connected to the write word line WWL, and the source is connected to the source line SL; the gate of the second transistor T2 is connected to the read word line RWL, and the source thereof is connected to the source line SL. Respectively leading out an end point from the reference layers of MTJA and MTJB, and respectively leading out two end points and a corresponding read bit line RBLAAnd RBLBAnd (4) connecting.
With the MRAM memory cells of the above embodiments, two states can be written to the memory cell as well. The specific status writing and reading processes are as follows:
writing state 1: as shown in fig. 7, the transistor T2 is turned off, the transistor T1 is turned on, current flows from the transistor T1, and since the current supplied through the spin-orbit moments below the two MTJs reverses the magnetization of the free layers of the two MTJs, the opposite spin moments are generated to act on the free layers of the two MTJs to switch their magnetization directions, and as shown in fig. 7, the MTJA is placed in a parallel state (i.e., low resistance state) and the MTJB is placed in an anti-parallel state (i.e., high resistance state).
Writing state 2: as shown in fig. 8, the transistor T2 is turned off, the transistor T1 is turned on, current flows in from the WBL and out from the transistor T1, and since the current flow through the spin orbit torque supply lines under the two MTJs is in opposite directions, opposite spin magnetic moments are generated to act on the free layers of the two MTJs to flip their magnetization directions, as shown in fig. 8, MTJA is placed in an anti-parallel state (i.e., high resistance state) and MTJB is placed in a parallel state (i.e., low resistance state).
Reading the state: as shown in FIG. 9, two read bit lines RBLAAnd RBLBAnd accessing a differential signal amplifier, and reading the data of the MRAM memory cell through the differential signal amplifier. The T1 transistor is closed, the T2 transistor is opened, the differential signal amplifier applies the same voltage signal to MTJA and MTJB, because the two MTJs have different resistances, the current passing through the two MTJs is different, the current magnitude is related to the state of the MTJs, and the differential signal amplifier outputs data according to the current magnitude relation. Defining two MTJ current difference sign (I)A-IB)>0 is data 1, sign (I) is definedA-IB)<0 is data 2.
In the above embodiment, the MTJA and MTJB may be in-plane magnetization MTJs or out-of-plane perpendicular magnetization MTJs. Here, only MRAM memory cells based on spin orbit torque supply lines with U-shaped meander line structures will be taken as an example, and various MTJ structures will be described in detail. MRAM memory cells based on a line-type structure of spin-orbit torque providing lines are equally applicable to MTJs of different structures.
As shown in fig. 10, an MRAM memory cell in the form of an in-plane magnetized dual MTJ differential complementary structure. MTJA and MTJB include a reference layer, a barrier layer, and a free layer, which provides a line direct contact with the spin orbit torque, wherein the material of each layer is only an example and is not limited to the above materials.
As shown in fig. 11, the MRAM memory cell is in the form of an in-plane magnetized dual MTJ differential complementary structure with spacers. The MTJA and MTJB include reference layer, barrier layer, free layer and isolation layer, the isolation layer locates between free layer and spin orbit moment and provides the line, the material can be Mo, Ta, etc., the function lies in providing the growth substrate condition of the crystal structure of free layer, avoid growing the tunnel TMR magneto-resistance that the free layer causes on the spin orbit moment directly provides the line and reduces, and this isolation layer thickness is thinner, has longer spin scattering distance. It should be noted that the reference layer is not limited to a single layer of magnetic material, and preferably, the reference layer may also be a composite structure of a ferromagnetic layer and an antiferromagnetic layer.
As shown in fig. 12, an MRAM memory cell in the form of an out-of-plane perpendicular magnetization dual MTJ differential complementary structure. The MTJA and MTJB include a reference layer, a barrier layer, a free layer, and a bias magnetic field providing layer, the free layer and the spin orbit torque providing line are in direct contact, wherein the material of each layer is only an example and is not limited to the above materials. Since the out-of-plane perpendicular magnetization MTJ is perpendicular to the direction of the spin magnetic moment generated by the spin-orbit moment supply line, an additional magnetic field in one direction is required to flip the MTJ free layer. In fig. 12 we add a bias magnetic field providing layer that provides a magnetic field in an orthogonal direction to the MTJ magnetization direction and the direction of the spin magnetic moment generated by the spin orbit torque providing line, together with the spin magnetic moment generated by the spin orbit torque providing line, to flip the MTJ free layer. It should be noted that the reference layer is not limited to a single layer of magnetic material, and may be a composite structure of a ferromagnetic layer and an artificial antiferromagnetic layer.
As shown in fig. 13, an MRAM memory cell in the form of an out-of-plane perpendicular magnetization dual MTJ differential complementary structure with spacers. The MTJA and the MTJB comprise a bias magnetic field providing layer, a reference layer, a barrier layer, a free layer, a first isolation layer and a second isolation layer, wherein the first isolation layer is positioned between the free layer and a spin orbit torque providing line, the material can be Mo, Ta and the like, the growth substrate condition for providing a free layer crystal structure is acted, the tunnel magnetoresistance TMR reduction caused by directly growing the free layer on the spin orbit torque providing line is avoided, and the isolation layer is thinner and has longer spin scattering distance; the second isolation layer is located between the bias magnetic field providing layer and the reference layer, and is made of Ta, Ru, Ir, Mo and the like, and has the function of avoiding the bias magnetic field providing layer from generating direct exchange coupling action with the reference layer.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are also within the scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.
Claims (9)
1. An MRAM memory cell, comprising: the magnetic tunnel junction comprises two magnetic tunnel junctions, a spin orbit torque providing line and a transistor, wherein the spin orbit torque providing line is of a linear structure, the two magnetic tunnel junctions are respectively positioned on the same side surface of the spin orbit torque providing line, a gap is reserved between the two magnetic tunnel junctions, a free layer of each magnetic tunnel junction is close to the spin orbit torque providing line, the magnetization directions of reference layers of the two magnetic tunnel junctions are the same, the spin orbit torque providing line is used for applying spin magnetic torques with opposite directions to the two magnetic tunnel junctions so as to enable the free layers of the two magnetic tunnel junctions to have opposite magnetization directions, and the two free layers of the two magnetic tunnel junctions have opposite magnetization directions,
two ends of the spin orbit torque providing line of the linear structure are respectively led out to form an end point, and the two end points are connected to one point and connected to the writing bit line;
the position of the spin orbit torque providing line of the linear structure between the two magnetic tunnel junctions leads out an end point which is connected to the drain electrode of the transistor;
the grid electrode of the transistor is connected with a word line;
the source of the transistor is connected to a source line.
2. The MRAM memory cell of claim 1, further comprising a selector having two ends respectively connected to two ends of the write bit line and the spin orbit torque providing line of the line type structure for reducing leakage during a read operation.
3. An MRAM memory cell, comprising: two magnetic tunnel junctions, a spin orbit torque providing line and two transistors, the spin orbit torque providing line adopts a U-shaped bending line structure, the two magnetic tunnel junctions are respectively positioned on the same side surface of two arms of the spin orbit torque providing line of the U-shaped bending line structure, and each free layer of the magnetic tunnel junction is close to the spin orbit torque providing line, the magnetization directions of the reference layers of the two magnetic tunnel junctions are the same, the spin orbit torque providing line is used for applying spin magnetic torques with opposite directions to the two magnetic tunnel junctions so as to enable the free layers of the two magnetic tunnel junctions to have opposite magnetization directions, wherein,
two ends of the spin orbit torque providing line of the U-shaped bent line structure are respectively led out to form an end point, wherein one end point is connected to the drain electrode of the first transistor, and the other end point is connected to the write bit line;
the spin orbit torque providing line of the U-shaped bent line structure is positioned between the two magnetic tunnel junctions, and an end point is led out and connected to the drain electrode of the second transistor;
the grid electrode of the first transistor is connected with a writing word line, and the source electrode of the first transistor is connected with a source line;
the grid electrode of the second transistor is connected with the reading word line, and the source electrode of the second transistor is connected with the source line.
4. MRAM memory cell according to any of claims 1 to 3, characterized in that the reference layers of both said magnetic tunnel junctions lead out a respective end point, which is connected to a respective read bit line.
5. The MRAM memory cell according to any of claims 1 to 3, wherein the material of the spin orbit torque providing line is a material having a spin orbit torque effect, comprising: heavy metals, topological insulators, or antiferromagnetic alloys.
6. The MRAM memory cell according to any one of claims 1 to 3, wherein the spin orbit torque supply line has a multi-segment structure, and a portion at the position of two of the magnetic tunnel junctions is a material having a spin orbit torque effect, and a portion at the other position is a low resistance metal material.
7. The MRAM memory cell of any of claims 1 to 3, wherein both of the magnetic tunnel junctions are in-plane magnetization MTJs or out-of-plane perpendicular magnetization MTJs.
8. The MRAM memory cell of claim 7, wherein the in-plane magnetization MTJ comprises a reference layer, a barrier layer, a free layer, and an isolation layer between the free layer and the spin orbit torque providing line for providing a growth substrate condition for the free layer crystal structure.
9. The MRAM memory cell of claim 7, wherein the out-of-plane perpendicular magnetization MTJ comprises a bias magnetic field providing layer, a reference layer, a barrier layer, a free layer, a first isolation layer, and a second isolation layer, wherein,
the first isolation layer is positioned between the free layer and the spin orbit torque providing line and is used for providing a growth substrate condition of the crystal structure of the free layer;
the second isolation layer is positioned between the bias magnetic field providing layer and the reference layer and used for avoiding the bias magnetic field providing layer and the reference layer from generating direct exchange coupling effect.
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| CN111490156A (en) * | 2020-04-21 | 2020-08-04 | 浙江驰拓科技有限公司 | Spin orbit torque magnetic memory device and preparation method thereof |
| CN111864060B (en) * | 2020-07-30 | 2023-02-28 | 浙江驰拓科技有限公司 | Spin orbit torque based memory cell |
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| CN112420095A (en) * | 2020-11-20 | 2021-02-26 | 复旦大学 | Spin orbit torque magnetic random access memory based on heavy metal layer magnetic tunnel junction pair |
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| CN114596890A (en) * | 2020-12-02 | 2022-06-07 | 浙江驰拓科技有限公司 | Non-uniform magnetized memory cell |
| CN113450849B (en) * | 2021-02-10 | 2022-12-16 | 北京航空航天大学 | Magnetic storage unit, data writing method, memory and equipment |
| CN113451356B (en) * | 2021-02-10 | 2022-12-20 | 北京航空航天大学 | Magnetic random access memory cell, memory and apparatus |
| CN113450850B (en) * | 2021-02-10 | 2022-12-16 | 北京航空航天大学 | Magnetic storage unit, data writing method, memory and equipment |
| CN113744779A (en) * | 2021-08-12 | 2021-12-03 | 中国科学院微电子研究所 | Magnetoresistive memory unit, write control method and memory module |
| WO2023060475A1 (en) * | 2021-10-13 | 2023-04-20 | 中国科学院微电子研究所 | Spintronic device, storage unit, storage array, and read-write circuit |
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| US10381552B2 (en) * | 2016-06-17 | 2019-08-13 | Western Digital Technologies, Inc. | SOT MRAM cell with perpendicular free layer and its cross-point array realization |
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