JP2011198416A - Magnetic memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a magnetic memory reducing a write error.SOLUTION: The magnetic memory includes: a magnetoresistive element 10 including a reference layer 14 having an invariable magnetization direction, a recording layer 12 having a variable magnetization direction, and a non-magnetic layer 13 held between the reference layer 14 and the recording layer 12, and a write circuit 23 for allowing a write current to flow into the magnetoresistive element 10 by using a constant current power supply when setting the magnetization arrangement of the magnetoresistive element 10 from parallel to anti-parallel, and for allowing a write current to flow into the magnetoresistance element 10 by using a constant-voltage power supply when setting the magnetization arrangement of the magnetoresistive element 10 from anti-parallel to parallel.

Description

  The present invention relates to a magnetic memory, for example, a magnetic memory including a storage element using a magnetoresistive effect.

  A magnetic random access memory (MRAM) uses an MTJ (Magnetic Tunnel Junction) element using a magnetoresistive effect in which a resistance value changes depending on the direction of magnetization as a memory element. A spin injection MRAM using a write method by spin injection is excellent in high speed, high integration, and durability, and is expected as a general-purpose nonvolatile random access memory.

  The MTJ element has a three-layer structure of a reference layer whose magnetization direction is invariable, a recording layer whose magnetization direction is variable, and an insulating layer sandwiched between the reference layer and the recording layer to form a tunnel barrier. Depending on whether the magnetizations of the recording layer and the reference layer are parallel or antiparallel, the MTJ element has a low resistance or a high resistance. By associating the low resistance state and high resistance state of the MTJ element with binary data, the MTJ element can be used as a memory element.

  Writing by spin injection is performed by passing a current in a direction perpendicular to the MTJ film surface and reversing the magnetization of the recording layer. When reversing the magnetization from the antiparallel state to the parallel state, current is applied in the direction from the recording layer toward the reference layer. By this energization, a spin torque that is parallel to the magnetization of the reference layer acts on the magnetization of the recording layer. On the other hand, when the magnetization is reversed from the parallel state to the antiparallel state, current is applied in the direction from the reference layer to the recording layer. By this energization, a spin torque that is antiparallel to the magnetization of the reference layer acts on the magnetization of the recording layer. By changing the energization direction in this way, binary data can be rewritten. As the current value increases, the probability that the magnetization of the recording layer is reversed also increases. A current that reduces the probability of magnetization reversal of the recording layer to 1/2 is defined as Ic.

  When writing data to the MTJ element, it is necessary to sufficiently reduce the write error rate (= 1−inversion probability). When the write current is Ic, the inversion probability is ½, but as the current increases, the inversion probability also increases. However, if the write current is increased to satisfy the specification of the write error rate, the tunnel barrier breaks down, or the current drive capability of the element selection transistor and the peripheral circuit transistor becomes insufficient.

  On the other hand, data stored in the MTJ element is also read by passing a current in a direction perpendicular to the MTJ film surface. The problem that data is rewritten by the read current is defined as read disturb. By reducing the read current or reducing the read pulse width, the probability of read disturb is reduced. However, if the read current is too small, there is a problem that the SN ratio cannot be obtained. Moreover, since the delay of the pulse due to the wiring capacity increases as the scale of the memory increases, there is a limit to reducing the pulse width.

  As a related technique, a resistance change memory that suppresses erroneous writing due to heat generation of a resistance change element is disclosed (Patent Document 1).

US Patent Application Publication No. 2009/0034320

  The present invention provides a magnetic memory capable of reducing write errors.

  A magnetic memory according to an aspect of the present invention includes a magnetoresistive element including a reference layer whose magnetization direction is invariable, a recording layer whose magnetization direction is variable, and a nonmagnetic layer sandwiched between the reference layer and the recording layer. A first write circuit for supplying a write current to the magnetoresistive element using a constant current power source when setting the element and the magnetization arrangement of the magnetoresistive element from parallel to antiparallel, and the magnetization arrangement of the magnetoresistive element Is set from anti-parallel to parallel, a second write circuit for supplying a write current to the magnetoresistive element using a constant voltage power supply.

  According to the present invention, a magnetic memory capable of reducing write errors can be provided.

1 is a cross-sectional view showing a configuration of an MTJ element 10 according to an embodiment. FIG. 3 is a schematic diagram illustrating a magnetization state of the MTJ element 10. FIG. 3 is a schematic diagram for explaining voltage dependency of resistance of the MTJ element 10. The schematic diagram which shows the process in which read-out disturbance generate | occur | produces. The graph which shows the electric current dependence of inversion probability. The result of measuring the current Icr of the MTJ element. The schematic diagram which shows the process in which read-out disturbance generate | occur | produces. 1 is a block diagram showing a configuration of an MRAM according to a first embodiment. The circuit diagram which shows the principal part of MRAM which concerns on a 1st Example. The circuit diagram which shows the structure of one memory cell MC. The circuit diagram which shows the principal part of MRAM which concerns on a 2nd Example.

  Embodiments of the present invention will be described below with reference to the drawings. However, it should be noted that the drawings are schematic or conceptual, and the dimensions and ratios of the drawings are not necessarily the same as the actual ones. Further, even when the same portion is represented between the drawings, the dimensional relationship and ratio may be represented differently. In particular, the following embodiments exemplify an apparatus and a method for embodying the technical idea of the present invention, and the technical idea of the present invention depends on the shape, structure, arrangement, etc. of components. Is not specified. Various changes can be added to the technical idea of the present invention without departing from the gist thereof. In the following description, elements having the same function and configuration are denoted by the same reference numerals, and redundant description will be given only when necessary.

[1. Configuration of magnetoresistive element]
FIG. 1 is a cross-sectional view showing a configuration of a magnetoresistive element (MTJ element) 10 according to an embodiment of the present invention. The MTJ element 10 is configured by laminating a lower electrode 11, a recording layer (also referred to as a storage layer or a free layer) 12, a nonmagnetic layer 13, a reference layer (also referred to as a fixed layer) 14, and an upper electrode 15 in this order. Note that the stacking order may be reversed.

  Each of the recording layer 12 and the reference layer 14 is made of a ferromagnetic material. Examples of the ferromagnetic material include one element of cobalt (Co), iron (Fe), and nickel (Ni), or of these elements. An alloy containing one or more elements can be used. Each of the recording layer 12 and the reference layer 14 has a structure in which a layer made of an alloy or artificial lattice having a high magnetic anisotropy and a layer made of CoFe or CoFeB having a high spin polarization are stacked. be able to.

  Each of the recording layer 12 and the reference layer 14 has magnetic anisotropy in a direction perpendicular to the film surface, and their easy magnetization direction is perpendicular to the film surface. That is, the MTJ element 10 is a so-called perpendicular magnetization MTJ element in which the magnetization directions of the recording layer 12 and the reference layer 14 are perpendicular to the film surface. Note that the easy magnetization direction is a direction in which the internal energy is lowest when the spontaneous magnetization is directed in the absence of an external magnetic field, assuming a macro-sized ferromagnetic material. The difficult magnetization direction is a direction in which the internal energy is maximized when the spontaneous magnetization is directed in the absence of an external magnetic field, assuming a macro-sized ferromagnetic material.

  The recording layer 12 has a variable magnetization (or spin) direction (inverted). The reference layer 14 has an invariable magnetization direction (fixed). The reference layer 14 is set to have a sufficiently large perpendicular magnetic anisotropy energy than the recording layer 12. The magnetic anisotropy can be set by adjusting the material configuration and the film thickness. In this way, the magnetization reversal current of the recording layer 12 is reduced, and the magnetization reversal current of the reference layer 14 is made larger than that of the recording layer 12. Thereby, it is possible to realize the MTJ element 10 including the recording layer 12 having a variable magnetization direction and the reference layer 14 having a constant magnetization direction with respect to a predetermined write current.

As the nonmagnetic layer 13, a nonmagnetic metal, a nonmagnetic semiconductor, an insulator, or the like can be used. When an insulator is used as the nonmagnetic layer 13, it is called a tunnel barrier layer, and when a metal is used as the nonmagnetic layer 13, it is called a spacer layer. As the tunnel barrier layer, an insulating oxide film such as MgO or Al ₂ O ₃ can be used. The thickness of the insulating oxide film is desirably set to about 1 nm or less so that the sheet resistance due to the tunnel current is about several tens of Ω · μm ² or less. The size of the MTJ element 10 is desirably a diameter (φ) of 100 nm or less, particularly φ40 nm or less in order to perform spin injection efficiently.

  In the present embodiment, an example of a perpendicular magnetization MTJ element will be described. However, the contents of the present embodiment are valid even in the case of an in-plane magnetization MTJ element in which the direction of magnetization is horizontal to the film surface.

  FIG. 2 is a schematic diagram for explaining the magnetization state of the MTJ element 10. In the present embodiment, a spin injection writing method is adopted in which a write current is directly supplied to the MTJ element 10 and the magnetization state of the MTJ element 10 is controlled by this write current. The MTJ element 10 can take one of two states, a high resistance state and a low resistance state, depending on whether the relative relationship of magnetization between the recording layer 12 and the reference layer 14 is parallel or antiparallel.

  As shown in FIG. 2A, when a write current from the recording layer 12 to the reference layer 14 is passed through the MTJ element 10, the relative relationship of magnetization between the recording layer 12 and the reference layer 14 becomes parallel. In the parallel state, the MTJ element 10 has the lowest resistance value, that is, the MTJ element 10 is set to the low resistance state. The low resistance state of the MTJ element 10 is defined as, for example, data “0”.

  On the other hand, as shown in FIG. 2B, when a write current from the reference layer 14 to the recording layer 12 is applied to the MTJ element 10, the relative relationship of magnetization between the recording layer 12 and the reference layer 14 is antiparallel. become. In the antiparallel state, the resistance value of the MTJ element 10 is the highest, that is, the MTJ element 10 is set to a high resistance state. The high resistance state of the MTJ element 10 is defined as, for example, data “1”. Thereby, the MTJ element 10 can be used as a storage element capable of storing 1-bit data (binary data).

[2. Read and write methods]
FIG. 3 is a diagram schematically showing the voltage dependence of the resistance of the MTJ element 10. The vertical axis represents the resistance (also referred to as MTJ resistance) of the MTJ element 10. The horizontal axis indicates the voltage applied to the MTJ element 10, where the left side from the vertical axis is the polarity of current flowing from the reference layer 14 to the recording layer 12, and the right side from the vertical axis is from the recording layer 12 to the reference layer 14. The polarity in which a current flows toward is shown. The right side is a positive voltage and the left side is a negative voltage. The upper line is the MTJ resistance in the high resistance state, and the lower line is the MTJ resistance in the low resistance state. For example, in order to prevent dielectric breakdown of the MTJ element 10, the voltage applied to the MTJ element 10 is set to about 1 V or less.

  The rate of resistance change due to magnetization reversal is called the magnetoresistance ratio (MR), where Rap is the resistance value in the high resistance state and Rp is the resistance value in the low resistance state, “MR = (Rap−Rp) / Rp ". As shown in FIG. 3, the voltage dependency of the MTJ resistance is different between the high resistance state and the low resistance state.

  When the MTJ element 10 is in an antiparallel state, that is, in a high resistance state, the MTJ resistance has a strong dependency on the bias voltage, and the resistance value decreases as the absolute value of the applied voltage increases. On the other hand, when the MTJ element 10 is in a parallel state, that is, in a low resistance state, the MTJ resistance is less dependent on the bias voltage, and the change in the resistance value is small even when the absolute value of the applied voltage increases. For this reason, when the absolute value of the applied voltage increases, MR, which is an index of the resistance difference between the two states, decreases. Unless otherwise specified in the future, the resistance change rate when the applied voltage to the MTJ element 10 is sufficiently small is MR.

  When reading data from the MTJ element 10, the direction of the read current is selected and used in either the direction from the reference layer 14 toward the recording layer 12 or the direction from the recording layer 12 toward the reference layer 14. First, a case where reading is performed by energizing in a direction in which spin torque works from a parallel state to an antiparallel state will be described. This corresponds to the case where reading is performed using the left half of FIG. 3, and the reading current flows from the reference layer 14 toward the recording layer 12.

  The arrow from state A1 to state A3 in FIG. 3 causes a read disturb in which data is read by applying a negative constant voltage to the MTJ element 10 in the low resistance state, and the data is erroneously inverted. It shows the process. FIG. 4 schematically illustrates the magnetization movement in this process and the read current flowing through the MTJ element 10. A1 to A3 in FIG. 4 correspond to A1 to A3 in FIG.

  FIG. 4A1 shows a state immediately after energization, and the magnetization direction of the recording layer 12 is substantially parallel to the magnetization direction of the reference layer 14. Thereafter, as shown in FIG. 4 (A2), the spin torque due to the spin-polarized current acts on the recording layer 12, a uniform precession occurs in the magnetization of the recording layer 12, and the magnetization direction tilts from the vertical direction. . As a result, the MTJ resistance increases, so that the current flowing in the MTJ element 10 in the state A2 in FIG. 3 is smaller than the initial current flowing in the state A1 in FIG. Since the frictional force acts on the precession of magnetization, if the current decreases before the magnetization direction crosses the equator plane, the state A2 in FIG. The probability of returning increases. That is, it is considered that the magnetization reversal probability due to spin injection strongly depends not only on the current in the initial state of A1, but also on the current during the reversal of A2. When reading is performed at a constant voltage, the probability of read disturb decreases in the MTJ element 10 having a large MR.

  FIG. 5 is an example of an experimental result of measuring the current dependence of the reversal probability when the magnetization reversal from the parallel state to the antiparallel state. The current I on the horizontal axis is normalized by a current Ic at which the magnetization reversal probability of the recording layer is ½. The vertical axis represents the inversion probability of the MTJ element and is expressed in logarithm. “E” in FIG. 5 means 10 exponential notation. Generally, there is a relationship of Ic_PtoAP> Ic_APtoP, which is different from Ic (Ic_PtoAP) in which magnetization is reversed from parallel to antiparallel and Ic (Ic_APtoP) in which magnetization is reversed from antiparallel to parallel.

By reducing the current flowing through the MTJ element 10, the inversion probability, that is, the read disturb probability is exponentially reduced. When the MTJ element 10 is used as a memory element, the read current is set so that the inversion probability is equal to or less than an allowable value by design. Here, it is assumed that the allowable value is 1 × 10 ⁻¹⁰ (= 1.E−10), and a current with an inversion probability P = 1 × 10 ⁻¹⁰ is defined as Icr.

  FIG. 6 shows the result of measuring the current Icr for a plurality of MTJ elements having different MR. The horizontal axis is MR (%). The vertical axis is a value obtained by normalizing the current Icr with the current Ic. From FIG. 6, the value of Icr / Ic tends to increase as MR increases. This means that the read disturb is reduced as the MTJ element has a higher MR. The experimental result of FIG. 6 is considered to be the result of suppressing the magnetization reversal by reducing the current due to the increase of the MTJ resistance during the magnetization reversal shown in the state A2, as described in FIG. 3 and FIG. Can do.

  As described above, when data is read using a read current from the reference layer 14 toward the recording layer 12, it is advantageous to use a constant voltage source because read disturbance can be reduced. In FIG. 3, a solid line arrow indicates a highly efficient path, and a broken line arrow indicates an inefficient path.

  On the other hand, when a read current is supplied using a constant current source, magnetization reversal occurs along the arrow from state A1 to state A5 in FIG. In this case, the MTJ resistance increases in the state A4 during the inversion, the absolute value of the voltage applied to the MTJ element 10 increases accordingly, and the current remains constant. For this reason, the state A4 in FIG. 3 does not return to the state A1, but the state A5 is shifted to, and the probability of magnetization reversal, that is, the probability of occurrence of read disturb increases.

  Next, a case where writing is performed from the parallel state to the antiparallel state by flowing a write current in the direction from the reference layer 14 toward the recording layer 12 will be described. In this case, since the magnetization of the recording layer 12 must be reliably reversed, it is advantageous to use a constant current power source.

  In the constant voltage power supply, magnetization reversal occurs along the path of the arrow from state B1 to state B2 in FIG. 3, but the MTJ resistance increases during the reversal. For this reason, the current flowing through the MTJ element 10 decreases, and the probability that a write error will occur increases. On the other hand, if writing is performed using a constant current power supply, magnetization reversal will occur through the path of the arrow from state B1 to state B3 in FIG. In this case, the absolute value of the voltage increases by the increase in the MTJ resistance, and the current does not decrease. Therefore, the magnetization of the MTJ element 10 can be reversed with high efficiency.

  In order to ensure the signal-to-noise ratio of the read signal, the absolute value of the voltage in state A1 has a lower limit. In the state B3, the write voltage cannot be increased beyond the tunnel barrier breakdown voltage. When reading and writing are performed by applying current in the direction in which spin torque works from the parallel state to the antiparallel state, reading is performed with a constant voltage power supply, and writing is performed with a constant current power supply, thereby satisfying the above two restrictions. However, read disturb and write error can be reduced.

  Next, a case where reading is performed by energizing in the direction in which the spin torque works from the antiparallel state to the parallel state will be described. This corresponds to the case where reading is performed using the right half of FIG. 3, and the reading current flows from the recording layer 12 toward the reference layer 14.

  The arrow from state C1 to state C3 in FIG. 3 causes a read disturb in which data is read by applying a positive constant voltage to the MTJ element 10 in the high resistance state, and the data is erroneously inverted. It shows the process. FIG. 7 schematically illustrates the magnetization movement in this process and the read current flowing through the MTJ element 10. C1 to C3 in FIG. 7 correspond to C1 to C3 in FIG.

  FIG. 7C1 shows a state immediately after energization, and the magnetization direction of the recording layer 12 is substantially antiparallel to the magnetization direction of the reference layer 14. Thereafter, as shown in FIG. 7C2, spin torque due to the spin-polarized current acts on the recording layer 12, and uniform precession occurs in the magnetization of the recording layer 12, and the direction of magnetization tilts from the perpendicular direction. . As a result, the MTJ resistance decreases, so that the current flowing in the MTJ element 10 in the state C2 of FIG. 3 increases from the initial current flowing in the state C1. Therefore, the state C2 in FIG. 3 does not return to the state C1, but shifts to the state C3, and the probability of magnetization reversal, that is, the probability of occurrence of read disturb increases.

  On the other hand, when a read current is passed using a constant current power supply, magnetization reversal occurs along the arrow from state C1 to state C5 in FIG. In this case, even if the MTJ resistance decreases in the middle of the magnetization reversal in the state C4 in FIG. 3, the voltage applied to the MTJ element 10 correspondingly decreases, and the current flowing through the MTJ element 10 does not increase. Therefore, even when the state C4 is reached, the probability of returning to the initial state C1 again by the friction generated by the precession of magnetization and avoiding the read disturb is higher than the probability of returning from the state C2 to the state C1. That is, when reading is performed by flowing a read current in the direction from the recording layer 12 to the reference layer 14, using a constant current power supply is more advantageous for reducing read disturb than using a constant voltage power supply. It is.

  Next, a case where writing is performed from the antiparallel state to the parallel state by flowing a write current in the direction from the recording layer 12 to the reference layer 14 will be described. In this case, it is advantageous to use a constant voltage power source.

  When a constant voltage power supply is used, magnetization reversal occurs along the path of the arrow from state D1 to state D2 in FIG. 3, but when the MTJ resistance decreases during the magnetization reversal, the current flowing through the MTJ element 10 increases. To do. Therefore, the magnetization of the MTJ element 10 can be reversed with high efficiency.

  On the other hand, when a constant current power supply is used, magnetization reversal occurs along the path of the arrow from state D1 to state D3 in FIG. 3, but the voltage applied to the MTJ element 10 decreases during the magnetization reversal, Remains constant. Therefore, the probability of occurrence of a write error that returns to the initial state D1 due to friction generated with the precession of magnetization from the middle of magnetization reversal increases.

  In order to ensure the S / N ratio of the read signal, the voltage of the state C1 has a lower limit. In the state D1, the write voltage cannot be increased beyond the tunnel barrier breakdown voltage. When reading and writing are performed by energizing in the direction in which the spin torque works from the antiparallel state to the parallel state, reading is performed with a constant current power source, and writing is performed with a constant voltage power source, thus satisfying the above two restrictions. However, read disturb and write error can be reduced.

[3. Circuit configuration of MRAM]
Next, an example of the circuit configuration of the MRAM that employs the reading method and the writing method of the present embodiment will be described. A circuit configuration example (first embodiment) in which a read current flows through the MTJ element 10 in the direction from the reference layer 14 toward the recording layer 12, and a read current in the direction from the recording layer 12 toward the reference layer 14 in the MTJ element 10 A circuit configuration example (second embodiment) in the case of flowing a current will be described in order.

[3-1. First Example]
FIG. 8 is a block diagram showing the configuration of the MRAM according to the first embodiment. The MRAM includes a memory cell array 20 in which a plurality of memory cells MC are arranged in a matrix. Memory cell MC includes an MTJ element 10. In the memory cell array 20, a plurality of first bit lines BL1 and a plurality of second bit lines BL2 extending in the column direction are alternately arranged. The memory cell array 20 is provided with a plurality of word lines WL extending in the row direction.

  A first write circuit 23-1 and a first read circuit 24-1 are connected to one end of the first bit line BL1 and the second bit line BL2 via the first bit line selection circuit 21-1. It is connected. The second write circuit 23-2 and the second read circuit 24-2 are connected to the other ends of the first bit line BL1 and the second bit line BL2 via the second bit line selection circuit 21-2. Is connected.

  For example, a column address is input to the column decoder 22 from the outside. The column decoder 22 decodes the column address, sends the decode signals Ayn and Byn to the first bit line selection circuit 21-1, and sends the decode signals Ays and Bys to the second bit line selection circuit 21-2. The first bit line selection circuit 21-1 selects a bit line designated by the decode signals Ayn and Byn. The second bit line selection circuit 21-2 selects a bit line designated by the decode signals Ays and Bys.

  A row decoder 25 is connected to the word line WL. For example, a row address is input to the row decoder 25 from the outside. The row decoder 25 decodes the row address and selects a word line specified by the row address.

  The write circuits 23-1 and 23-2 write the first write current via the first bit line BL 1, the memory cell MC and the second bit line BL 2, or the first A second write current is passed through the second bit line BL2, the memory cell MC, and the first bit line BL1. At this time, the write circuits 23-1 and 23-2 generate a first write current using a constant current power source. The write circuits 23-1 and 23-2 generate a second write current using a constant voltage power supply.

  The read circuits 24-1 and 24-2 pass a read current that passes through the first bit line BL1, the memory cell MC, and the second bit line BL2 when reading data. At this time, the read circuits 24-1 and 24-2 generate a read current using a constant voltage power supply.

  The control circuit 26 controls the write operation by supplying the control signals SRCn and SNKn to the first write circuit 23-1 and the control signals SRCs and SNKs to the second write circuit 23-2. Further, the control circuit 26 controls the reading operation by supplying SNKr to the first reading circuit 24-1 and SRCr to the second reading circuit 24-2.

  FIG. 9 is a circuit diagram showing the configuration of the bit line selection circuit 21, the write circuit 23, and the read circuit 24. FIG. 9 shows only the circuit portion connected to the 2 × 2 region in the memory cell array 20 arranged in a matrix.

  The memory cell MC has one MTJ element 10 and one select transistor ST. FIG. 10 is a circuit diagram showing a configuration of one memory cell MC. The selection transistor ST is composed of, for example, an N-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor).

  The reference layer 14 of the MTJ element 10 is connected to the first bit line BL1 via the upper electrode 15 (not shown). The recording layer 12 of the MTJ element 10 is connected to one end of the current path of the selection transistor ST via a lower electrode 11 (not shown). The other end of the current path of the selection transistor ST is connected to the second bit line BL2. A word line WL is connected to the gate of the selection transistor ST.

  The first bit line selection circuit 21-1 includes N-channel MOSFETs (NMOSFETs) 30 as the number of switch elements corresponding to the first bit line BL1 and the number of switch elements corresponding to the second bit line BL2. NMOSFET 31. The NMOSFET 30 <t> is connected between the first bit line BL1 <t> and the node N1. A decode signal Ayn <t> is supplied from the column decoder 22 to the gate of the NMOSFET 30 <t>. The NMOSFET 31 <t> is connected between the second bit line BL2 <t> and the node N2. A decode signal Byn <t> is supplied from the column decoder 22 to the gate of the NMOSFET 31 <t>.

  The second bit line selection circuit 21-2 includes NMOSFETs 32 as the number of switch elements corresponding to the first bit line BL1 and NMOSFETs 33 as the number of switch elements corresponding to the second bit line BL2. Yes. The NMOSFET 32 <t> is connected between the first bit line BL1 <t> and the node N3. A decode signal Bys <t> is supplied from the column decoder 22 to the gate of the NMOSFET 32 <t>. The NMOSFET 33 <t> is connected between the second bit line BL2 <t> and the node N4. A decode signal Ays <t> is supplied from the column decoder 22 to the gate of the NMOSFET 33 <t>.

  The first write circuit 23-1 includes a constant current power supply 34, a P-channel MOSFET (PMOSFET) 35 as a switch element, and an NMOSFET 36 as a switch element. The source of the PMOSFET 35 is connected to the constant current power supply 34, the drain of the PMOSFET 35 is connected to the node N1, and the control signal SRCn is supplied from the control circuit 26 to the gate of the PMOSFET 35. The drain of the NMOSFET 36 is connected to the node N1, the source of the NMOSFET 36 is grounded, and the control signal SNKn is supplied from the control circuit 26 to the gate of the NMOSFET 36. VDD is a power supply voltage, and VSS is a ground voltage.

  The second write circuit 23-2 includes a constant voltage power source 37, a PMOSFET 38 as a switch element, and an NMOSFET 39 as a switch element. The source of the PMOSFET 38 is connected to the constant voltage power supply 37, the drain of the PMOSFET 38 is connected to the node N4, and the control signal SRCs is supplied from the control circuit 26 to the gate of the PMOSFET 38. The drain of the NMOSFET 39 is connected to the node N4, the source of the NMOSFET 39 is grounded, and the control signal SNKs is supplied to the gate of the NMOSFET 39 from the control circuit 26.

  The first readout circuit 24-1 includes an NMOSFET 40 as a switch element. The drain of the NMOSFET 40 is connected to the node N2, the source of the NMOSFET 40 is grounded, and the control signal SNKr is supplied from the control circuit 26 to the gate of the NMOSFET 40.

  The second readout circuit 24-2 includes a PMOSFET 41 as a switch element, a sense amplifier SA, and a resistor Rf. The drain of the PMOSFET 41 is connected to the node N3, the source of the PMOSFET 41 is connected to the first input terminal (inverted input terminal) of the sense amplifier SA, and the control signal SRCr is supplied from the control circuit 26 to the gate of the PMOSFET 41. A reference voltage Vref is supplied to a second input terminal (non-inverting input terminal) of the sense amplifier SA. A resistor Rf is connected between the first input terminal and the output terminal of the sense amplifier SA. The sense amplifier SA outputs data read from the memory cell MC.

(Operation)
The operation of the MRAM configured as described above will be described. First, the data write operation of the MRAM will be described. When writing to the MTJ element 10 of the selected memory cell MC from the low resistance state to the high resistance state, recording is performed from the reference layer 14 using the constant current generated by the first writing circuit 23-1. A write current directed to the layer 12 is passed through the MTJ element 10.

  Specifically, the first bit line BL1 selected by the first bit line selection circuit 21-1 is connected to the node N1, and the second bit selected by the second bit line selection circuit 21-2. Line BL2 is connected to node N4. Further, the selected word line WL is set to the high level, and the selection transistor ST connected to the selected word line WL is turned on.

  Subsequently, both the control signals SRCn and SNKn are set to a low level, the PMOSFET 35 is turned on, and the NMOSFET 36 is turned off. Further, both the control signals SRCs and SNKs are set to the high level, the PMOSFET 38 is turned off, and the NMOSFET 39 is turned on. The NMOSFET 39 and the ground terminal VSS function as a current sink. As a result, a write current is supplied from the constant current power supply 34 to the MTJ element 10, and the MTJ element 10 is set from the low resistance state to the high resistance state.

  On the other hand, when writing from the high resistance state to the low resistance state for the MTJ element 10 of the selected memory cell MC, the recording layer 12 is generated using the constant voltage generated by the second writing circuit 23-2. A write current from to the reference layer 14 is passed through the MTJ element 10.

  Specifically, both control signals SRCs and SNKs are set to a low level, PMOSFET 38 is turned on, and NMOSFET 39 is turned off. Further, both the control signals SRCn and SNKn are set to the high level, the PMOSFET 35 is turned off, and the NMOSFET 36 is turned on. The NMOSFET 36 and the ground terminal VSS function as a current sink. The selection operation of the bit line and the word line is the same as when writing from the low resistance state to the high resistance state. As a result, a write current is supplied from the constant voltage power supply 37 to the MTJ element 10, and the MTJ element 10 is set from the high resistance state to the low resistance state.

  Next, the data read operation of the MRAM will be described. In the data read operation, a read current from the reference layer 14 toward the recording layer 12 is supplied to the MTJ element 10 of the selected memory cell MC using the constant voltage generated by the second read circuit 24-2. The read current is set to a value smaller than the write current.

  Specifically, the second bit line BL2 selected by the first bit line selection circuit 21-1 is connected to the node N2, and the first bit selected by the second bit line selection circuit 21-2. Line BL1 is connected to node N3. Further, the selected word line WL is set to the high level, and the selection transistor ST connected to the selected word line WL is turned on.

  Subsequently, the control signal SNKr is set to the high level, the control signal SRCr is set to the low level, and both the NMOSFET 40 and the PMOSFET 41 are turned on. The NMOSFET 40 and the ground terminal VSS function as a current sink. Since the first input terminal and the second input terminal of the sense amplifier SA have the same potential, that is, the reference voltage Vref, the voltage of the first input terminal of the sense amplifier SA, that is, the second readout circuit 24-2. The generated constant voltage is applied to the memory cell MC. That is, the sense amplifier SA also functions as a constant voltage power source. As a result, a read current flows through the MTJ element 10 in the direction from the reference layer 14 toward the recording layer 12, and data corresponding to the resistance of the MTJ element 10 is output from the sense amplifier SA.

  In the case of a circuit configuration in which the reference layer 14 is connected to the selection transistor ST, the recording layer 12 is connected to the second bit line BL2, and the selection transistor ST is connected to the first bit line BL1. This configuration example corresponds to an MTJ element having a structure in which the recording layer 12 is disposed above the reference layer 14. Even in this case, the above-described read operation and write operation are possible.

  In addition, after data is written to the memory cell, a verify read operation for confirming whether or not the data is correctly written is executed. This verify read operation is the same as the read operation of the present embodiment described above. Also in the verify read operation, a read operation using a constant voltage power supply can be applied.

[3-2. Second embodiment]
FIG. 11 is a circuit diagram showing the configuration of the bit line selection circuit 21, the write circuit 23, and the read circuit 24 according to the second embodiment. The second embodiment differs from the first embodiment in the circuit configuration of the read circuits 24-1 and 24-2, and accordingly, the destinations of the control signals SRCr and SNKr from the control circuit 26 are reversed. However, except for these points, the block diagram of the MRAM according to the second embodiment is the same as FIG.

  The first readout circuit 24-1 includes a constant current power source 42, a sense amplifier SA, and a PMOSFET 43 as a switch element. The source of the PMOSFET 43 is connected to the constant current power source 42, the drain of the PMOSFET 43 is connected to the node N 2, and the control signal SRCr is supplied from the control circuit 26 to the gate of the PMOSFET 43. A first input terminal (inverting input terminal) of the sense amplifier SA is connected to the constant current source 42, and a reference voltage Vref is supplied to a second input terminal (non-inverting input terminal) of the sense amplifier SA. . The sense amplifier SA compares the voltages at the first input terminal and the second input terminal to output data read from the memory cell MC.

  The second readout circuit 24-2 includes an NMOSFET 44 as a switch element. The drain of the NMOSFET 44 is connected to the node N 3, the source of the NMOSFET 44 is grounded, and the control signal SNKr is supplied from the control circuit 26 to the gate of the NMOSFET 44.

(Operation)
The operation of the MRAM configured as described above will be described. In the data read operation, a read current from the recording layer 12 toward the reference layer 14 is supplied to the MTJ element 10 of the selected memory cell MC using the constant current generated by the first read circuit 24-1.

  The selection operation of the bit line and the word line is the same as that at the time of reading in the first embodiment. Subsequently, the control signal SRCr is set to a low level, the control signal SNKr is set to a high level, and both the PMOSFET 43 and the NMOSFET 44 are turned on. The NMOSFET 44 and the ground terminal VSS function as a current sink. As a result, a read current from the recording layer 12 toward the reference layer 14 flows through the MTJ element 10 by the constant current power source 42. At this time, the sense amplifier SA compares the voltages of the two input terminals and outputs data corresponding to the resistance of the MTJ element 10.

  The configuration and operation of the write circuit 23 are the same as those in the first embodiment. As in the first embodiment, a read operation using a constant current power source can also be applied in the verify read operation.

[4. effect]
As described above in detail, in the present embodiment, (1) writing is performed by energizing in the direction in which the spin torque is applied from the parallel state to the antiparallel state, that is, writing current from the reference layer 14 toward the recording layer 12 is changed to MTJ. A constant current power supply is used when data is written by flowing through the element 10. (2) When writing is performed by energizing the anti-parallel state to the parallel state in the direction in which the spin torque acts, that is, when writing data by passing a write current from the recording layer 12 toward the reference layer 14 to the MTJ element 10 A constant voltage power supply is used. (3) When reading is performed by energizing in the direction in which spin torque works from the parallel state to the antiparallel state, that is, when reading data by passing a read current from the reference layer 14 toward the recording layer 12 to the MTJ element 10 A constant voltage power supply is used. (4) When reading is performed by energizing in the direction in which spin torque works from the antiparallel state to the parallel state, that is, when reading data by passing a read current from the recording layer 12 toward the reference layer 14 to the MTJ element 10 A constant current power supply is used.

  Therefore, according to the present embodiment, the write current flowing through the MTJ element 10 does not decrease during the write process, and thus write errors can be reduced. Also, write errors can be reduced without greatly increasing the write current. Further, since the read current flowing through the MTJ element 10 does not increase in the read process, read disturb can be reduced. As a result, an MRAM with high data reliability can be configured.

  The present invention is not limited to the above embodiment, and can be embodied by modifying the constituent elements without departing from the scope of the invention. Further, the above embodiments include inventions at various stages, and are obtained by appropriately combining a plurality of constituent elements disclosed in one embodiment or by appropriately combining constituent elements disclosed in different embodiments. Various inventions can be configured. For example, even if some constituent elements are deleted from all the constituent elements disclosed in the embodiments, the problems to be solved by the invention can be solved and the effects of the invention can be obtained. Embodiments made can be extracted as inventions.

  DESCRIPTION OF SYMBOLS 10 ... MTJ element, 11 ... Lower electrode, 12 ... Recording layer, 13 ... Nonmagnetic layer, 14 ... Reference layer, 15 ... Upper electrode, 20 ... Memory cell array, 21 ... Bit line selection circuit, 22 ... Column decoder, 23 ... Write circuit, 24 ... Read circuit, 25 ... Row decoder, 26 ... Control circuit, 30 to 33, 36, 39, 40, 44 ... NMOSFET, 34,42 ... Constant current power supply, 35, 38, 41, 43 ... PMOSFET, 37: constant voltage power supply, MC: memory cell, WL: word line, BL: bit line, ST: selection transistor, SA: sense amplifier, Rf: resistance.

Claims (5)

A magnetoresistive element having a reference layer whose magnetization direction is invariable, a recording layer whose magnetization direction is variable, and a nonmagnetic layer sandwiched between the reference layer and the recording layer;
A first write circuit for supplying a write current to the magnetoresistive element using a constant current power supply when setting the magnetization arrangement of the magnetoresistive element from parallel to antiparallel;
A second write circuit for supplying a write current to the magnetoresistive element using a constant voltage power supply when setting the magnetization arrangement of the magnetoresistive element from antiparallel to parallel;
A magnetic memory comprising: A first bit line connected to one end of the magnetoresistive element;
A selection transistor having one end of a current path connected to the other end of the magnetoresistive element;
A second bit line connected to the other end of the current path of the selection transistor;
Further comprising
2. The magnetic memory according to claim 1, wherein each of the first and second write circuits is connected to the first and second bit lines. The first write circuit includes a first current sink that draws a current from the constant current power source;
The magnetic memory according to claim 2, wherein the second write circuit includes a second current sink that draws a current from the constant voltage power source.   When reading data from the magnetoresistive element, the apparatus further comprises a read circuit that uses a constant voltage power supply to flow a read current in a direction in which a spin torque is applied from parallel to antiparallel to the magnetoresistive element. The magnetic memory according to claim 1.   When reading data from the magnetoresistive element, the apparatus further comprises a read circuit that uses a constant current power source to flow a read current in a direction in which a spin torque acts on the magnetoresistive element from antiparallel to parallel. The magnetic memory according to claim 1.

Images