CN110632975B

CN110632975B - Sequence signal generation method and device

Info

Publication number: CN110632975B
Application number: CN201910880596.1A
Authority: CN
Inventors: 朱明东; 秦熙; 张闻哲; 仝煜; 王淋; 荣星; 杜江峰
Original assignee: University of Science and Technology of China USTC
Current assignee: University of Science and Technology of China USTC
Priority date: 2019-09-18
Filing date: 2019-09-18
Publication date: 2022-09-06
Anticipated expiration: 2039-09-18
Also published as: CN110632975A

Abstract

The invention provides a sequence signal generating method and a device, wherein the scheme acquires waveform setting information; the waveform setting information comprises logic level, period number and target delay parameters; obtaining the configuration combination of the delay units of each level of delay chain corresponding to the target delay parameter from a preset correction table; the delay chains at each stage are positioned in the time adjusting module; configuring each level of delay chain in the time adjusting module according to the configuration combination of the delay units corresponding to the target delay parameters; and generating an original sequence signal according to the period number and the logic level, and transmitting the original sequence signal to a time adjusting module to obtain a first sequence signal. According to the invention, the configuration combination of the delay units of each stage of the delay chain with the actual delay closest to the expected delay is obtained through the preset correction table, so that the nonlinear influence of each stage of the delay chain is reduced, and the deviation between the output sequence signal and the target sequence signal is reduced.

Description

Sequence signal generation method and device

Technical Field

The present invention relates to the field of timing control technologies, and in particular, to a method and an apparatus for generating a sequence signal.

Background

In recent years, with the rapid development of electronic science and technology and related research fields, the precision requirement of advanced scientific research fields such as aerospace, communication, automatic control, electronic precision instruments, basic physics, even medical biology and the like on time sequence control is higher and higher. The high-precision timing control can be realized by a high-precision serial signal which is a serial signal formed by specifically arranging 0/1 binary codes. In the prior art, a sequence signal can be generated by a time interpolation method, in which a delay unit with higher time precision than that of a clock cycle is interpolated in the clock cycle to obtain a sequence signal with the same time precision as that of the delay unit.

However, in application, there may be a deviation between the actual delay of the interpolated delay unit and the target expected delay, so that a delay chain formed by the interpolated delay unit has nonlinearity, which increases the deviation between the output sequence signal and the target sequence signal and affects the accuracy of timing control.

Disclosure of Invention

In view of this, embodiments of the present invention provide a method and an apparatus for generating a sequence signal to reduce the effect of the delay chain nonlinearity, so as to achieve the purpose of reducing the deviation between the output sequence signal and the target sequence signal.

The technical scheme is as follows:

one aspect of the present invention provides a sequence signal generating method, including:

acquiring waveform setting information; the waveform setting information is obtained according to time information of a target sequence signal and a clock cycle of a working clock of a sequence signal generator, and comprises a logic level, a cycle number and a target delay parameter;

obtaining a configuration combination of delay units of each level of delay chain corresponding to the target delay parameter from a preset correction table; the time delay chains at all levels are positioned in a time adjusting module, the preset correction table is obtained according to a nonlinear correction method, and the nonlinear correction method obtains the corresponding relation between different time delay parameters and the configuration combination of time delay units according to the actual time delay of the time adjusting module and the expected time delay corresponding to the different time delay parameters;

configuring each level of delay chain in the time adjusting module according to the configuration combination of the delay units corresponding to the target delay parameters;

and generating an original sequence signal according to the period number and the logic level, and transmitting the original sequence signal to the time adjusting module to obtain a first sequence signal output after the delay action of each stage of delay chain in the time adjusting module.

Further, the nonlinear correction method is an integral nonlinear correction method, and obtaining the corresponding relationship between different delay parameters and configuration combinations of the delay units by the integral nonlinear correction method includes:

combining the delay units among the delay chains according to the configurable number of the delay units of each level of delay chain to obtain various configuration combinations (n) of the delay units among the delay chains ₁ ，n ₂ ，…，n _m ) Wherein n is _i The configuration number of the delay units in the ith level delay chain in the configuration combination is N _i A delay unit, then n _i ∈[0，N _i ]，i∈[1，m]，m≥2，n _i I and m are integers;

according to the various configuration combinations, obtaining the corresponding relation (t (n)) of the various configuration combinations and the actual time delay of the time adjusting module ₁ ，n ₂ ，…，n _m )，n ₁ ，n ₂ ，…，n _m )，n _i ∈[0，N _i ]，i∈[1，m](ii) a Wherein, t (n) ₁ ，n ₂ ，…，n _m ) Is a configuration combination of delay units of (n) ₁ ，n ₂ ，…，n _m ) Actual time delay of the time adjustment module;

according to the preset value range of the delay series a and the time precision t _s Obtaining expected delays t corresponding to different delay levels a _I (a) Satisfy t _I (a)＝a×t _s (ii) a Wherein a is more than or equal to 0 and less than or equal to T/T _s A is an integer and T is the clock period; the delay parameter comprises the delay series a or the expected delay t _I (a) (ii) a Said time precision t _s Is the average unit delay t of the delay units according to the m-th stage delay chain _m ' and expected unit delay t of delay unit of said m-th stage delay chain _m Determined by the average unit delay t _m ’＝(t(0，0，…，N _m )-t(0，0，…，0))/N _m ，N _m For delay of m-th stage delay chainA configurable maximum number of units;

according to the corresponding relation (t (n) ₁ ，n ₂ ，…，n _m )，n ₁ ，n ₂ ，…，n _m ) Respectively selecting the actual time delay t of the time adjustment unit _set (a) Satisfy t _set (a)→t _I (a)，0≤a≤T/t _s The configuration combination of the delay units of each stage of delay chain (n) _1a ，n _2a ，…，n _ma ) (ii) a Thereby obtaining different delay levels a and the configuration combination (n) _1a ，n _2a ，…，n _ma ) (a), (n) of (c) _1a ，n _2a ，…，n _ma ) Or a different desired delay t) _I (a) And the configuration combination (n) _1a ，n _2a ，…，n _ma ) Corresponding relation (t) _I (a)，(n _1a ，n _2a ，…，n _ma ) ); wherein, t is _set (a) In combination with said configuration (n) _1a ，n _2a ，…，n _ma ) The corresponding actual delay.

Further, the nonlinear correction method is a differential nonlinear correction method, and obtaining the corresponding relationship between different delay parameters and configuration combinations of delay units by the differential nonlinear correction method includes:

according to the various configuration combinations, obtaining the corresponding relation (t (n)) of the various configuration combinations and the actual time delay of the time adjusting module ₁ ，n ₂ ，…，n _m )，n ₁ ，n ₂ ，…，n _m )，n _i ∈[0，N _i ]，i∈[1，m](ii) a Wherein, t (n) ₁ ，n ₂ ，…，n _m ) Is a configuration combination of delay units as (n) ₁ ，n ₂ ，…，n _m ) Actual time delay of the time adjustment module;

according to the preset value range of the delay series a and the time precision t _s Obtaining expected delays t corresponding to different delay levels a _D (a) Satisfy t _D (a)＝t _set (a-1)+t _s (ii) a Wherein a is more than or equal to 0 and less than or equal to a _max A is a positive integer, a _max To satisfy inequality t _set (a) A maximum integer value of a when T is less than or equal to T, wherein T is the clock period; t is t _set (a-1) is the desired delay t _D (a-1) the closest actual delay, t, of said time adjustment module _set (a) To be delayed by t _D (a) The closest actual delay of the time adjustment module; said time accuracy t _s Is the average unit delay t of the delay units according to the m-th stage delay chain _m ' and expected unit delay t of delay unit of m-th stage delay chain _m Determined, said average unit delay t _m ’＝(t(0，0，…，N _m )-t(0，0，…，0))/N _m ，N _m A configurable maximum number of delay units for the mth stage delay chain;

according to the corresponding relation (t (n) ₁ ，n ₂ ，…，n _m )，n ₁ ，n ₂ ，…，n _m ) Selecting the actual time delay t of the time adjustment unit respectively _set (a) Satisfy t _set (a)→t _D (a)，0≤a≤a _max The configuration combination of the delay units of each stage of delay chain (n) _1a ，n _2a ，…，n _ma ) (ii) a So as to obtain the corresponding relation (a, (n) of different delay series a and the configuration combination _1a ，n _2a ，…，n _ma ) Or a different desired delay t) _D (a) And the configuration combination (n) _1a ，n _2a ，…，n _ma ) Corresponding relation (t) _D (a)，(n _1a ，n _2a ，…，n _ma ) Wherein, the t _set (a) In combination with said configuration (n) _1a ，n _2a ，…，n _ma ) The corresponding actual delay.

Further, the nonlinear correction method includes an integral nonlinear correction method and a differential nonlinear correction method; the waveform setting information also comprises a method identifier for indicating that a correction method is currently adopted;

the obtaining of the configuration number of the delay units of each level of the delay chain corresponding to the target delay parameter from the preset correction table includes:

and acquiring the configuration combination of the delay units of each level of delay chain corresponding to the method identification and the target delay parameter from the preset correction table.

Further, the configuring the delay chains of each stage in the time adjustment module includes:

and determining the number of delay units used for delaying in each stage of delay chain in the time adjusting module according to the configuration combination of the delay units of each stage of delay chain corresponding to the target delay parameter.

Further, the method also comprises the following steps: and updating the preset correction table.

Another aspect of the present invention provides a sequence signal generating apparatus, including: the device comprises a time adjusting module and an original sequence signal generating module; wherein, the first and the second end of the pipe are connected with each other,

the original sequence signal generating module is used for acquiring the number of cycles in waveform setting information, the logic level in the waveform setting information and a working clock of the sequence signal generator; generating an original sequence signal according to the period number, the logic level and the working clock, and transmitting the original sequence signal to the time adjusting module; the waveform setting information is obtained according to time information of a target sequence signal and a clock cycle of the working clock, and comprises cycle number and a target delay parameter;

the time adjustment module includes: the device comprises a correction submodule and an interpolation submodule, wherein the interpolation submodule comprises at least two stages of delay chains; wherein the content of the first and second substances,

the correction submodule is used for acquiring a target delay parameter in the waveform setting information; obtaining the configuration combination of the delay units of each level of the delay chain of the interpolation sub-module corresponding to the target delay parameter from a preset correction table; sending the configuration combination of the delay units to the interpolation submodule; the preset correction table is obtained according to a nonlinear correction method, and the nonlinear correction method obtains the corresponding relation between different delay parameters and configuration combinations of delay units according to the actual delay of the time adjusting module and expected delays corresponding to the different delay parameters;

the interpolation sub-module is used for configuring the delay chains at all levels according to the configuration combination of the delay units corresponding to the target delay parameters; and receiving the original sequence signal sent by the original sequence signal generation module, and outputting the first sequence signal after the original sequence signal sequentially passes through the delay action of each stage of delay chain.

Further, the interpolation sub-module includes: the system comprises a multi-stage delay chain and a multiplexer, wherein each stage of delay chain is connected with one multiplexer;

the multiplexer is used for determining the number of the delay units used for delaying in the delay chains connected with the multiplexer according to the configuration combination of the delay units of each level of delay chains corresponding to the target delay parameters, and gating the delay units used for delaying in the delay chains connected with the multiplexer;

any stage of delay chain in the multi-stage delay chain is used for receiving the sequence signal output by the previous stage of delay chain, delaying the sequence signal output by the previous stage of delay chain through the gated delay unit in the stage of delay chain to obtain the sequence signal output by the stage of delay chain, and transmitting the sequence signal to the next stage of delay chain; and the first-stage delay chain in the multi-stage delay chains receives the original sequence signal, and the level conversion time of the original sequence signal is delayed through the gated delay unit in each stage of delay chain, so that the last-stage delay chain in the multi-stage delay chains outputs the first sequence signal.

Further, the original sequence signal generating module comprises a waveform playing unit and a counting unit;

the counting unit is used for acquiring the cycle number and the working clock in the waveform setting information, and sending a counting completion signal to the waveform playing unit when the time for the waveform playing unit to continuously play the level signal reaches the cycle number of clock cycles;

and the waveform playing unit is used for acquiring the logic level in the waveform setting information, playing a level signal corresponding to the logic level, and converting the level signal at the edge of the working clock to generate an original sequence signal when receiving the counting completion signal.

Further, the system further comprises an updating module, configured to update the preset fix-up table.

Based on the technical scheme, waveform setting information is obtained; the waveform setting information is obtained according to time information of a target sequence signal, and comprises a logic level, a period number and a target delay parameter; obtaining the configuration combination of the delay units of each level of delay chain corresponding to the target delay parameter from a preset correction table; the delay chains at each stage are positioned in the time adjusting module; configuring each level of delay chain in the time adjusting module according to the configuration combination of the delay units corresponding to the target delay parameters; and generating an original sequence signal according to the period number and the logic level, and transmitting the original sequence signal to the time adjusting module to obtain a first sequence signal output after the delay action of each stage of delay chain in the time adjusting module. Compared with the prior art, the preset correction table is obtained according to a nonlinear correction method, the nonlinear correction method obtains the corresponding relation between different delay parameters and the configuration combination of the delay units according to the actual delay of the time adjustment module and the expected delay corresponding to the different delay parameters, and after the target delay parameter matched with the target sequence signal is obtained, the configuration combination of the delay units corresponding to (i.e. matched with) the target delay parameter can be obtained from each corresponding relation in the preset correction table, so that the nonlinear influence of each stage of delay chain is reduced, and the output first sequence signal is closer to the target sequence signal.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the prior art descriptions will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.

FIG. 1 is a flow chart of a method for generating a sequence signal according to an embodiment of the present invention;

FIG. 2 is a waveform diagram illustrating a target expected delay obtained from a target sequence signal according to the present invention;

FIG. 3 is a flowchart illustrating an integral non-linear correction method in a sequence signal generation method according to an embodiment of the present invention;

FIG. 4 is a flowchart of a differential non-linear correction method in a sequence signal generation method according to an embodiment of the present invention;

fig. 5 is a schematic waveform diagram illustrating an i-th stage delay chain delay effect in a sequence signal generation method according to an embodiment of the present invention;

FIG. 6 is a flowchart illustrating a method for generating a sequence signal according to another embodiment of the present invention;

FIG. 7 is a flowchart illustrating a method for generating a sequence signal according to another embodiment of the present invention;

fig. 8 is a schematic structural diagram of a sequence signal generating apparatus according to yet another embodiment of the present invention;

fig. 9 is a schematic structural diagram of a serial signal transmitter according to yet another embodiment of the present invention.

Detailed Description

The existing sequence signal generator adopts a single-stage time interpolation method or a two-stage time interpolation method, the sequence signal generator adopting the single-stage time interpolation method comprises a single-stage delay chain, and the sequence signal generator adopting the two-stage time interpolation method comprises a two-stage delay chain.

Although the sequence signal generator adopting the single-stage time interpolation method has a simple structure, under the design index of high time precision, the difficulties of too many delay units and power consumption increase can be faced, and in addition, the consistency of delay stepping of each delay unit is not easy to be ensured by too many delay units.

Compared with a single-stage time interpolation method, the sequence signal generator adopting the two-stage time interpolation method effectively reduces the number of required delay units under the condition of reaching the same time precision. However, the two-stage time interpolation method may use a larger number of delay units under the design criterion of higher time precision.

The sequence signal generator comprises a multi-stage time delay chain, and on the basis of a two-stage time interpolation method, the number of stages (such as three-stage and more than three-stage delay chains) of the delay chain can be further increased according to time precision, so that the number of delay units required for realizing the same time precision as the two-stage time interpolation method is reduced. For example, in the case of interpolating the delay units to a time precision of 0.1ps for the working clock of 5ns, when the same precision as that of the two-stage time interpolation method is achieved, only 60 delay units need to be used by adopting the four-stage time interpolation method (i.e., the sequence signal generator includes a four-stage delay chain), and the number of delay units is obviously reduced.

However, in practical applications, it is found that it is difficult to keep the unit delays of the delay units of each stage of the delay chain consistent, which results in significant nonlinearity problems, for example, in the actually applied sequence signal generator, there are 224 delay units with unit delay of 0.1ps, and for various reasons, there are delay units with unit delay greater than 0.1ps or less than 0.1 ps; the same problem exists with 224 delay cells with 22.4ps unit delay. The delay deviation of each stage of delay chain in the multi-stage delay chain is transferred step by step, so that the nonlinear problem of the multi-stage delay chain is more obvious. The non-linearity problem of the delay chain causes deviation between the sequence signal output by the sequence signal generator and the target sequence signal, so that the accuracy of time control of the sequence signal generator is poor.

In order to solve the nonlinear problem, the sequence signal generation method and the sequence signal generator provided by the invention obtain the configuration combination of the delay units of each stage of delay chain with the closest actual delay and expected delay through the preset correction table, thereby reducing the nonlinear influence of each stage of delay chain and reducing the deviation between the output sequence signal and the target sequence signal. Meanwhile, the sequence signal generator can use two or more stages of delay chains according to the time precision requirement so as to reduce the number of delay units and reduce the single-channel realization cost and power consumption.

The invention provides a sequence signal generating method and a device, which can be applied to the fields of aerospace, communication, automatic control, electronic precision instruments, basic physics, even medical biology and the like. The sequence signal generator is realized by adopting a multi-stage time interpolation method with two or more stages.

Before describing the sequence signal generating method and the sequence signal generator provided by the present invention, the terms involved will be explained:

time accuracy t _s Indicating the minimum time scale that the time adjustment block in the sequence signal generator can adjust, typically in terms of the average unit delay t of the delay units of the last stage delay chain in the time adjustment block _m ' and expected unit delay t of delay unit of last stage delay chain _m Determination of t _m ' and t _m The last stage of delay chain is represented as the mth stage of delay chain, and m is an integer greater than or equal to 2.

Desired unit delay t _i In order to realize the theoretical unit delay of the delay unit of the ith stage delay chain in the design stage of the sequence signal generator, the unit delay of each delay unit in the ith stage delay chain is considered to be consistent and equal to t _i ；t _i Decreases with increasing i, and the total number N of delay units of the i-th stage delay chain _i And t _i The relation between them satisfies inequality (1+ N) _i )·t _i ≥t _i-1 ，i∈[1，m]，t ₀ Equal to the clock period T.

However, when the sequence signal generator is actually implemented, the actual unit delay of the delay units of each stage of delay chain is not uniform, the actual total number of the delay units of each stage of delay chain is larger than the theoretically required number calculated in the design stage, and a certain margin is left to prevent the occurrence of non-adjustable 'blind areas' due to the fact that the actual unit delay of some delay units is too large. For example, the expected unit delay t of the delay cells of the first stage delay chain ₁ 0.1s, the expected unit delay t of the delay unit of the second stage delay chain ₁ 0.01s, if substituting the inequality (1+ N) _i )·t _i ≥t _i-1 The total number N of the second stage delay units can be obtained ₂ Not less than 9. In an actual situation, a delay unit with an actual unit delay larger than 0.1, for example, a delay unit with an actual unit delay of 0.15s, may exist in the first-stage delay chain, and at this time, if the second-stage delay chain has only 9 delay units, the "blind zone" between 0.1s and 0.15s cannot be adjusted; if the second-stage delay unit has a margin in design, for example, 14 delay units are provided to avoid the occurrence of "blind areas". Usually, at the beginning of design, the maximum deviation of the actual unit delay of the delay unit from the expected unit delay is estimated, and a sufficient margin is reserved.

Delay t of mean unit _i ' the actual unit delay of the delay unit of the i-th stage delay chain is calculated after the sequence signal generator is manufactured and in actual application, and the actual unit delay can be calibrated by a formula t in the sequence signal generator _i ’＝(t(0，…，N _i ，…，0)-t(0，…，0，…，0))/N _i Is calculated to obtain, wherein N _i For the total number of delay units of the ith stage delay chain, i belongs to [1, m ]]。

Mean unit delay t _m ' the actual unit delay of the delay unit of the last stage delay chain is calculated as follows: t is t _m ’＝(t(0，0，…，N _m )-t(0，0，…，0))/N _m (ii) a Time accuracy t _s May be equal to the average unit delay t _m ' or may be selected to be similarMean unit delay t _m Value of' because of the average unit delay t _m The value of' may exist in multiple decimal places, and may incorporate a desired unit delay t to reduce the amount of unnecessary computation _m Selecting an approximate average unit delay t _m Time accuracy t of ` _s 。

The target sequence signal is a sequence signal expected to be output by the sequence signal generator and consists of a series of high-level and low-level signals, the target sequence signal realizes the time sequence control of other devices or systems through time intervals of high and low levels, and the time intervals of the high voltage and the low level can be different or the same according to different use scenes. The time interval of the high and low levels of the sequence signal actually output by the sequence signal generator is as close to the target sequence signal as possible.

High level duration t of target sequence signal _H The time duration of the high level signal in the target sequence signal is part of the time information of the target sequence signal.

Low level duration t of target sequence signal _L The time duration of the low level signal in the target sequence signal is part of the time information of the target sequence signal.

And the logic level is used for indicating whether the current target sequence signal is in a high level or a low level.

The clock period T is the period of the operating clock used to synchronize the sequence signal generator.

Number of cycles P, representing the number of clock cycles into which the level signal has been advanced in duration, according to t _H Or t _L And (4) calculating. Number of cycles P _i And represents the number of clock cycles that the level signal duration of the ith segment of the target sequence signal has passed.

Target desired delay t _G When the target sequence signal is generated, the expected delay that the actual delay of the time adjustment module needs to approach is the target expected delay. Target desired delay t _Gi Indicating that the actual delay of the time adjustment module needs to be approached when generating the level signal of the ith waveform of the target sequence signalThe expected delay is a target expected delay.

The number of cycles P _i And target desired delay t _Gi The calculation formula of (c) is:

if the ith waveform of the target sequence signal is high,

wherein, here "

"denotes a downward integer, i.e. P _i P is not more than (t) _H +t _G(i-1) ) The largest integer of/T; if the ith waveform of the target sequence signal is low,

P _i p is an integer greater than or equal to 0. Wherein t is _G(i-1) The delay is expected for the target for the ith waveform of the target sequence signal.

If the ith segment of the target sequence signal has high level, t _Gi ＝t _G(i-1) +t _H -P _i T, if the ith segment of the target sequence signal has a low level, T _Gi ＝t _G(i-1) +t _L -P _i T. Wherein the target expected delay t of the target sequence signal of the previous moment _G(i-1) The target expected delay is the ith waveform of the target sequence signal; general setting t _G0 ＝0。

Target delay progression a, a ═ t _G /t _s ]Is a delay progression, where "[ alpha ], [ alpha ] is a time-delay progression]"denotes an integer that is closest to the value in parentheses, i.e. A is closest to t _G /t _s Is an integer of (1).

The delay series a is [0, T/T ] when the nonlinear correction method is an Integral Non-linear (INL) correction method _s ]An integer within the range; when the nonlinear correction method is a Differential Non-Linearity (DNL) correction method, a is more than or equal to 0 and less than or equal to a _max A is a positive integer, a _max To satisfy inequality t _set (a) Maximum integer of a when T is less than or equal toValue, t _set (a) To be delayed by t _D (a) The actual delay of the closest time adjustment module.

Desired delay t _I (a) The ideal delay time of the time adjustment module corresponding to the delay order a when the nonlinear correction method is the INL correction method satisfies t _I (a)＝a×t _s ；

Desired delay t _D (a) The ideal delay time of the time adjustment module corresponding to the delay progression a when the nonlinear correction method is the DNL correction method satisfies t _D (a)＝t _set (a-1)+t _s ，t _set (a-1) is the desired delay t _D (a-1) actual delays of the nearest time adjustment modules.

Actual delay t (n) ₁ ，n ₂ ，…，n _m ) The configuration combination of the delay units is (n) ₁ ，n ₂ ，…，n _m ) And the actual delay time of the time adjusting module.

Actual time delay t _set (a) The configuration combination of the delay units is (n) _1a ，n _2a ，…，n _ma ) And the actual delay time of the time adjusting module. When the nonlinear correction method is an INL correction method, (n) _1a ，n _2a ，…，n _ma ) To delay the actual time t _set (a)→t _I (a)，0≤a≤T/t _s Wherein the symbol "→" represents approach, i.e., t → ", to each stage of the delay chain delay cell configuration combination _set (a)→t _I (a) Representing the actual delay t _set (a) To be closest to the desired delay t _I (a) By configuring a combination of (n) _1a ，n _2a ，…，n _ma ) Obtaining the actual time delay of the time adjusting module; when the nonlinear correction method is a DNL correction method, (n) _1a ，n _2a ，…，n _ma ) To delay (t) the reality _set (a)-t _set (a-1))→t _s ，0≤a≤a _max (i.e., t) _set (a)→t _D (a) ) configuration combinations of delay chain delay units of each stage.

Configuration combination (n) ₁ ，n ₂ ，…，n _m ) Is to eachCombinations of the number of configurations of delay cells of a stage delay chain, where n _i The configuration number of the delay units in the ith stage delay chain in the configuration combination is n _i ∈[0，N _i ]，i∈[1，m]，m≥2，n _i I and m are integers.

The delay parameters include the delay order a, the expected delay (i.e. t) _I (a) Or t _D (a) T), the actual delay time t _set (a) Or else may be combined with different configurations (n) _1a ，n _2a ，…，n _ma ) And parameters are in one-to-one correspondence.

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

In this application, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. The term "comprising", without further limitation, means that the element so defined is not excluded from the group consisting of additional identical elements in the process, method, article, or apparatus that comprises the element.

Referring to fig. 1, a flowchart of a method for generating a sequence signal according to an embodiment of the present invention is shown, where the method includes the following steps:

s101, acquiring waveform setting information.

In this step, the waveform setting information is obtained according to the time information of the target sequence signal and the clock period T of the operating clock of the sequence signal generator, and the waveform setting information includes the period number P, the logic level, and the target delay parameter. The clock period T is adopted in the embodimentPeriod T of the operating clock of the sequence signal generator of method. The target delay parameter is a parameter indicating a time relationship between the target sequence signal and the original sequence signal, and is the same as the delay parameter in the preset correction table. The target delay parameter can be a target delay progression A or a target expected delay t _G When the preset correction table includes a plurality of delay stages a and configuration combinations (n) _1a ，n _2a ，…，n _ma ) In the corresponding relation, the obtained target delay parameter is a target delay stage A; when the predetermined correction table includes a plurality of desired delay and configuration combinations (n) _1a ，n _2a ，…，n _ma ) Or a plurality of actual delays and configuration combinations (n) _1a ，n _2a ，…，n _ma ) In the corresponding relation, the target delay parameter is obtained as the target expected delay t _G 。

The time information of the target sequence signal comprises a high level duration t _H And/or low level duration t _L . The period number P, the logic level and the target delay parameter in the waveform setting information can be obtained by an upper computer, a sequence signal generator or other processing devices according to the time information of the target sequence signal under the working clock.

An example of obtaining waveform setting information based on time information of a target sequence signal is described below with reference to fig. 2: assuming that the clock period T is 1s, the time precision T _s The target sequence signal is a high level signal for 2.5s, then is inverted to a low level signal for 2.5s, as shown in fig. 2. The first section of the target sequence signal is a high level signal, and the corresponding time information is high level duration t _H The second segment of the target sequence signal has a low level signal with corresponding time information of low level duration t 2.5s _L 2.5 s. When a first section of waveform of a target sequence signal is generated, the logic level is high level; let t be _G0 At s, as shown in fig. 2, according to the formula for calculating the number of cycles (see the description of the terms specifically),

calculation of the desired delay according to the target, t _G1 0+2.5-2 × 1-0.5 s; according to the formula of calculating the target delay progression, A ₁ ＝[0.5/0.1](ii) 5; the first waveform, i.e. the high level duration t, of the target sequence signal can be obtained _H The waveform setting information corresponding to 2.5s includes: number of cycles P ₁ 2, the target delay parameter is the target expected delay t _G1 0.5s or target delay progression a ₁ ＝5。

When a second section of waveform of the target sequence signal is generated, the logic level is a low level; the original sequence signal jumps to low level, the signal edge is a falling edge, and the target sequence signal generates a falling edge after 0.5s _G1 0.5s, as shown in fig. 2, according to the calculation formula of the number of cycles,

from the calculation of the target desired delay, t _G2 0.5+2.5-3 × 1 ═ 0 s; according to the formula of the calculation of the target delay progression, A ₂ ＝[0/0.1]0; obtaining a second waveform, i.e. low level duration t, corresponding to the target sequence signal _L The waveform setting information corresponding to 2.5s is: number of cycles P ₂ 3, the target delay parameter is the target expected delay t _G2 0s or target delay progression a ₂ 0. The target delay parameter is selected according to a delay parameter in a preset correction table.

S102, obtaining the configuration combination (n) of the delay units of each level of delay chain corresponding to the target delay parameter from the preset correction table _1A ，n _2A ，…，n _mA )。

The method comprises the following steps of correcting nonlinearity of each level of delay chain through a preset correction table, wherein the preset correction table can be downloaded into a sequence signal generator in advance, real-time correction is realized through the sequence signal generator, the preset correction table can also be placed in an upper computer, and the upper computer sends configuration combination of delay units of each level of delay chain in the preset correction table to the sequence signal generator.

In this step, each stage of delay chain is a structure for delaying time in the time adjustment module, and the delay chain can be equivalent to an interpolated delay chain formed by connecting a plurality of delay units in series. The preset correction table may include a plurality of pieces of correction data including a delay parameter and a configuration combination (n) of delay units of each stage of the delay chain corresponding to the delay parameter ₁ ，n ₂ ，…，n _m ) To obtain from these correction data a combination of configurations of delay units of each stage of the delay chain matching the target delay parameter (n) _1A ，n _2A ，…，n _mA )。

In this embodiment, the preset correction table may be obtained according to a nonlinear correction method, and the nonlinear correction method obtains a corresponding relationship between different delay parameters and configuration combinations of the delay units according to the actual delay of the time adjustment module and expected delays corresponding to the different delay parameters. The non-linear correction method is explained in detail as follows:

one implementation of the nonlinear correction method may adopt an INL correction method, please refer to fig. 3, which shows a flow of obtaining a corresponding relationship between different delay levels and configuration combinations of delay units by the INL correction method, and may include the following steps:

s201, combining the delay units among the delay chains according to the configurable number of the delay units of each level of delay chain to obtain various configuration combinations (n) of the delay units among the delay chains ₁ ，n ₂ ，…，n _m ) Wherein n is _i For configuring the configuration number of delay units in the ith stage delay chain in the combination, the ith stage delay chain has N _i A delay unit (i.e. the configurable data of the delay unit of the ith stage delay chain is N _i ) Then n is _i ∈[0，N _i ]，i∈[1，m]，m≥2，n _i I and m are integers.

S202, obtaining corresponding relation (t (n) between various configuration combinations and actual time delay of the time adjusting module according to the various configuration combinations ₁ ，n ₂ ，…，n _m )，n ₁ ，n ₂ ，…，n _m )，n _i ∈[0，N _i ]，i∈[1，m](ii) a Wherein t: (n ₁ ，n ₂ ，…，n _m ) Is a configuration combination of delay units as (n) ₁ ，n ₂ ，…，n _m ) The actual delay of the time adjustment module.

Steps S201 and S202 are calibration processes of the corresponding relationship of each stage of delay chain, taking two stages of delay chains as an example, assuming that the first stage of delay chain is provided with 10 delay units, and the second stage is provided with 20 delay units. The calibration process may take one of two forms, as described below.

One way is as follows: traversing different numbers of delay units in the first-stage delay chain to obtain the actual delay of the first-stage delay chain corresponding to the different numbers, namely obtaining the actual delay t of the first-stage delay chain when 1 delay unit is taken ₁ (1) (ii) a Obtaining the actual delay t of the first-stage delay chain when 2 delay units are available ₁ (2) (ii) a ... when 10 delay units are taken, the actual delay t of the first-stage delay chain is obtained ₁ (10). Similarly, traversing different numbers of delay units in the second-stage delay chain to obtain the actual delay t of the second-stage delay chain ₂ (j)，j∈[0，20]And j is an integer.

The first-stage delay chain and the second-stage delay chain are tested for 11+21 times in total, the unit delay of each delay unit of the first-stage delay chain and the unit delay of each delay unit of the second-stage delay chain and the average unit delay t of the first-stage delay chain are obtained through calibration ₁ ’＝t ₁ (10) 10 and average unit delay t of second-stage delay chain ₂ ’＝t ₂ (20) And/20, obtaining the actual delay t (n) of different configuration combinations of the delay units of each stage of delay chain by permutation and combination ₁ ，n ₂ )＝t ₁ (n ₁ )+t ₂ (n ₂ ) Therefore, the corresponding relation between various configuration combinations of the delay units of the two stages of delay chains and the actual delay of the time adjusting module is obtained.

The other mode is as follows: configuration combination (n) of delay units traversing two-stage delay chains ₁ ，n ₂ )，n ₁ ∈[0，10]，n ₂ ∈[0，20]Directly obtaining the actual time delay t (n) of the time adjusting module under different configuration combinations ₁ ，n ₂ ). The arrangement of the delay units of the first stage delay chain can be fixed firstA constant number n ₁ 0, the configuration number n of the delay units of the second-stage delay chain ₂ Respectively testing for 21 times from 0 to 20 to obtain the actual time delay t (0, n) of the time adjusting module ₂ )，n ₂ ∈[0，20](ii) a Then the configuration number of the delay units of the first-stage delay chain is increased by 1, n ₁ 1, traversing different configuration numbers of the delay units of the second-stage delay chain to obtain the actual delay t (1, n) of the time adjusting module ₂ )，n ₂ ∈[0，20](ii) a ... finally, the configuration number n of the delay units of the first stage delay chain is ensured ₁ And (10) traversing different configuration numbers of the delay units of the second-stage delay chain to obtain the actual delay t (10, n) of the time adjusting module ₂ )，n ₂ ∈[0，20]. The total number of times of 11 × 21 — 131 is tested, so that the corresponding relationship between various configuration combinations of the delay units of the two-stage delay chain and the actual delay of the time adjustment module is obtained. The average unit delay t of the first-stage delay chain and the second-stage delay chain can be obtained by calibration ₁ ’＝t(10，0)/10，t ₂ ’＝t(0，20)/20。

S203, according to the preset value range and the time precision t of the delay series a _s To obtain the expected delay t corresponding to different delay levels a _I (a) Satisfy t _I (a)＝a×t _s (ii) a Wherein a is more than or equal to 0 and less than or equal to T/T _s A is an integer and T is a clock period. The delay parameter comprises the delay series a or the expected delay t _I (a) (ii) a Time accuracy t _s Is the average unit delay t of the delay units according to the m-th stage delay chain _m Expected unit delay t of delay units of' and m-th stage delay chains _m The result is determined. With respect to time accuracy t _s Average unit delay t _m ' sum desired Unit delay t _m For explanation, refer to the foregoing description of terms.

S204, according to the corresponding relation (t (n) ₁ ，n ₂ ，…，n _m )，n ₁ ，n ₂ ，…，n _m ) The actual delay t of the time adjustment unit is selected separately _set (a) Satisfy t _set (a)→t _I (a)，0≤a≤T/t _s The configuration combination of the delay units of each stage of delay chain (n) _1a ，n _2a ，…，n _ma ) (ii) a Thereby obtaining different delay series a and configuration combinations (n) _1a ，n _2a ，…，n _ma ) (a), (n) of _1a ，n _2a ，…，n _ma ) Or to obtain different desired delays t) _I (a) And configuration combinations (n) _1a ，n _2a ，…，n _ma ) Corresponding relation (t) _I (a)，(n _1a ，n _2a ，…，n _ma )). The delay parameter can be the delay series a or the expected delay t _I (a) Or other combinations with the arrangement (n) _1a ，n _2a ，…，n _ma ) And parameters are in one-to-one correspondence.

Another implementation manner of the nonlinear correction method may adopt a DNL correction method, please refer to fig. 4, which shows a specific flowchart of the DNL correction method obtaining the corresponding relationship between different delay parameters and configuration combinations of delay units, and includes the following steps:

s301, combining the delay units among the delay chains according to the configurable number of the delay units of each level of delay chain to obtain various configuration combinations (n) of the delay units among the delay chains ₁ ，n ₂ ，…，n _m )。

S302, obtaining the corresponding relation (t (n) between the various configuration combinations and the actual time delay of the time adjusting module according to the various configuration combinations ₁ ，n ₂ ，…，n _m )，n ₁ ，n ₂ ，…，n _m )，n _i ∈[0，N _i ]，i∈[1，m]。

The descriptions of the processes of steps S301-S302 refer to step S201 and step S202, and are not described herein again.

S303, according to the preset value range and the time precision t of the delay series a _s To obtain the expected delay t corresponding to different delay levels a _D (a) Satisfy t _D (a)＝t _set (a-1)+t _s . Wherein a is more than or equal to 0 and less than or equal to a _max A is a positive integer, a _max To satisfy inequality t _set (a) A maximum integer value of a when T is less than or equal to T, wherein T is a clock period; t is t _set (a-1) is the desired delay t _D (a-1) the closest said timeActual delay of the regulating module, t _set (a) To be delayed by t _D (a) The closest actual delay of the time adjustment module. With respect to time accuracy t _s Average unit delay t _m ' and desired unit delay t _m For explanation, refer to the foregoing description of terms.

S304, according to the corresponding relation (t (n) ₁ ，n ₂ ，…，n _m )，n ₁ ，n ₂ ，…，n _m ) Respectively selecting the actual delay t of the time adjustment unit _set (a) Satisfy t _set (a)→t _D (a)，0≤a≤a _max The configuration combination of the delay units of each stage of delay chain (n) _1a ，n _2a ，…，n _ma ). Thereby obtaining different combinations of delay levels a and configurations (n) _1a ，n _2a ，…，n _ma ) Corresponding relation (a, (n) _1a ，n _2a ，…，n _ma ) Or a different desired delay t) _D (a) And configuration combination (n) _1a ，n _2a ，…，n _ma ) Corresponding relation (t) _D (a)，(n _1a ，n _2a ，…，n _ma )). Wherein, t _set (a) In combination with configuration (n) _1a ，n _2a ，…，n _ma ) The corresponding actual delay.

In practical application, the delay function of each stage of the delay chain of the time adjusting module is actually realized through an electronic device, and the actual delay function of the output can be slightly different for the input of different level change edges. For example, in a delay chain in which 5 delay units of 0.1s are arranged, for a level falling edge, 0.51s is delayed, and for a level rising edge, 0.49s is delayed, so to further reduce nonlinearity, the correction and calibration processes can respectively traverse two cases of a level rising edge (low level is inverted to high level) and a level falling edge (high level is inverted to low level), and the implementation manner shown in fig. 2 or fig. 3 is applied to each case to obtain correction data of the level rising edge and correction data of the level falling edge, that is, the corresponding relationship between different delay parameters and configuration combinations of the delay units corresponding to the level rising edge and the level falling edge is obtained.

If the time precision required by the target sequence signal is not high, the influence of different actual delays caused by different level conversion edges does not need to be considered, and calibration correction does not need to be separately carried out. However, if the time accuracy reaches 0.01s, it is necessary to obtain the correction data for the rising edge of the level and the correction data for the falling edge of the level, respectively, in consideration of the different influences of the two.

S103, according to the configuration combination (n) of the delay units corresponding to the target delay parameters _1A ，n _2A ，…，n _mA ) And configuring delay chains of all stages in the time adjusting module.

In this step, the delay chain in the time adjustment module may be equivalent to an interpolated delay chain formed by serially connecting a plurality of delay units. The single-stage delay chain can be output through the tap delay chain, different output sites are selected, and different delay outputs are obtained; different delay outputs can be obtained by gating different clock phases through a multi-phase clock; or the 0/1 strings which are parallel and low-speed under the working clock are coded and output according to the high-speed clock through the parallel-serial conversion of the high-speed clock, and the time can be regarded as the result of the selective output at a plurality of positions. In the implementation mode, the tap delay chain and the multiphase clock need to be added with a multi-path selector, and the parallel-serial conversion of the high-speed clock can achieve the function of setting the number of delay units without the multi-path selector. The delay chain of the above implementation manner can be regarded as an interpolation delay chain structure which can perform gating operation on a plurality of delay units connected in series to obtain different delay outputs.

The configuration of each stage of delay chain comprises the following steps: according to the configuration combination (n) of the delay units of each level of the delay chain corresponding to the target delay parameter _1A ，n _2A ，…，n _mA ) Determining the number n of delay units for delaying in each stage of delay chain in the time adjustment module _iA ，i∈[1，m]The delay chains of each stage are respectively gated by a multiplexer for delaying n _iA A delay unit. Such as n _1A If the value is 3, the first three delay units are gated from the first-stage delay chain, and the output of the third delay unit of the first-stage delay chain is taken as an output locus。

When the delay units gated by the delay chains at different stages are different, the corresponding output sequence signals are different, as shown in fig. 5, which shows a comparison waveform diagram of the output sequence signals and the input sequence signals when the delay chains at the ith stage gate different numbers of delay units.

And S104, generating an original sequence signal according to the period number P and the logic level, transmitting the original sequence signal to the time adjusting module, and obtaining a first sequence signal output after the delay action of each stage of delay chain in the time adjusting module.

In this step, the original sequence signal determines whether the current signal is a high level signal or a low level signal according to the logic level, specifically, when the logic level indicates a high level, the original sequence signal is currently output as a high level signal; when the logic level indicates a low level, the original sequence signal is currently output as a low level signal. The number of periods P is used to indicate the duration of the current level signal, i.e. the duration PT.

Each stage of delay chain in the time adjusting module receives the sequence signal output by the last stage of delay chain, obtains the sequence signal output by the stage after the delay action of the gated delay unit in the stage of delay chain, and transmits the sequence signal to the next stage of delay chain for delay processing. The first stage of delay chain receives the original sequence signal sent by the original sequence signal generating module, and the last stage of delay chain delays to output the first sequence signal after the delay action of the delay unit in each stage of delay chain.

According to the method, the preset correction table obtained by calibration through the nonlinear correction method is used for obtaining the configuration combination of the delay units of each stage of the delay chain, the actual delay of which is closest to the expected delay, so that the nonlinear influence of each stage of the delay chain is reduced, and the deviation between the output first sequence signal and the target sequence signal is reduced.

Please refer to fig. 6 for details, which shows a flowchart of a method for generating a sequence signal according to another embodiment of the present invention, wherein compared with the method provided in the previous embodiment, the nonlinear correction method of the present embodiment adopts an INL correction method and a DNL correction method to obtain two sets of correction data, and then the method for generating a sequence signal according to the present embodiment includes the following steps:

s401, acquiring waveform setting information.

Compared to step S101, the waveform setting information in this step further includes a method flag indicating that the correction method is currently employed. The method identification can directly acquire the correction method which the user wants to select to set the method identification through the upper computer or other processing devices; and can also be identified by a time information adaptive determination method of the target sequence signal. For further explanation of the waveform setting information, refer to step S101.

S402, obtaining the configuration combination of the delay units of each level of the delay chain corresponding to the method identification and the target delay parameter from the preset correction table.

Compared with step S102, the correction data of the preset correction table in this step includes two sets of INL correction data and DNL correction data, and only the configuration combination of the delay units of each stage of the delay chain can be determined through the method identifier and the target delay parameter. The preset correction table is obtained according to the INL correction method and the DNL correction method. For a detailed explanation of the INL correction method and the DNL correction method, refer to step S102.

And S403, configuring each level of delay chain in the time adjusting module according to the configuration combination of the delay units corresponding to the target delay parameters.

S404, generating an original sequence signal according to the period number and the logic level, transmitting the original sequence signal to the time adjusting module, and obtaining a first sequence signal output after the delay action of each stage of delay chain in the time adjusting module.

For the explanation of step S403 and step S404, refer to step S103 and step S104, respectively, and are not repeated herein.

Referring to fig. 7, a schematic flow chart of a sequence signal generating method according to another embodiment of the present invention is shown, where compared with fig. 1, step S105 is added to the method: and updating the preset correction table.

In this step, the updating may update the preset correction table in response to an update request of the sequencer, so that the preset correction table changes in response to a change in a delay unit in the sequencer, may actively update the preset correction table according to a time-precision change of the target sequencer, or may update the correction data in the preset correction table in response to a change of the correction method.

According to the method, the step of updating the preset correction table is added, the correction table can be updated according to the change of an application scene or other conditions, the sequence signal generation method is more flexible, and the universality is improved.

The following describes a specific implementation process of the scheme provided by the invention applied to the sequence signal generator, calibration and correction with reference to a specific example. Assume that the sequence signal generator conditions are as follows:

the period T of the working clock is 3ns, and the time adjusting module comprises a three-stage delay chain, namely m is 3: expected unit delay t of delay unit of first-stage delay chain ₁ 1ns, the stage is provided with 4 delay elements, i.e. N ₁ 4; expected unit delay t of delay unit of second-stage delay chain ₂ 0.4ns, the stage is provided with 3 delay elements, i.e. N ₂ 3; expected unit delay t of delay unit of third-stage delay chain ₃ 0.2ns, the stage is provided with 3 delay elements, i.e. N ₃ ＝3。

Before generating the sequence signal, the time adjustment module in the sequence signal generator needs to be calibrated and corrected, the time precision in this example is not high, and the small difference of the time delay after the level rising edge and the level falling edge pass through the time adjustment module does not need to be considered, and the specific process is as follows:

(1) the delay units traversing each stage of delay chain adopt different number of configuration combinations (n) ₁ ，n ₂ ，n ₃ )，n ₁ ∈[0，4]，n ₂ ∈[0，3]，n ₃ ∈[0，3]Obtaining the corresponding relation (t (n) of the actual time delay of various configuration combinations and time adjusting modules ₁ ，n ₂ ，n ₃ )，n ₁ ，n ₂ ，n ₃ )，n ₁ ∈[0，4]，n ₂ ∈[0，3]，n ₃ ∈[0，3]. In particular, by multiplexingThe selector is such that n ₁ ＝0，n ₂ ＝0，n ₃ When the actual delay of the time adjusting module is t (0, 0, 0) ═ 0ns, obtaining a corresponding relation (0ns, 0, 0, 0) between the actual delay 0ns and the configuration combination (0, 0, 0); by means of a multiplexer so that n ₁ ＝1，n ₂ ＝0，n ₃ When the actual delay time is t (1, 0, 0) ═ 1.1ns, the corresponding relation (1.1ns, 1, 0, 0) between the actual delay time 1.1ns and the configuration combination (1, 0, 0) is obtained; by analogy, the corresponding relation between the actual delay and the configuration combination is obtained: (0ns, 0, 0, 0), (1.1ns, 1, 0, 0), (2ns, 2, 0, 0), (3ns, 3, 0, 0), (4.15ns, 4, 0, 0), (0.45ns, 0, 1, 0), (0.95ns, 0, 2, 0), (1.33ns, 0, 3, 0), (0.21ns, 0, 0, 1), (0.38ns, 0, 0, 2), (0.64ns, 0, 0, 3), (0.66ns, 0, 1, 1), (0.84ns, 0, 1, 2), (6.12ns, 4, 3, 3). After testing 5 × 4 × 80 times to obtain 80 sets of correspondences, step (2) is performed.

(2) According to the obtained 80 groups of actual delays t (n) ₁ ，n ₂ ，n ₃ ) And configuration combinations (n) ₁ ，n ₂ ，n ₃ ) Obtaining the average unit delay t of the 1 st level delay unit according to the corresponding relation ₁ ' -t (4, 0, 0)/4-4.15 ns/4-1.0375 ns; average unit delay t of 2 nd stage delay unit ₂ ' -t (0, 3, 0)/3 ═ 1.33ns/3 ≈ 0.4433 ns; average unit delay t of 3 rd stage delay unit ₃ ' -t (0, 0, 3)/3-0.64 ns/3 ≈ 0.2133 ns. According to the mean unit delay t ₃ ' ≈ 0.2133ns and desired unit delay t ₃ 0.2ns, determining the time accuracy t _s Go to step (3) for 0.21 ns.

(3) And selecting a corresponding correction method according to the correction strategy. If the actual delay and the expected delay a x t of the time adjusting module are expected _s The closer the better, the INL correction method is selected, and the step (4.1) is executed; if it is desired that the actual delay of the time adjustment module is closer to the desired step, the desired step is a time precision t _s If 0.21ns, selecting the DNL correction method, and executing step (4.2);

(4.1) according to the time accuracy t _s ＝0.21ns and a clock period T of 3ns, with actual delays T (n) from 80 sets ₁ ，n ₂ ，n ₃ ) And configuration combinations (n) ₁ ，n ₂ ，n ₃ ) In the corresponding relation, the actual delay t of the time adjustment unit is selected _set (a) Satisfy t _set (a)→t _I (a)＝a×t _s The configuration combination of the delay units of each stage of delay chain (n) _1a ，n _2a ，n _3a ) Wherein a is more than or equal to 0 and less than or equal to T/T _s I.e. a is [0, 14 ]]Is an integer between.

Specifically, the number of delay steps a is 0, and the actual delay t is selected from the 80-group correspondence _set (0) T (0, 0, 0) 0ns and t _I (0)＝0×t _s 0ns closest, corresponding configuration combination (n) _1o ，n ₂₀ ，n ₃₀ ) (0, 0, 0); selecting the delay series a as 1, selecting the actual delay t from the 80 corresponding relations _set (1) T (0, 0, 1) ═ 0.21ns and t _I (1)＝1×t _s Closest 0.21ns, corresponding configuration combination (n) ₁₁ ，n ₂₁ ，n ₃₁ ) (0, 0, 1); .., until the delay series a is 14, the actual delay t is selected from the 80-group corresponding relation _set (14) T (2, 2, 0) 2.95ns and t _I (14)＝14×t _s 2.94ns, corresponding configuration combination (n) ₁₁₄ ，n ₂₁₄ ，n ₃₁₄ ) (2, 2, 0). Obtaining the delay series a (the number of the 3 rd level delay units of the equivalent interpolation) and (n) _1a ，n _2a ，n _3a ) And (5) combining the corresponding relations and entering the step (5).

(4.2) according to the time accuracy t _s 0.21ns, when the delay order a is 0, the delay t is expected _D (0) When the time delay t is 0ns, the actual time delay t is selected from 80 corresponding groups _set (0) T (0, 0, 0) 0ns and t _D (0) 0ns closest, corresponding configuration combination (n) ₁₀ ，n ₂₀ ，n ₃₀ ) (0, 0, 0); when the delay order a is 1, the desired delay t _D (1)＝t _set (0) + 0.21-0.21 ns, the actual delay t is selected from the 80-group correspondence _set (1) T (0, 0, 1) ═ 0.21ns and t _D (1) Closest, corresponding configuration combination (n) ₁₁ ，n ₂₁ ，n ₃₁ ) (0, 0, 1); .. _s 0.21ns, the actual delay t of the time adjustment unit is obtained _set (a) Satisfy t _set (a)→t _set (a-1)+t _s The configuration combination of the delay units of each stage of delay chain (n) _1a ，n _2a ，…，n _ma ). Until a is obtained and does not satisfy inequality t _set (a) T is less than or equal to the integral value of the spoon, and the step (5) is carried out.

(5) According to the steps (4.1) and (4.2), the combination of the delay series a and the configuration (n) is obtained _1a ，n _2a ，n _3a ) Obtaining a preset correction table according to the corresponding relation, and realizing the combination of the delay progression a and the configuration (n) by the preset correction table _1a ，n _2a ，n _3a ) And (4) mutual conversion.

After the preset correction table is obtained, if the high level duration of the target sequence signal is 7ns, the logic level and the period number in the waveform setting information corresponding to the target sequence signal are 2, the target delay parameter adopts the delay progression, and the corresponding expected delay is 1 ns.

According to the comparison between the expected delay and the actual delay in the preset correction table, the following results are found: the actual delay 0.95ns is closest to the desired delay, whereby (0, 2, 0) of (0.95ns, 0, 2, 0) is combined as a configuration of delay elements matching the desired delay, and then for the sequence signal generator the first sequence signal is output from the second delay element of the second stage delay chain.

Another embodiment of the present invention provides a sequence signal generating apparatus, which has a structure as shown in fig. 8, and includes: the device comprises a time adjusting module and an original sequence signal generating module.

The original sequence signal generation module is used for acquiring the period number P in the waveform setting information, the logic level in the waveform setting information and the working clock of the sequence signal generator; and generating an original sequence signal according to the period number P, the logic level and the working clock, and transmitting the original sequence signal to the time adjusting module. The waveform setting information is obtained according to the time information of the target sequence signal and the clock period of the working clock, and the waveform setting information comprises the period number P and the target delay parameter. For a description of how to obtain the waveform setting information, please refer to step S101 in the above method embodiment.

The original sequence signal generating module comprises a waveform playing unit and a counting unit;

a counting unit for acquiring the cycle number P and the working clock in the waveform setting information; and when the time for continuously playing the level signal by the waveform playing unit reaches P clock cycles, sending a counting completion signal to the waveform playing unit. The counting mode of the counting unit can adopt a countdown mode of starting from P and descending to 0, a counting mode of starting from 0 and ascending to P or other counting modes.

And the waveform playing unit is used for acquiring the logic level in the waveform setting information, playing the level signal corresponding to the logic level, and converting the level signal at the edge of the P-th working clock by the played level signal to generate an original sequence signal when receiving the counting completion signal.

In addition, the original sequence signal generation module further comprises an updating unit, and the updating unit is used for sending a waveform updating request to an upper computer or other processing devices when receiving the counting completion signal of the counting unit, so that the sequence signal generation device can acquire waveform setting information at the next moment.

The time adjustment module includes: a modification submodule and an interpolation submodule. The correction submodule is used for acquiring a target delay parameter in the waveform setting information; and obtaining the configuration combination of the delay units of each level of the delay chain of the interpolation sub-module corresponding to the target delay parameter from the preset correction table, so that the finally output actual delay is as close as possible to the target expected delay required by the target sequence signal. And the configuration combination of the delay units is sent to the interpolation submodule. The preset correction table is obtained according to a nonlinear correction method, and the nonlinear correction method obtains the corresponding relation between different delay parameters and the configuration combination of the delay units according to the actual delay of the time adjusting module and the expected delays corresponding to the different delay parameters. For the process of obtaining the preset correction table by the nonlinear correction method, please refer to the method embodiment.

The interpolation submodule is used for receiving the configuration combination sent by the correction submodule and configuring each level of delay chain according to the configuration combination of the delay unit corresponding to the target delay parameter; receiving an original sequence signal sent by an original sequence signal generating module; and the original sequence signal is sequentially subjected to the delay action of each stage of delay chain and then is output as a first sequence signal.

The interpolation sub-module includes: the system comprises a plurality of stages of delay chains and a multiplexer, wherein each stage of delay chain is connected with one multiplexer so as to select the output site of the corresponding delay chain through the multiplexer. The interpolation submodule includes at least two stages of delay chains, and as shown in fig. 8, the interpolation submodule may include m stages of delay chains, where m is greater than or equal to 3.

After the multiplexer receives the configuration combination of the delay units, the multiplexer is configured to determine the number of delay units used for delaying in the delay chain connected to the multiplexer according to the configuration combination of the delay units of each stage of the delay chain corresponding to the target delay parameter, and one multiplexer can control the corresponding delay chain to select different output sites, so as to gate the delay unit used for delaying in the delay chain corresponding to any multiplexer through the all-in-one gating function of the multiplexer, as shown in fig. 8, so that the final output actual delay is as close as possible to the target expected delay required by the target sequence signal.

Any stage of delay chain in the multi-stage delay chain is used for receiving the sequence signal output by the previous stage of delay chain, obtaining the sequence signal output by the stage after the delay action of the gated delay unit in the stage of delay chain, and transmitting the sequence signal to the next stage of delay chain; the first-stage delay chain in the multi-stage delay chain receives the original sequence signal sent by the original sequence signal generating module, so that the last-stage delay chain in the multi-stage delay chain outputs the first sequence signal through the level conversion time of the delayed original sequence signal of the gated delay unit in each stage of delay chain.

The total number of delay units in the multi-stage delay chain is too much, which increases the production cost and power consumption of the device, the interpolation submodule of the embodiment can set up the multi-stage delay chain with more than two stages, the interpolation stage number can be increased in the design stage, and the number of delay units required for realizing the same time precision is reduced, so that the number of the selected delay units is within a proper range, and generally, the total number of the delay units of the multi-stage delay chain is limited within 100.

The delay chains of all levels of the interpolation submodule can be designed according to the known clock period T and the expected time precision T' _s And the interpolation submodule is provided with a k-stage delay chain and can pass through a formula [ (T/T' _s )^(1/k)]k is calculated to obtain the minimum number of delay units needed by the interpolation submodule, and the minimum number of delay units needed can be reduced as k is increased. Under the determined interpolation series k, the proportional distribution can lead to the minimum total number of the delay units, but in practical application, the number of the delay units of each stage of the delay chain is reserved with allowance in consideration of the nonlinearity prevention ' dead zone ' of the delay units, so that the interpolation series k is based on the formula [ (T/T ' _s )^(1/k)]After the number of the delay units (called theoretical number for short) which are minimum needed is calculated, more delay units than the theoretical number need to be arranged in the interpolation submodule.

The device of the embodiment obtains the configuration combination of the delay units of each stage of delay chain with the actual delay closest to the expected delay through the correction submodule, reduces the nonlinear influence of each stage of delay chain, and reduces the deviation of the output first sequence signal and the target sequence signal. Meanwhile, the device of the embodiment can use two or more stages of delay chains according to the time precision requirement so as to reduce the number of delay units and reduce the single-channel realization cost and power consumption.

Compared with the apparatus in fig. 8, the apparatus of this embodiment further includes an updating module for updating the predetermined correction table. The updating module can update the preset correction table after the updating unit of the original sequence signal generating module sends an updating request; the preset correction table can be actively updated according to the time precision change of the target sequence signal; the method can also be suitable for the replacement of the correction method, and the correction data in the preset correction table is updated; or the preset correction table can be updated in response to the acquired request for updating the correction table externally, so that the correction table is updated according to the change of an application scene or other conditions, the generation of the sequence signal is more flexible, and the universality is improved.

Another embodiment of the present invention provides a sequence signal generator, which has a structure as shown in fig. 9, and includes: clock generation means, communication control means, waveform storage means and at least one sequence generation means.

And the clock generating device is used for generating the working clock of the sequence signal generator and distributing the working clock to the communication control device, the waveform storage device and each sequence generating device.

And the communication control device is used for communicating with the upper computer and receiving instructions and data. Specifically, the communication control device transmits waveform setting information of the upper computer to the waveform storage device, and inputs the correction data to the corresponding sequence generation device. In other embodiments, the upper computer may be replaced with another processing device, or the calculation of the waveform setting information may be implemented by incorporating it into the communication control device.

And the waveform storage device is used for storing the waveform setting information, updating the waveform setting information according to the waveform updating request sent by the sequence generation device during playing, and sending the waveform setting information to the sequence generation device.

Each sequence generating apparatus may be implemented by using the sequence signal generating apparatus provided in the foregoing embodiment, or the sequence signal generating method provided in the foregoing embodiment is built in the sequence signal generating apparatus to implement output of a sequence signal, and for the execution process of each sequence generating apparatus, reference may be made to the description in the foregoing embodiment, which is not described in this embodiment. Each sequence signal generating device can adopt delay chains with different stages, so that different first sequence signals can be output in parallel through each sequence generating device, and parallel processing of different target sequence signals is realized.

Based on the above description of the sequence signal generator, the sequence signal generator of the present embodiment is considered from three aspects: the first aspect is to set a margin for the number of delay units of each level of delay chain, the second aspect is to adopt two or more levels of delay chains, and the third aspect is to obtain a preset correction table through calibration and correction, so as to carry out nonlinear correction on each level of delay chain through the preset correction table. The sequence signal generator provided by the embodiment has the following advantages based on the three aspects:

firstly, the number of the delay units of each level of delay chain is provided with a margin to prevent the occurrence of an adjustment blind area; secondly, when higher time precision is realized, the method is easier to realize by adopting two or more stages of delay chains compared with a single-stage delay chain; and finally, the configuration combination of the delay units of each stage of delay chain with the actual delay closest to the expected delay is obtained through the preset correction table, so that the nonlinear influence of each stage of delay chain is reduced, and the deviation of the output first sequence signal and the target sequence signal is reduced.

All the embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, the system or system embodiments are substantially similar to the method embodiments and therefore are described in a relatively simple manner, and reference may be made to some of the descriptions of the method embodiments for related points. The above-described system and system embodiments are only illustrative, wherein the units described as separate parts may or may not be physically separate, and the parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment. One of ordinary skill in the art can understand and implement it without inventive effort.

Those of skill would further appreciate that the various illustrative components and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the components and steps of the various examples have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the technical solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A sequence signal generation method, comprising:

obtaining the configuration combination of the delay units of each level of delay chain corresponding to the target delay parameter from a preset correction table; the time delay chains at all levels are positioned in a time adjusting module, the preset correction table is obtained according to a nonlinear correction method, and the nonlinear correction method obtains the corresponding relation between different time delay parameters and the configuration combination of time delay units according to the actual time delay of the time adjusting module and the expected time delay corresponding to the different time delay parameters;

configuring each level of delay chain in the time adjusting module according to the configuration combination of the delay unit corresponding to the target delay parameter;

generating an original sequence signal according to the period number and the logic level, transmitting the original sequence signal to the time adjusting module, and obtaining a first sequence signal output after the delay action of each stage of delay chain in the time adjusting module;

the nonlinear correction method comprises an integral nonlinear correction method and a differential nonlinear correction method; the waveform setting information also comprises a method identifier for indicating that a correction method is currently adopted;

2. The method according to claim 1, wherein the nonlinear correction method is an integral nonlinear correction method, and the obtaining of the corresponding relationship between different delay parameters and configuration combinations of delay units by the integral nonlinear correction method comprises:

according to the preset value range and time of the delay series aAccuracy t _s Obtaining expected delays t corresponding to different delay levels a _I (a) Satisfy t _I (a)＝a×t _s (ii) a Wherein a is more than or equal to 0 and less than or equal to T/T _s A is an integer, T is the clock period; the delay parameter comprises the delay series a or the expected delay t _I (a) (ii) a Said time accuracy t _s Is the average unit delay t of the delay units according to the m-th stage delay chain _m ' and expected unit delay t of delay unit of m-th stage delay chain _m Determined, said average unit delay t _m ’＝(t(0，0，…，N _m )-t(0，0，…，0))/N _m ，N _m A configurable maximum number of delay units for the mth stage delay chain;

according to the corresponding relation (t (n) ₁ ，n ₂ ，…，n _m )，n ₁ ，n ₂ ，…，n _m ) Respectively selecting the actual time delay t of the time adjustment module _set (a) Satisfy t _set (a)→t _I (a)，0≤a≤T/t _s The configuration combination of the delay units of each stage of delay chain (n) _1a ，n _2a ，…，n _ma ) (ii) a Thereby obtaining different delay levels a and the configuration combination (n) _1a ，n _2a ，…，n _ma ) (a), (n) of _1a ，n _2a ，…，n _ma ) Or a different desired delay t) _I (a) And the configuration combination (n) _1a ，n _2a ，…，n _ma ) Corresponding relation (t) _I (a)，(n _1a ，n _2a ，…，n _ma ) ); wherein, t is _set (a) In combination with said configuration (n) _1a ，n _2a ，…，n _ma ) The corresponding actual delay.

3. The method according to claim 1, wherein the nonlinear modification method is a differential nonlinear modification method, and the obtaining the corresponding relationship between different delay parameters and configuration combinations of delay units by the differential nonlinear modification method comprises:

according to the configurable number of the delay units of each stage of delay chain, the pairsThe delay units between the delay chains at all levels are combined to obtain various configuration combinations (n) of the delay units between the delay chains at all levels ₁ ，n ₂ ，…，n _m ) Wherein ni is the configuration number of the delay units in the ith stage delay chain in the configuration combination, and the ith stage delay chain has N in total _i A delay unit, then n _i ∈[0，N _i ]，i∈[1，m]M is more than or equal to 2, and ni, i and m are integers;

according to the preset value range and time precision t of the delay series a _s Obtaining expected delays t corresponding to different delay levels a _D (a) Satisfy t _D (a)＝t _set (a-1)+t _s (ii) a Wherein a is more than or equal to 0 and less than or equal to a _max A is a positive integer, a _max To satisfy inequality t _set (a) A maximum integer value of a when T is less than or equal to T, wherein T is the clock period; t is t _set (a-1) is the desired delay t _D (a-1) the closest actual delay, t, of said time adjustment module _set (a) Is delayed by t _D (a) The closest actual delay of the time adjustment module; said time precision t _s Is the average unit delay t of the delay units according to the m-th stage delay chain _m ' and expected unit delay t of delay unit of said m-th stage delay chain _m Determined, said average unit delay t _m ’＝(t(0，0，…，N _m )-t(0，0，…，0))/N _m ，N _m A configurable maximum number of delay units for the mth stage delay chain;

according to the corresponding relation (t (n) ₁ ，n ₂ ，…，n _m )，n ₁ ，n ₂ ，…，n _m ) Respectively selecting the actual time delay t of the time adjusting module _set (a) Satisfy t _set (a)→t _D (a)，0≤a≤a _max The configuration combination of the delay units of each stage of delay chain (n) _1a ，n _2a ，…，n _ma ) (ii) a Thereby obtaining the corresponding relation (a, (n) of different delay series a and the configuration combination _1a ，n _2a ，…，n _ma ) Or a different desired delay t) _D (a) And said configuration combination (n) _1a ，n _2a ，…，n _ma ) Corresponding relation (t) _D (a)，(n _1a ，n _2a ，…，n _ma ) Wherein, the t _set (a) In combination with said configuration (n) _1a ，n _2a ，…，n _ma ) The corresponding actual delay.

4. The method of claim 1, wherein the configuring the delay chains of each stage in the time adjustment module comprises:

5. The method of claim 1, further comprising: and updating the preset correction table.

6. A sequence signal generation apparatus, comprising: the device comprises a time adjusting module and an original sequence signal generating module; wherein the content of the first and second substances,

the original sequence signal generating module is used for acquiring the period number in waveform setting information, the logic level in the waveform setting information and the working clock of the sequence signal generator; generating an original sequence signal according to the period number, the logic level and the working clock, and transmitting the original sequence signal to the time adjusting module; the waveform setting information is obtained according to time information of a target sequence signal and a clock cycle of the working clock, and comprises cycle number and a target delay parameter;

the correction submodule is used for acquiring a target delay parameter in the waveform setting information; obtaining a configuration combination of delay units of each level of delay chain of the interpolation sub-module corresponding to the target delay parameter from a preset correction table; sending the configuration combination of the delay units to the interpolation submodule; the preset correction table is obtained according to a nonlinear correction method, and the nonlinear correction method obtains the corresponding relation between different delay parameters and configuration combinations of delay units according to the actual delay of the time adjusting module and expected delays corresponding to the different delay parameters;

the interpolation sub-module is used for configuring each stage of delay chain according to the configuration combination of the delay unit corresponding to the target delay parameter; receiving an original sequence signal sent by the original sequence signal generation module, and outputting a first sequence signal after the original sequence signal sequentially passes through the delay action of each level of delay chain;

the nonlinear correction method comprises an integral nonlinear correction method and a differential nonlinear correction method; the waveform setting information also comprises a method identifier for indicating that a correction method is currently adopted; the correction submodule is specifically configured to:

7. The apparatus of claim 6, wherein the interpolation sub-module comprises: the system comprises a multi-stage delay chain and a multiplexer, wherein each stage of delay chain is connected with one multiplexer;

any stage of delay chain in the multistage delay chain is used for receiving the sequence signal output by the previous stage of multiplexer, delaying the sequence signal output by the previous stage of delay chain through the gated delay unit in the stage of delay chain to obtain the sequence signal output by the stage of delay chain, and transmitting the sequence signal to the next stage of delay chain; and the first-stage delay chain in the multi-stage delay chains receives the original sequence signal, and the level conversion time of the original sequence signal is delayed by the gated delay units in the delay chains at all stages, so that the last-stage delay chain in the multi-stage delay chains outputs the first sequence signal.

8. The apparatus of claim 6, wherein the original sequence signal generating module comprises a waveform playing unit and a counting unit;

the counting unit is used for acquiring the cycle number and the working clock in the waveform setting information, and when the time for the waveform playing unit to continuously play the level signal reaches the cycle number of clock cycles, sending a counting completion signal to the waveform playing unit;

and the waveform playing unit is used for acquiring the logic level in the waveform setting information, playing the level signal corresponding to the logic level, and converting the level signal at the edge of the working clock to generate an original sequence signal when receiving the counting completion signal.

9. The apparatus of claim 6, further comprising an update module configured to update the preset fix-up table.