CN116418317A - Clock generation method and system in ATE equipment - Google Patents

Abstract

The invention provides a clock generation method and a clock generation system in ATE equipment, wherein the method comprises the following steps: acquiring clock parameters of a clock to be configured, and analyzing clock period and edge time parameters; the edge moment submodule calculates output of each level and outputs delay data of each edge moment; the residual time submodule selects a corresponding updating strategy to output corresponding residual time and obtains the waveform shape of each edge moment; and the preset waveform output submodule generates a clock waveform of the clock to be configured according to the waveform shape and delay data of each edge moment under the control of the system clock. The clock generation scheme of the invention gives consideration to clock precision and clock parameter flexibility, and can realize large-scale adjustment of clock frequency and clock duty ratio while giving consideration to clock precision only by configuring rising edge parameters and period parameters of the clock to be configured.

Description

Clock generation method and system in ATE equipment

Technical Field

The present invention relates to the field of clock generation, and in particular, to a clock generation method and system in ATE equipment.

Background

ATE (Automatic Test Equipment) is an automatic test equipment, which is an aggregate of test instruments controlled by a high-performance computer, which is a test system composed of a tester and a computer, and the computer controls test hardware by running instructions of a test program. Semiconductor chip ATE is used for detecting the integrity of functions and performances of integrated circuits, and is an important device for ensuring the quality of integrated circuits in the integrated circuit production and manufacturing process, and the integrated circuit test usually needs to be performed by four processes of test programming, program compiling, vector loading and test.

In ATE devices, the clock signal is a very important parameter. ATE equipment needs to generate working clocks required by various chips to be tested, and the clock frequencies and the clock duty ratios of the working clocks are different.

The clock generation schemes in the prior art are mainly divided into two types. One clock generation scheme is to multiply an input signal of a specific frequency by a specific multiplication factor to generate an output clock signal. However, the clock duty cycle of this scheme cannot be widely adjusted. Another clock generation scheme is based on direct generation of waveforms by a delay unit, can generate stable clock signals with adjustable frequency, and has strong flexibility. However, the scheme is adjustable in frequency on the basis of sacrificing clock precision, the precision of the generated clock signal is extremely poor, and the high-precision requirement of ATE equipment on the clock is difficult to meet.

Accordingly, there is a great need for a clock scheme with adjustable frequency and duty cycle to solve the above problems.

Disclosure of Invention

In view of this, the invention provides a clock generation method and system in ATE equipment, and the specific scheme is as follows:

a method of clock generation in an ATE device, comprising:

setting a system clock period, acquiring clock parameters of a clock to be configured, and analyzing the clock period and edge time parameters from the clock parameters;

The preset edge time submodule acquires the residual time output by the preset residual time submodule, calculates the output of each level by combining the clock period, transmits the output to the residual time submodule, calculates a plurality of subsequent edge times according to the edge time parameter, and outputs delay data of each edge time;

in the residual time submodule, a corresponding update strategy is selected according to the number of edge moments in each system clock period to output corresponding residual time, and the waveform shape of each edge moment is obtained according to received output of each stage; wherein the remaining time is a time interval between a current system clock cycle and a next edge time;

and the preset waveform output submodule generates a clock waveform of the clock to be configured according to the waveform shape and delay data of each edge moment under the control of the system clock.

In one particular embodiment, "selecting a respective update policy to output a respective remaining time based on the number of edge moments per system clock cycle" specifically includes:

obtaining the output of each stage and the residual time of the previous system clock period;

judging whether the edge time of the clock to be configured exists in the current system clock period or not so as to select corresponding intermediate parameters:

If not, taking the remaining time of the previous system clock cycle as an intermediate parameter, and storing the intermediate parameter into a preset register;

if yes, selecting the highest-level output from all levels of outputs, judging the number of edge moments in the system clock period according to the highest-level output, taking the highest-level output as an intermediate parameter, and storing the intermediate parameter into a preset register;

and calculating the residual time between the current system clock cycle and the next edge moment according to the intermediate parameter.

In a specific embodiment, the edge time parameters include a first edge parameter and a second edge parameter;

the clock cycles include a first clock cycle and a second clock cycle;

the remaining time includes a first remaining time and a second remaining time;

the delay data comprises first delay data and second delay data;

the first delay data, the first remaining time, the first clock period, and the first edge parameter are all in nanoseconds;

the second delay data, the second remaining time, the second clock period, and the second edge parameter are all in picoseconds;

The outputs of each stage include picosecond outputs and nanosecond outputs.

In a specific embodiment, the edge time submodule includes a plurality of stages of computing units, where the stage of computing units is the most initial computing unit;

each stage of computing unit comprises a picosecond adder and a nanosecond adder;

in the same-stage computing unit, the carry output signal of the picosecond adder is the carry input signal of the nanosecond adder;

the nanosecond output signal of the nanosecond adder of each stage of computing unit is a first nanosecond input signal of the nanosecond adder of the next stage of computing unit, the first nanosecond input signal of the nanosecond adder of the first stage of computing unit is the first residual time, and the second nanosecond input signal of each nanosecond adder is the first clock period; each nanosecond adder adds the first nanosecond input signal and the second nanosecond input signal to obtain a nanosecond output signal, and the obtained nanosecond output signal is used as the nanosecond output of each stage;

the picosecond output signal of the picosecond adder of each stage of computing unit is the first picosecond input signal of the picosecond adder of the next stage of computing unit, the first picosecond input signal of the picosecond adder of the first stage of computing unit is the second residual time, and the second picosecond input signal of each picosecond adder is the second clock period; each picosecond adder adds the first picosecond input signal and the second picosecond input signal to obtain a picosecond output signal, and the obtained picosecond output signal is output as picoseconds of each stage.

In a specific embodiment, according to the maximum number of edge moments of the clock to be configured in each system clock period, the number of stages of the required computing units is calculated, and the specific expression is as follows:

wherein N represents the number of stages of the calculation unit, M represents the maximum number of edge moments of clocks to be configured in each system clock period,

log of representation pair ₂ M is rounded upwards;

if N is a non-integer, then rounding up.

In a specific embodiment, the first edge parameter includes a first rising edge parameter and a first falling edge parameter, and the second edge parameter includes a second rising edge parameter and a second falling edge parameter;

the edge time submodule is divided into a rising edge submodule and a falling edge submodule;

the rising edge submodule calculates a plurality of rising edge moments according to the first rising edge parameter and the second rising edge parameter to obtain rising edge nanosecond output and rising edge picosecond output of each stage;

and the falling edge submodule calculates a plurality of falling edge moments according to the first falling edge parameter and the second falling edge parameter to obtain falling edge nanosecond output and falling edge picosecond output of each stage.

In a specific embodiment, the remaining time submodule receives rising edge nanosecond output and rising edge picosecond output of each stage, falling edge nanosecond output and falling edge picosecond output of each stage, divides the nanosecond output and picosecond output, and sequentially sorts the nanosecond output and picosecond output according to the order of magnitude;

And obtaining the waveform shape of each corresponding edge moment according to the sequencing result.

In a specific embodiment, the remaining time submodule comprises a time calculation submodule, and the time calculation submodule comprises a first time calculation subunit and a second time calculation subunit;

in the first time calculating subunit, after obtaining an intermediate parameter, making a difference between the intermediate parameter and a system clock cycle to obtain a first residual time of the current system clock cycle;

and in the second time calculation subunit, taking the acquired intermediate parameter as a second residual time of the current system clock cycle.

In a specific embodiment, the waveform output submodule comprises a coarse-granularity delay unit and a fine-granularity delay unit;

the coarse granularity time delay unit delays according to the first time delay data in nanoseconds;

and the fine-granularity delay unit delays according to the second delay data by taking picoseconds as a unit.

A clock generation system in an ATE device, comprising:

the clock parameter acquisition sub-module is used for setting a system clock period, acquiring clock parameters of a clock to be configured, and analyzing the clock period and the edge time parameters from the clock parameters;

The edge time submodule is used for acquiring the residual time output by the preset residual time submodule, calculating the output of each level by combining the clock period, transmitting the output to the residual time submodule, calculating a plurality of subsequent edge times according to the edge time parameters, and outputting delay data of each edge time;

the residual time sub-module is used for selecting a corresponding updating strategy according to the number of edge moments in each system clock period to output corresponding residual time, and obtaining the waveform shape of each edge moment according to the received output of each stage; the residual time is the time interval between the current system clock cycle and the next edge moment;

and the waveform output sub-module is used for generating clock waveforms of clocks to be configured according to waveform shapes and delay data of all edge moments under the control of a system clock.

In a specific embodiment, the edge time submodule includes a rising edge submodule and a falling edge submodule;

the rising edge submodule comprises a plurality of stages of computing units, wherein the one-stage computing unit is the most initial computing unit; each stage of computing unit comprises a picosecond adder and a nanosecond adder;

In the same-stage computing unit, the carry output end of the picosecond adder is connected with the carry input end of the nanosecond adder;

the nanosecond output end of the nanosecond adder of each level of computing unit is connected with the first nanosecond input end of the nanosecond adder of the next level of computing unit, the first nanosecond input end of the nanosecond adder of the level of computing unit is used for acquiring first residual time, and the second nanosecond input end of each nanosecond adder is used for acquiring a first clock period;

each nanosecond adder is used for adding the signal of the first nanosecond input end and the signal of the second nanosecond input end to obtain a nanosecond output signal, and the obtained nanosecond output signal is used as the nanosecond output of each stage;

the picosecond output end of the picosecond adder of each stage of computing unit is connected with the first picosecond input end of the picosecond adder of the next stage of computing unit, the first picosecond input end of the picosecond adder of the first stage of computing unit is used for acquiring second residual time, and the second picosecond input end of each picosecond adder is used for acquiring a second clock period;

each picosecond adder is used for adding the signal of the first picosecond input end and the signal of the second picosecond input end to obtain a picosecond output signal, and the obtained picosecond output signal is used as the picosecond output of each stage;

The falling edge submodule has the same structure as the rising edge submodule.

In a specific embodiment, the remaining time submodule includes a sorting decision submodule, a first time calculation submodule and a second time calculation submodule;

the sequencing judgment sub-module is used for receiving rising edge nanosecond output and rising edge picosecond output of each stage, falling edge nanosecond output and falling edge picosecond output of each stage, dividing the nanosecond output and picosecond output, and sequencing sequentially according to the size sequence; obtaining the waveform shape of each corresponding edge moment according to the sequencing result;

the first time calculating subunit is provided with a first adder and a first register, and is used for obtaining a first residual time of a current system clock period and registering the first residual time into the first register by making a difference between the intermediate parameter and the system clock period through the first adder after the intermediate parameter is obtained;

the second time calculating subunit is provided with a second register, and is used for taking the acquired intermediate parameter as the second residual time of the current system clock period and registering the second residual time into the second register.

The beneficial effects are that:

the invention provides a clock generation method and a clock generation system in ATE equipment, which are capable of considering clock precision and clock parameter flexibility. The scheme can realize the large-scale adjustment of the clock frequency and the clock duty ratio while considering the clock precision only by configuring the rising edge parameter and the period parameter of the clock to be configured. The clock signal is respectively carried out according to two paths of nanosecond level and picosecond level in the generation process, and on the basis of guaranteeing the basic shape of the waveform, the precision of the clock signal is improved, so that the generated high-precision clock signal can meet the precision requirement of ATE equipment.

Drawings

FIG. 1 is a schematic flow chart of a clock generation method according to an embodiment of the invention;

FIG. 2 is a schematic diagram of a relationship structure between modules according to an embodiment of the present invention;

FIG. 3 is an exemplary diagram of a clock cycle according to an embodiment of the present invention;

FIG. 4 is a diagram illustrating another example clock cycle according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of a rising edge sub-module according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of a falling edge submodule according to an embodiment of the present invention;

FIG. 7 is a schematic diagram of a remaining time submodule according to an embodiment of the present invention;

fig. 8 is a schematic diagram of a clock generation system according to an embodiment of the invention.

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Reference numerals: 1-a clock parameter acquisition sub-module; 2-an edge time sub-module; 3-a remaining time sub-module; 4-a waveform output sub-module; 21-rising edge sub-module; 22-falling edge sub-module; 31-a first time calculation subunit; 32-a second time calculation subunit; 33-a ranking decision sub-module.

Detailed Description

Hereinafter, various embodiments of the present disclosure will be more fully described. The present disclosure is capable of various embodiments and its modifications and variations are possible in light of the above teachings. However, it should be understood that: there is no intention to limit the various embodiments of the present disclosure to the specific embodiments disclosed herein, but rather the present disclosure is to be understood to cover all modifications, equivalents, and/or alternatives falling within the spirit and scope of the various embodiments of the present disclosure.

It should be noted that, the "clock period" of the present invention refers to a clock period with a configuration clock, and the "system clock period" refers to a clock configured by each module unit together, and the whole clock generation scheme needs to be implemented by using an external clock signal as a time axis.

Example 1

The embodiment 1 of the invention discloses a clock generation method in ATE equipment, which can realize the adjustable clock frequency and clock duty ratio on the premise of ensuring the clock precision. The specific scheme is as follows, and the clock generation method is shown in the flow chart of the method and the figure 1 of the specification:

a method of clock generation in ATE equipment, comprising the steps of:

101. setting a system clock period, acquiring clock parameters of a clock to be configured, and analyzing the clock period and edge time parameters from the clock parameters;

102. The preset edge time submodule acquires the residual time output by the preset residual time submodule, calculates the output of each level by combining with a clock period, transmits the output to the residual time submodule, calculates a plurality of subsequent edge times according to the edge time parameters, and outputs delay data of each edge time;

103. in the residual time submodule, a corresponding update strategy is selected according to the number of edge moments in each system clock period to output corresponding residual time, and the waveform shape of each edge moment is obtained according to received output of each stage;

104. and the preset waveform output submodule generates a clock waveform of the clock to be configured according to the waveform shape and delay data of each edge moment under the control of the system clock.

The clock generation method of the embodiment is suitable for a system comprising an edge time submodule, a residual time submodule and a waveform output submodule, wherein the edge time submodule comprises a rising edge submodule and a falling edge submodule, and the connection relation among the modules is shown in an attached figure 2 of the specification. The clock with adjustable frequency and duty ratio can be generated while the clock precision is considered only by configuring the rising edge parameter and the period parameter of the clock to be configured.

In this embodiment, the precision of the clock signal is improved, and the related clock parameters are divided into two precision, namely picosecond level and nanosecond level. For example, the clock period is 18ns+125ps, the rising edge time is 7ns+62.5ps, wherein 18ns and 7ns represent nanosecond precision, and 125ps and 62.5ps represent picosecond precision. The clock accuracy that can be generated by the scheme of this embodiment is tens of picoseconds, depending on the highest accuracy that can be achieved. Preferably, the clock accuracy is 62.5 picoseconds.

The main parameters involved in the embodiment are divided into nanosecond level data and picosecond level data, and the nanosecond level data and the picosecond level data are processed and transmitted in different paths respectively, so that better precision control can be realized. Preferably, the edge time parameter includes a first edge parameter and a second edge parameter; the clock cycles include a first clock cycle and a second clock cycle; the remaining time includes a first remaining time and a second remaining time; the delay data comprises first delay data and second delay data; the first delay data, the first remaining time, the first clock cycle, and the first edge parameter are all in nanoseconds; the second delay data, the second remaining time, the second clock period and the second edge parameter are all in picoseconds; the outputs of each stage include picosecond outputs and nanosecond outputs.

In fig. 2 of the accompanying drawings, prd_xns represents a first clock cycle, prd_xps represents a second clock cycle, clk_pos_xns represents a first rising edge remaining time, clk_pos_xps represents a second rising edge remaining time, clk_prd_xns represents a first falling edge remaining time, and clk_prd_xps represents a second falling edge remaining time. For example, the clock period is 18ns+125ps, then the first clock period is 18ns and the second clock period is 125ps.

In the clock signal, the edge instants include rising and falling edges. In this embodiment, only clock period and edge time parameters of the clock are configured, and the edge time parameters are divided into rising edge parameters and falling edge parameters. The default clock cycle is zero, the rising edge is the first edge time, and the falling edge is the end of one clock cycle as shown in fig. 3 and 4 of the specification. The clock period may also default to a falling edge parameter. Therefore, the scheme of the present embodiment requires at least one of the falling edge parameter and the clock period to be acquired in addition to the rising edge parameter. This embodiment takes the example of acquiring the rising edge parameter and the clock period.

Specifically, when the clock period is equal to the system clock period, the clock to be configured and the system clock are equal, and no additional acquisition is required. Therefore, the clock period of the clock to be configured is divided into two cases, the clock period is greater than the system clock period, and the clock period is less than the system clock period. The clock period is larger than the system clock period, which is shown in figure 3 of the specification, and the clock period is smaller than the system clock period, which is shown in figure 4 of the specification. In fig. 3 and 4, the system clock period is 4ns. In fig. 3, the clock parameters are set to 7ns+62.5ps and 18ns+125ps, the rising edge position of the clock signal is 7ns+62.5ps, and the period is 18ns+125ps. In fig. 4, the clock parameters are configured to be 1ns+62.5ps and 2ns+62.5ps, the rising edge position of the clock signal is 1ns+62.5ps, and the period is 2ns+62.5ps.

The first edge parameter includes a first rising edge parameter and a first falling edge parameter, and the second edge parameter includes a second rising edge parameter and a second falling edge parameter. The edge time submodule is divided into a rising edge submodule and a falling edge submodule; the rising edge submodule calculates a plurality of rising edge moments according to the first rising edge parameter and the second rising edge parameter to obtain rising edge nanosecond output and rising edge picosecond output of each stage; and the falling edge submodule calculates a plurality of falling edge moments according to the first falling edge parameter and the second falling edge parameter to obtain falling edge nanosecond output and falling edge picosecond output of each stage.

The edge time submodule includes a multi-stage computation unit. The first-stage computing unit is the most initial computing unit, the computing units at all stages are sequentially connected, the first-stage computing unit is connected with the second-stage computing unit, the second-stage computing unit is connected with the third-stage computing unit … …, and the like.

Each stage of computing unit comprises a picosecond adder and a nanosecond adder. In the same-stage computing unit, the carry output signal of the picosecond adder is the carry input signal of the nanosecond adder.

The nanosecond output signal of the nanosecond adder of each stage of computing unit is a first nanosecond input signal of the nanosecond adder of the next stage of computing unit, the first nanosecond input signal of the nanosecond adder of the first stage of computing unit is a first residual time, and the second nanosecond input signal of each nanosecond adder is a first clock period; each nanosecond adder adds the first nanosecond input signal and the second nanosecond input signal to obtain a nanosecond output signal, and the obtained nanosecond output signal is used as the nanosecond output of each stage.

The picosecond output signal of the picosecond adder of each stage of computing unit is a first picosecond input signal of the picosecond adder of the next stage of computing unit, the first picosecond input signal of the picosecond adder of the first stage of computing unit is a second residual time, and the second picosecond input signal of each picosecond adder is a second clock period; each picosecond adder adds the first picosecond input signal and the second picosecond input signal to obtain a picosecond output signal, and the obtained picosecond output signal is output as picoseconds of each stage.

The structural schematic diagram of the rising edge sub-module is shown in fig. 5 of the specification, and the structural schematic diagram of the falling edge sub-module is shown in fig. 6 of the specification. In FIG. 5, the rising edge submodule is composed of N stages of computing units, each of which is composed of 1 picosecond adder and 1 nanosecond adder, and the input terminal A of the picosecond adder _i The second rising edge remaining time (CLK_POS_XPS) is the output picosecond value of the remaining time submodule, and input terminal B _i For the second clock period (prd_xps). Input terminal A of nanosecond adder _i For the first rising edge remaining time (CLK_POS_XNS), input B _i For a first clock cycle (PRD_XNS), input C _i The carry signal of the picosecond adder of this stage. When the value of the picosecond adder is more than or equal to 1000ps, 1 is added to the nanosecond adder, and after the picosecond adder is carried, 1 is added to the nanosecond adder, so that the number of the computing units is +1.

The schematic structure of the falling edge sub-module is shown in fig. 6 of the specification, and is the same as that of the rising edge sub-module. Wherein the input terminal A of the picosecond adder _i The second falling edge remaining time (CLK_PRD_XPS) for obtaining the output picosecond value of the remaining time submodule, the input terminal A of the nanosecond adder _i For obtaining a first falling edge remaining time (CLK PRD XNS).

In the edge time sub-module, the output of each stage of computing unit is required to be transmitted to the remaining time sub-module, for example, the output of the first stage computing unit and the output of the second stage computing unit are both transmitted to the remaining time sub-module. Specifically, according to the maximum number of edge moments of clocks to be configured in each system clock period, the number of stages of the required computing units is calculated, and the specific expression is as follows:

wherein N isRepresenting the number of stages of the computation unit, M representing the maximum number of edge instants of the clock to be configured per system clock cycle,

log of representation pair ₂ M is rounded up, and the operation is called Ceiling.

If N is a non-integer, then rounding up. For example, at most 3 edge moments exist in a certain system clock period, where M is equal to 3, N of an integer is difficult to obtain, the integer N needs to be rounded up, N of an integer can be obtained when M is equal to 4, and then a 2-stage computing unit is taken. For example, a system clock period of 4ns, a rising edge time information of 1ns+125ps, and a period of 2ns+125ps, requires 2 stages of computation units.

Each stage of the computing unit adds one clock cycle. For example, the primary output of the up-edge sub-module is added once to the clock period (prd_xns, prd_xps) based on the calculated up-edge remaining time register (clk_pos_xns, clk_pos_xps) output of the previous period. The second output of the upper edge sub-module is the second addition of the calculated rising edge remaining time register (clk_pos_xns, clk_pos_xps) output from the previous cycle to the clock cycles (prd_xns, prd_xps), i.e. two clock cycles.

The remaining time sub-module specifically comprises: obtaining the output of each stage and the residual time of the previous system clock period; judging whether the edge time of the clock to be configured exists in the current system clock period or not so as to select corresponding intermediate parameters: if not, taking the remaining time of the previous system clock cycle as an intermediate parameter; if yes, selecting the highest-level output from all levels of outputs, judging the number of edge moments in the system clock period according to the highest-level output, and taking the highest-level output as an intermediate parameter; and calculating the residual time between the current system clock period and the next edge moment according to the intermediate parameter.

The remaining time submodule receives rising edge nanosecond output and rising edge picosecond output of each stage, falling edge nanosecond output and falling edge picosecond output of each stage, divides the nanosecond output and picosecond output and sequentially sorts the nanosecond output and the picosecond output according to the size sequence; and obtaining the waveform shape of each corresponding edge moment according to the sequencing result.

Specifically, the remaining time submodule includes a sorting decision submodule and a time calculation submodule. The sequencing decision sub-module is used for receiving the outputs of all levels and sequencing. The time calculation sub-module comprises a first time calculation sub-unit and a second time calculation sub-unit, wherein the first time calculation sub-unit corresponds to nanosecond calculation, and the second time calculation sub-unit corresponds to picosecond calculation.

And in the first time calculating subunit, after the intermediate parameter is acquired, the intermediate parameter is differenced from the system clock period, and the first residual time of the current system clock period is obtained. The first time calculating subunit is also divided into a first rising edge time calculating subunit and a first falling edge time calculating subunit, which respectively correspond to the rising edge and the falling edge.

In the second time calculation subunit, the obtained intermediate parameter is taken as a second residual time of the current system clock period. The second time calculating subunit is also divided into a second rising edge time calculating subunit and a second falling edge time calculating subunit, which respectively correspond to the rising edge and the falling edge.

Description fig. 7 provides a schematic structural diagram of a remaining time sub-module. In fig. 7, the sort decision submodule receives the multi-level output from the edge time submodule, including the one-level output and the two-level output, and sorts the outputs.

Condition 1 exists: how many edges exist in the current period, condition 2: whether the first edge is a rising or falling edge. When condition 1 and condition 2 are known, all edge moments within the current period can be determined. The sequencing decision sub-module can judge that a plurality of edge moments exist in a system clock period according to the multi-stage output, and N stages of output represent the existence of N edge moments. The picosecond output and the nanosecond output are divided for sorting and are compared separately. Comparing the output values of each stage, wherein the larger the output value of each stage is, the farther the output value of each stage is from the current system clock period is proved; the smaller the output value per stage, the closer to the current system clock cycle is proved. And selecting the output value with the smallest value, and judging whether the output of the stage is sent by the rising edge submodule or the falling edge submodule so as to judge whether the first edge moment is the rising edge or the falling edge.

For example, the current system clock cycle has 2 edge moments, the first edge being a rising edge, the second being a falling edge, and vice versa; when there are 3 edges in the current system clock cycle, if the first edge is a rising edge, the second is a falling edge, and the third is a rising edge. If the first edge is a falling edge, the second is a rising edge and the third is a falling edge. The current system clock cycle has 4 edge moments, and if the first edge is a rising edge, the first edge is followed by a falling edge, a rising edge and a falling edge in sequence.

And acquiring the waveform shape of the configuration clock in the current system clock period according to the sequencing result. For example, if the result of the sorting is (rising edge, falling edge, rising edge), a corresponding waveform (UP, DOWN, UP) is output.

In fig. 7, a time calculation sub-module is provided. The corresponding remaining time calculations are different for nanosecond and picosecond calculations. The first time calculation subunit includes a selector, an adder, and a register. The selector MUX is used for judging whether the edge time of the clock to be configured exists in the current system clock period or not so as to select corresponding intermediate parameters. ADDER subtracts one system clock cycle from the intermediate parameter by making a difference between the intermediate parameter and the system clock cycle. The register DFF is used for registering the calculated first remaining time.

The second time calculation subunit includes a selector MUX and a register DFF. The selector MUX is used for judging whether the edge time of the clock to be configured exists in the current system clock period or not so as to select corresponding intermediate parameters. The register DFF is used for registering the calculated second remaining time.

Wherein the CLK terminal of the register is connected to the system clock cycle.

Specifically, in fig. 7, if there is no edge time within the system clock period, a selector (MUX) in the figure selects the output values (clk_pos_xns, clk_pos_xps, clk_prd_xns, clk_prd_xps) of the register DFF. Wherein, for clk_pos_xns and clk_prd_xns, one system clock cycle is subtracted from each clock cycle.

The obtained first residual time is also used as first delay data to be output to the waveform output sub-module, and the second residual time is used as second delay data to be output to the waveform output sub-module. In fig. 7, the register outputs clk_pos_xns, clk_pos_xps, clk_prd_xns, clk_prd_xps are output to the waveform output sub-module.

In this embodiment, the waveform output submodule includes a coarse-granularity delay unit and a fine-granularity delay unit; the coarse granularity time delay unit delays according to the first time delay data in nanoseconds; the fine-granularity delay unit delays in picoseconds according to the second delay data. The edge moment calculation submodule outputs delay time, the rest time submodule outputs waveform shape, and the waveform output submodule can generate a high-precision clock waveform signal according to the waveform shape and delay data.

The delay data comprises first delay data and second delay data, and the first delay data and the second delay data comprise relevant data of rising edges and falling edges. The coarse-granularity delay unit receives the first delay data, and the fine-granularity delay unit receives the second delay unit. The first residual time is used as first delay data to be output to the coarse granularity delay unit, and the second residual time is used as second delay data to be output to the fine granularity delay unit.

Preferably, OSerdes in the FPGA chip is used as a coarse-granularity delay unit, and a delay carry chain is used as a fine-granularity delay unit. In addition, the fine granularity delay unit can also adopt a high-speed high-precision ASIC chip.

Preferably, the coarse-grained delay element has a resolution of 1ns and an Oserdes mode of operation of 1:4. The resolution of the delay carry chain is 62.5ps, and the delay carry chain is composed of a plurality of sub-chains which are sequentially connected in series, and each sub-chain represents 62.5ps of delay.

For example, the system clock is 250MHz, oserdes is in a 1:4 mode of operation, the resolution of coarse-grained delay elements is 1ns, and the resolution of the delay chain is 62.5ps. If the low level duration is (x+m/16) (ns), the high level duration is (y+n/16) (ns), wherein x is greater than or equal to 1, y is greater than or equal to 1, m is greater than or equal to 0, n is greater than or equal to 0, the generated clock duty cycle is 16x+m)/(16x+16y+m+n) (GHz), and the clock frequency is 16/(16x+16y+m+n). By setting the values of m and n, a wide range of adjustments of clock frequency and duty cycle can be achieved. The scheme of the embodiment can generate stable clock signals, the clock frequency and the duty ratio can be adjusted in a large range, and the requirements of ATE equipment on various working clocks can be met.

The embodiment provides a clock generation method in ATE equipment, which combines clock precision and clock parameter flexibility. The scheme can realize the large-scale adjustment of the clock frequency and the clock duty ratio while considering the clock precision only by configuring the rising edge parameter and the period parameter of the clock to be configured. The clock signal is respectively carried out according to two paths of nanosecond level and picosecond level in the generation process, and on the basis of guaranteeing the basic shape of the waveform, the precision of the clock signal is improved, so that the generated high-precision clock signal can meet the precision requirement of ATE equipment.

Example 2

The embodiment 2 of the invention discloses a clock generation system in ATE equipment, the clock generation method in ATE equipment of the embodiment 1 is systemized, the structural block diagram of the system is shown in an attached figure 8 of the specification, and the structural relationship among the modules is shown in an attached figure 2 of the specification. The specific scheme is as follows:

a clock generation system in an ATE device, comprising:

the clock parameter acquisition submodule 1 is used for setting a system clock period, acquiring clock parameters of a clock to be configured and analyzing the clock period and the edge time parameters from the clock parameters;

the edge time sub-module 2 is used for acquiring the residual time output by the preset residual time sub-module 3, calculating the output of each level by combining with a clock period, transmitting the output to the residual time sub-module 3, calculating a plurality of subsequent edge times according to the edge time parameters, and outputting delay data of each edge time;

A remaining time sub-module 3, configured to select a corresponding update policy according to the number of edge moments in each system clock cycle to output a corresponding remaining time, and obtain a waveform shape of each edge moment according to the received output of each stage; the residual time is the time interval between the current system clock cycle and the next edge moment;

the waveform output sub-module 4 is configured to generate a clock waveform of the clock to be configured according to the waveform shape and the delay data of each edge time under the control of the system clock.

The edge time submodule 2 comprises a rising edge submodule 21 and a falling edge submodule 22;

the rising edge sub-module 21 includes a plurality of stages of computing units, wherein the one stage of computing unit is the most initial computing unit; each stage of computing unit comprises a picosecond adder and a nanosecond adder;

in the same-stage computing unit, the carry output end of the picosecond adder is connected with the carry input end of the nanosecond adder;

the nanosecond output end of the nanosecond adder of each level of computing unit is connected with the first nanosecond input end of the nanosecond adder of the next level of computing unit, the first nanosecond input end of the nanosecond adder of the first level of computing unit is used for acquiring the first residual time, and the second nanosecond input end of each nanosecond adder is used for acquiring the first clock period;

Each nanosecond adder is used for adding the signal of the first nanosecond input end and the signal of the second nanosecond input end to obtain a nanosecond output signal, and the obtained nanosecond output signal is used as the nanosecond output of each stage;

the picosecond output end of the picosecond adder of each stage of computing unit is connected with the first picosecond input end of the picosecond adder of the next stage of computing unit, the first picosecond input end of the picosecond adder of the first stage of computing unit is used for acquiring second residual time, and the second picosecond input end of each picosecond adder is used for acquiring a second clock period;

each picosecond adder is used for adding the signal of the first picosecond input end and the signal of the second picosecond input end to obtain a picosecond output signal, and the obtained picosecond output signal is used as the picosecond output of each stage;

the falling edge sub-module 22 is identical in structure to the rising edge sub-module 21.

The remaining time sub-module 3 includes a sorting decision sub-module 33, a first time calculation sub-unit 31 and a second time calculation sub-unit 32;

a sorting decision sub-module 33, configured to receive the rising edge nanosecond output and the rising edge picosecond output of each stage, and the falling edge nanosecond output and the falling edge picosecond output of each stage, divide the nanosecond output and the picosecond output, and sequentially sort the nanosecond output and the picosecond output according to a size order; obtaining the waveform shape of each corresponding edge moment according to the sequencing result;

A first time calculating subunit 31, provided with a first adder and a first register, configured to, after obtaining the intermediate parameter, make a difference between the intermediate parameter and the system clock cycle through the first adder, obtain a first remaining time of the current system clock cycle, and register the first remaining time in the first register;

the second time calculation subunit 32 is provided with a second register, and is configured to register the acquired intermediate parameter as a second remaining time of the current system clock cycle in the second register.

The present embodiment provides a clock generation system in an ATE device, and the clock generation method in an ATE device of embodiment 1 is systemized.

The invention provides a clock generation method and a clock generation system in ATE equipment, which are capable of considering clock precision and clock parameter flexibility. The scheme can realize the large-scale adjustment of the clock frequency and the clock duty ratio while considering the clock precision only by configuring the rising edge parameter and the period parameter of the clock to be configured. The clock signal is respectively carried out according to two paths of nanosecond level and picosecond level in the generation process, and on the basis of guaranteeing the basic shape of the waveform, the precision of the clock signal is improved, so that the generated high-precision clock signal can meet the precision requirement of ATE equipment.

Those skilled in the art will appreciate that the drawing is merely a schematic illustration of a preferred implementation scenario and that the modules or flows in the drawing are not necessarily required to practice the invention. Those skilled in the art will appreciate that modules in an apparatus in an implementation scenario may be distributed in an apparatus in an implementation scenario according to an implementation scenario description, or that corresponding changes may be located in one or more apparatuses different from the implementation scenario. The modules of the implementation scenario may be combined into one module, or may be further split into a plurality of sub-modules. The above-mentioned inventive sequence numbers are merely for description and do not represent advantages or disadvantages of the implementation scenario. The foregoing disclosure is merely illustrative of some embodiments of the invention, and the invention is not limited thereto, as modifications may be made by those skilled in the art without departing from the scope of the invention.

Claims (12)

1. A method of clock generation in an ATE device, comprising:

setting a system clock period, acquiring clock parameters of a clock to be configured, and analyzing the clock period and edge time parameters from the clock parameters;

the preset edge time submodule acquires the residual time output by the preset residual time submodule, calculates the output of each level by combining the clock period, transmits the output to the residual time submodule, calculates a plurality of subsequent edge times according to the edge time parameter, and outputs delay data of each edge time;

In the residual time submodule, a corresponding update strategy is selected according to the number of edge moments in each system clock period to output corresponding residual time, and the waveform shape of each edge moment is obtained according to received output of each stage; wherein the remaining time is a time interval between a current system clock cycle and a next edge time;

and the preset waveform output submodule generates a clock waveform of the clock to be configured according to the waveform shape and delay data of each edge moment under the control of the system clock.

2. The clock generation method of claim 1, wherein selecting the corresponding update strategy to output the corresponding remaining time based on the number of edge moments per system clock cycle comprises:

obtaining the output of each stage and the residual time of the previous system clock period;

judging whether the edge time of the clock to be configured exists in the current system clock period:

if not, taking the remaining time of the previous system clock cycle as an intermediate parameter, and storing the intermediate parameter into a preset register;

if yes, selecting the highest-level output from all levels of outputs, judging the number of edge moments in the system clock period according to the highest-level output, taking the highest-level output as an intermediate parameter, and storing the intermediate parameter into a preset register;

And calculating the residual time between the current system clock cycle and the next edge moment according to the intermediate parameter.

3. The clock generation method according to claim 2, wherein the edge time parameters include a first edge parameter and a second edge parameter;

the clock cycles include a first clock cycle and a second clock cycle;

the remaining time includes a first remaining time and a second remaining time;

the delay data comprises first delay data and second delay data;

the first delay data, the first remaining time, the first clock period, and the first edge parameter are all in nanoseconds;

the second delay data, the second remaining time, the second clock period, and the second edge parameter are all in picoseconds;

the outputs of each stage include picosecond outputs and nanosecond outputs.

4. The clock generation method of claim 3, wherein the edge time submodule includes a plurality of stages of calculation units, wherein a stage of calculation unit is an initial calculation unit;

each stage of computing unit comprises a picosecond adder and a nanosecond adder;

in the same-stage computing unit, the carry output signal of the picosecond adder is the carry input signal of the nanosecond adder;

The nanosecond output signal of the nanosecond adder of each stage of computing unit is a first nanosecond input signal of the nanosecond adder of the next stage of computing unit, the first nanosecond input signal of the nanosecond adder of the first stage of computing unit is the first residual time, and the second nanosecond input signal of each nanosecond adder is the first clock period; each nanosecond adder adds the first nanosecond input signal and the second nanosecond input signal to obtain a nanosecond output signal, and the obtained nanosecond output signal is used as the nanosecond output of each stage;

the picosecond output signal of the picosecond adder of each stage of computing unit is the first picosecond input signal of the picosecond adder of the next stage of computing unit, the first picosecond input signal of the picosecond adder of the first stage of computing unit is the second residual time, and the second picosecond input signal of each picosecond adder is the second clock period; each picosecond adder adds the first picosecond input signal and the second picosecond input signal to obtain a picosecond output signal, and the obtained picosecond output signal is output as picoseconds of each stage.

5. The clock generation method according to claim 4, wherein the number of stages of the required calculation unit is calculated according to the maximum number of edge moments of the clock to be configured in each system clock cycle, and the specific expression is as follows:

Wherein N represents the number of stages of the calculation unit, M represents the maximum number of edge moments of clocks to be configured in each system clock period,

log of representation pair ₂ M is rounded upwards;

if N is a non-integer, then rounding up.

6. The clock generation method of claim 4, wherein the first edge parameter comprises a first rising edge parameter and a first falling edge parameter, and the second edge parameter comprises a second rising edge parameter and a second falling edge parameter;

the edge time submodule is divided into a rising edge submodule and a falling edge submodule;

the rising edge submodule calculates a plurality of rising edge moments according to the first rising edge parameter and the second rising edge parameter to obtain rising edge nanosecond output and rising edge picosecond output of each stage;

and the falling edge submodule calculates a plurality of falling edge moments according to the first falling edge parameter and the second falling edge parameter to obtain falling edge nanosecond output and falling edge picosecond output of each stage.

7. The clock generation method of claim 6, wherein the remaining time submodule receives rising edge nanosecond output and rising edge picosecond output of each stage, falling edge nanosecond output and falling edge picosecond output of each stage, divides the nanosecond output and picosecond output, and sequentially sorts them in order of magnitude;

And obtaining the waveform shape of each corresponding edge moment according to the sequencing result.

8. A clock generation method according to claim 3, wherein the remaining time submodule comprises a time calculation submodule comprising a first time calculation subunit and a second time calculation subunit;

in the first time calculating subunit, after obtaining an intermediate parameter, making a difference between the intermediate parameter and a system clock cycle to obtain a first residual time of the current system clock cycle;

and in the second time calculation subunit, taking the acquired intermediate parameter as a second residual time of the current system clock cycle.

9. A clock generation method according to claim 3, wherein the waveform output submodule includes a coarse granularity delay unit and a fine granularity delay unit;

the coarse granularity time delay unit delays according to the first time delay data in nanoseconds;

and the fine-granularity delay unit delays according to the second delay data by taking picoseconds as a unit.

10. A clock generation system in an ATE device, comprising:

the clock parameter acquisition sub-module is used for setting a system clock period, acquiring clock parameters of a clock to be configured, and analyzing the clock period and the edge time parameters from the clock parameters;

The edge time submodule is used for acquiring the residual time output by the preset residual time submodule, calculating the output of each level by combining the clock period, transmitting the output to the residual time submodule, calculating a plurality of subsequent edge times according to the edge time parameters, and outputting delay data of each edge time;

the residual time sub-module is used for selecting a corresponding updating strategy according to the number of edge moments in each system clock period to output corresponding residual time, and obtaining the waveform shape of each edge moment according to the received output of each stage; the residual time is the time interval between the current system clock cycle and the next edge moment;

and the waveform output sub-module is used for generating clock waveforms of clocks to be configured according to waveform shapes and delay data of all edge moments under the control of a system clock.

11. The clock generation system of claim 10, wherein the edge time submodule includes a rising edge submodule and a falling edge submodule;

the rising edge submodule comprises a plurality of stages of computing units, wherein the one-stage computing unit is the most initial computing unit; each stage of computing unit comprises a picosecond adder and a nanosecond adder;

In the same-stage computing unit, the carry output end of the picosecond adder is connected with the carry input end of the nanosecond adder;

the nanosecond output end of the nanosecond adder of each level of computing unit is connected with the first nanosecond input end of the nanosecond adder of the next level of computing unit, the first nanosecond input end of the nanosecond adder of the level of computing unit is used for acquiring first residual time, and the second nanosecond input end of each nanosecond adder is used for acquiring a first clock period;

each nanosecond adder is used for adding the signal of the first nanosecond input end and the signal of the second nanosecond input end to obtain a nanosecond output signal, and the obtained nanosecond output signal is used as the nanosecond output of each stage;

the picosecond output end of the picosecond adder of each stage of computing unit is connected with the first picosecond input end of the picosecond adder of the next stage of computing unit, the first picosecond input end of the picosecond adder of the first stage of computing unit is used for acquiring second residual time, and the second picosecond input end of each picosecond adder is used for acquiring a second clock period;

each picosecond adder is used for adding the signal of the first picosecond input end and the signal of the second picosecond input end to obtain a picosecond output signal, and the obtained picosecond output signal is used as the picosecond output of each stage;

The falling edge submodule has the same structure as the rising edge submodule.

12. The clock generation system of claim 10, wherein the remaining time submodule includes a sequencing decision submodule, a first time calculation submodule, and a second time calculation submodule;

the sequencing judgment sub-module is used for receiving rising edge nanosecond output and rising edge picosecond output of each stage, falling edge nanosecond output and falling edge picosecond output of each stage, dividing the nanosecond output and picosecond output, and sequencing sequentially according to the size sequence; obtaining the waveform shape of each corresponding edge moment according to the sequencing result;

the first time calculating subunit is provided with a first adder and a first register, and is used for obtaining a first residual time of a current system clock period and registering the first residual time into the first register by making a difference between the intermediate parameter and the system clock period through the first adder after the intermediate parameter is obtained;

the second time calculating subunit is provided with a second register, and is used for taking the acquired intermediate parameter as the second residual time of the current system clock period and registering the second residual time into the second register.

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