CN110600428A - Method for manufacturing semiconductor element - Google Patents
Method for manufacturing semiconductor element Download PDFInfo
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- CN110600428A CN110600428A CN201810601536.7A CN201810601536A CN110600428A CN 110600428 A CN110600428 A CN 110600428A CN 201810601536 A CN201810601536 A CN 201810601536A CN 110600428 A CN110600428 A CN 110600428A
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- Prior art keywords
- oxide layer
- voltage region
- manufacturing process
- low voltage
- forming
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
- H01L21/02301—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment in-situ cleaning
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses a method for manufacturing a semiconductor element, which comprises the steps of forming a first oxidation layer on a high-voltage area and a low-voltage area; performing an atomic layer deposition manufacturing process to form a second oxide layer on the first oxide layer, wherein the atomic layer deposition manufacturing process has a power of 50-400W; carrying out an annealing manufacturing process, wherein the temperature of the annealing manufacturing process is between 80 and 500 ℃; removing a portion of the first oxide layer and the second oxide layer covering the low voltage region; forming a third oxide layer on the high voltage region and the low voltage region; and forming a gate structure on the high-voltage region and the low-voltage region to form a high-voltage transistor and a low-voltage transistor. The method provided by the invention can effectively reduce the ion accumulation caused by the atomic layer deposition manufacturing process, thereby avoiding the catalysis of the subsequent manufacturing process steps on the damage of the substrate.
Description
Technical Field
The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for preventing a substrate from being damaged during a fabrication process.
Background
Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic products. In addition, under the current social trend of pursuing multi-functionality and high performance, in order to enable different devices with different voltages to operate smoothly on a chip, steps for manufacturing different threshold voltages are introduced into a semiconductor manufacturing process on a single chip.
In general, low supply voltage transistors (commonly referred to as logic transistors or core transistors) are typically optimized for high packing density and performance in a die or chip (hereinafter "chip"); high supply voltage transistors are commonly used to communicate with external devices/chips and are therefore labeled as input/output (I/O) transistors. Logic transistors are small and have thin gate oxide to maximize speed at low voltages; on the other hand, input/output (I/O) transistors are bulky and have a thick gate oxide layer to achieve reliable high voltage operation.
In order to realize that adjacent regions have gate oxide layers with different thicknesses, the gate oxide layers need to be formed on different voltage regions respectively, and different process procedures need to be carried out in the manufacturing process aiming at the different voltage regions, but the phenomenon of substrate erosion generated in partial regions is caused, so that the problem of unstable product yield is caused.
Disclosure of Invention
To solve the above problems, the present invention provides a method for fabricating a semiconductor device, which includes forming a first oxide layer on a high voltage region and a low voltage region; performing an atomic layer deposition manufacturing process to form a second oxide layer on the first oxide layer, wherein the atomic layer deposition manufacturing process has a power of 50-400W; carrying out an annealing manufacturing process, wherein the temperature of the annealing manufacturing process is between 80 and 500 ℃; removing a portion of the first oxide layer and the second oxide layer covering the low voltage region; forming a third oxide layer on the high voltage region and the low voltage region; and forming a gate structure on the high voltage region and the low voltage region to form a high voltage transistor and a low voltage transistor.
In an embodiment of the invention, the time of the annealing process is between 5 seconds and 60 minutes.
In an embodiment of the invention, the time of the annealing process is between 5 seconds and 10 minutes.
In an embodiment of the invention, before forming the third oxide layer, the method further includes: the pre-cleaning step is performed for 150 to 600 seconds.
In an embodiment of the invention, the cleaning liquid used in the pre-cleaning step includes Hydrogen Fluoride (HF).
In an embodiment of the invention, the cleaning solution further includes ammonium fluoride (NH)4F)。
In an embodiment of the invention, the ammonium fluoride accounts for 5% to 45% of the weight of the cleaning solution, and the hydrogen fluoride accounts for 0.1% to 10% of the weight of the etching solution.
In an embodiment of the invention, the low voltage transistor is an NMOS transistor.
In an embodiment of the invention, the low voltage transistor is a logic transistor.
In an embodiment of the invention, a thickness of the first oxide layer is between 80 and 200 angstroms.
In an embodiment of the invention, a thickness of the second oxide layer is between 20 and 100 angstroms.
In an embodiment of the invention, a thickness of the third oxide layer is between 12 and 50 angstroms.
According to the invention, through the low-temperature thermal annealing manufacturing process carried out after the atomic layer deposition manufacturing, the ion accumulation caused by the atomic layer deposition manufacturing process can be effectively reduced, and the catalysis of subsequent manufacturing process steps on the damage of the substrate is further avoided. In addition, in order to further reduce the ion accumulation on the surface of the substrate, the time of the pre-cleaning step after the photoresist is removed and before the core transistor gate electrode oxide layer is formed can be selectively prolonged, and experiments prove that the ion accumulation can be effectively reduced, and the yield of subsequent products is also obviously improved.
Drawings
FIG. 1 is a schematic cross-sectional view of a portion of a manufacturing process according to an embodiment of the present invention;
FIG. 2 is a partial cross-sectional view of the step of forming an oxide layer according to the embodiment of FIG. 1;
FIG. 3 is a partial cross-sectional view of a step of forming a photoresist according to the embodiment of the invention shown in FIG. 2;
FIG. 4 is a partial cross-sectional view of the step of removing the photoresist and a portion of the oxide layer according to the embodiment of the present invention shown in FIG. 3;
FIG. 5 is a partial cross-sectional view of another step of forming an oxide layer according to the embodiment of FIG. 4;
FIG. 6 is a partial cross-sectional view of a step of forming a gate structure according to the embodiment of the invention shown in FIG. 5.
Detailed Description
The present invention provides a method for fabricating a semiconductor device, which can avoid the problem of erosion of a part of a substrate caused by different fabrication processes performed on the substrate, thereby improving the yield of the product. In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, several preferred embodiments accompanied with figures are described in detail below.
Referring to fig. 1 to 6, fig. 1 is a schematic diagram illustrating a partial cross-sectional structure of a semiconductor device in different processes according to an embodiment of the invention. As shown in fig. 1, the semiconductor device includes a substrate 10, the substrate 10 includes a low voltage region R1 and a high voltage region R2, and the low voltage region R1 and the high voltage region R2 are separated by an isolation structure 13. Since the structure shown in fig. 1 can be realized by applying the prior art and manufacturing processes, the detailed manufacturing process and structure are not described herein, for example, the structure may further include doped regions such as well (deep well) regions, deep well (deep well), and the like, which can be understood by those skilled in the art according to the disclosure of the present invention or adjusted as required. The structure shown in FIG. 1 is for illustration purposes only and is not intended to limit the present invention; in addition, the existing semiconductor front-end manufacturing process structure may also be directly applied, for example, the doping concentration and type may be adjusted as needed, for example, N-type metal-oxide-semiconductor (NMOS) or P-type metal-oxide-semiconductor (PMOS), which is not limited and described herein. Generally, the low-voltage supply transistors (i.e., core transistors) are NMOS, and the embodiment is described with the low-voltage region R1 being an NMOS region, which can also be understood as a logic region, and then a logic transistor (or core transistor) is formed in this region by the following fabrication process.
Next, as shown in fig. 2, a first oxide layer 21 is formed by using a Rapid Thermal Oxidation (RTO) process, and then a second oxide layer 22 is formed by using an atomic deposition (ALD) process, wherein the first oxide layer 21 and the second oxide layer 22 together form a first gate oxide layer 20, which is subsequently used as a partial gate oxide layer of a high-voltage transistor, and the high-voltage transistor can realize reliable high-voltage operation, and two processes are used to form the first gate oxide layer 20 with a sufficient thickness by stacking. The thicknesses of the first oxide layer 21 and the second oxide layer 22 can be adjusted according to different product specifications; in a preferred embodiment of the present invention, the first oxide layer 21 has a thickness of between 80 and 200 angstroms (angstroms), and the second oxide layer has a thickness of between 20 and 100 angstroms.
The present inventors have studied about the technical problems of the conventional process, and found that ions generated during the process of forming an oxide layer are accumulated on the substrate 10, especially, the ions are more likely to be accumulated on the surface of the substrate 10 due to the atomic deposition process commonly used in the conventional semiconductor manufacturing process, which causes the substrate 10 to react with silicon during the catalysis of the subsequent manufacturing process steps, thereby causing erosion and damage to the substrate 10.
Accordingly, the atomic deposition process power is preferably between 50 to 400 watts, the low power ALD process is effective to reduce the ion accumulation compared to the high power ALD process, and the ALD process is followed by a low temperature thermal annealing process at a temperature of 80 to 500 degrees celsius for a time of 5 seconds to 60 minutes, preferably 5 seconds to 10 minutes. The low temperature thermal annealing process can effectively reduce the ion accumulation, and the reduction of the ion accumulation may have an adverse effect due to the higher energy provided by the low temperature thermal annealing process compared to the high temperature thermal annealing process (e.g., 800 to 1000 degrees celsius).
The patterned photoresist layer PR is then formed as shown in fig. 3, covering the high voltage region R2 and exposing the low voltage region R1 to the patterned photoresist layer PR. Using the patterned photoresist layer PR as a mask, a portion of the first gate oxide layer 20 (i.e., the exposed first oxide layer 21 and the exposed second oxide layer 22) covering the low voltage region R1 is removed by etching, plasma or other suitable means, which is not limited herein. The patterned photoresist layer PR is then removed, as shown in fig. 4.
Before the logic area gate oxide layer forming procedure, the substrate 10 and the remaining first gate oxide layer 20 are pre-cleaned. The cleaning solution preferably contains Hydrogen Fluoride (HF), oxide buffered etching solution (BOE) or ammonium fluoride (NH)4F) And Hydrogen Fluoride (HF). In some preferred embodiments of the invention, the hydrogen fluoride accounts for 0.1-49% of the cleaning solution by weight, and the balance is water; in other preferred embodiments of the present invention, the ammonium fluoride accounts for 5-45% of the weight of the cleaning solution, the hydrogen fluoride accounts for 0.1-10% of the weight of the etching solution, and the balance is water.
Since ions may be accumulated on the surface of the substrate 10 during the process of removing the patterned photoresist PR, in order to prevent the ions from reacting with the substrate 10 in the subsequent process, in the preferred embodiment of the present invention, the time of the pre-cleaning step is between 150 to 600 seconds, which can effectively reduce the ions accumulated on the surface of the substrate 10.
As shown in fig. 5, a rapid thermal oxidation process is performed after the preclean step to form a third oxide layer 30 on the low voltage region R1 and the high voltage region R2. The third oxide layer 30 is used as a gate oxide layer of a subsequent logic transistor in the low voltage region R1, and the thickness of the gate oxide layer of the subsequent high supply voltage transistor in the high voltage region R2 can be fine-tuned to compensate for a slight thickness of the first gate oxide layer 20 below the patterned photoresist layer PR that may be removed when the patterned photoresist layer PR is removed, but the invention is not limited thereto. In the preferred embodiment of the present invention, the thickness of the third oxide layer 30 is preferably between 12 to 50 angstroms.
Then, the gate structure 41 and the gate structure 42, and the source/drain 11 of the low voltage region R1 and the source/drain 12 of the high voltage region R2 are formed on the low voltage region R1 and the high voltage region R2, respectively, as shown in fig. 6, the low supply voltage transistor 100 and the high supply voltage transistor 200 are formed. Taking fig. 6 as an example for illustration, the gate structure 41 includes a gate electrode layer 411 and a spacer 412, and the gate structure 42 includes a gate electrode layer 421 and a spacer 422, but the detailed structure and material of the gate electrode structures 41 and 42 are not limited herein and can be adjusted according to the existing process and actual requirements; although not shown, other structures such as well regions (wells), deep well regions (deep wells) may be understood or modified by those skilled in the art in light of the present disclosure. Moreover, although fig. 6 illustrates the gate structures of the high voltage region R1 and the low voltage region R2, the included gate electrode layers and the spacers as the same configuration for convenience of illustration, the gate structures, the gate electrode layers and the spacers of the two regions, the detailed structures and materials thereof, etc. may be the same or different, and may be adjusted according to the prior art and actual requirements without departing from the spirit of the present invention, and the structures and symbols shown in fig. 6 are only for convenience of illustration and understanding, and are not intended to limit the present invention.
Through practical tests of the inventor, compared with the method only adopting the high-power ALD manufacturing process, the low-temperature thermal annealing manufacturing process adopted by the invention after the low-power ALD manufacturing process is matched can effectively reduce ion accumulation by more than 40%; in addition, compared with the short-time precleaning step which is carried out by the prior art for removing residues or pollutants, the invention can further reduce the ion accumulation by more than 20 percent by additionally matching with the long-time precleaning step.
While the invention is disclosed in conjunction with the above embodiments, it is not intended to limit the invention thereto. It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the protection scope of the present invention should be subject to the definition of the appended claims.
Claims (12)
1. A method of fabricating a semiconductor device, comprising:
forming a first oxide layer on the high voltage region and the low voltage region;
performing an atomic layer deposition manufacturing process to form a second oxide layer on the first oxide layer, wherein the atomic layer deposition manufacturing process has a power of 50-400W;
carrying out an annealing manufacturing process, wherein the temperature of the annealing manufacturing process is between 80 and 500 ℃;
removing a portion of the first oxide layer and the second oxide layer covering the low voltage region;
forming a third oxide layer on the high voltage region and the low voltage region; and
forming gate structures on the high voltage region and the low voltage region to form high voltage transistors and low voltage transistors.
2. The method of claim 1, wherein the annealing process takes between 5 seconds and 60 minutes.
3. The method of claim 2, wherein the annealing process is performed for a time period ranging from 5 seconds to 10 minutes.
4. The method of claim 1, wherein prior to forming the third oxide layer, the method further comprises:
the pre-cleaning step is performed for 150 to 600 seconds.
5. The method of claim 4, wherein the pre-cleaning step uses a cleaning fluid comprising hydrogen fluoride.
6. The method of claim 5, wherein the cleaning fluid further comprises ammonium fluoride.
7. The method of claim 6, wherein the ammonium fluoride comprises 5% to 45% by weight of the cleaning solution and the hydrogen fluoride comprises 0.1% to 10% by weight of the etching solution.
8. The method of claim 1, wherein the low voltage transistor is an NMOS transistor.
9. The method of claim 1, wherein the low voltage region is a logic region.
10. The method of claim 1, wherein the first oxide layer has a thickness of between 80 and 200 angstroms.
11. The method of claim 1, wherein the second oxide layer has a thickness between 20 and 100 angstroms.
12. The method of claim 1, wherein the third oxide layer has a thickness between 12 and 50 angstroms.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810601536.7A CN110600428A (en) | 2018-06-12 | 2018-06-12 | Method for manufacturing semiconductor element |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810601536.7A CN110600428A (en) | 2018-06-12 | 2018-06-12 | Method for manufacturing semiconductor element |
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| CN110600428A true CN110600428A (en) | 2019-12-20 |
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| CN201810601536.7A Pending CN110600428A (en) | 2018-06-12 | 2018-06-12 | Method for manufacturing semiconductor element |
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Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050136632A1 (en) * | 2003-12-17 | 2005-06-23 | Rotondaro Antonio L. | Implementation of split gate transistor technology with high-k gate dielectrics |
| US20060078678A1 (en) * | 2004-10-13 | 2006-04-13 | Samsung Electronics Co., Ltd. | Method of forming a thin film by atomic layer deposition |
| CN101271840A (en) * | 2007-03-22 | 2008-09-24 | 中芯国际集成电路制造(上海)有限公司 | Production method of gate oxide layer and semiconductor device |
| CN102909204A (en) * | 2011-08-05 | 2013-02-06 | 美新半导体（无锡）有限公司 | Method for cleaning wafer after deep silicon etching process |
| CN102931203A (en) * | 2011-08-11 | 2013-02-13 | 台湾积体电路制造股份有限公司 | Multiple gate dielectric structures and methods of forming the same |
| JP2015079937A (en) * | 2014-07-18 | 2015-04-23 | 三井造船株式会社 | Film formation apparatus and film formation method |
| CN105374754A (en) * | 2014-08-28 | 2016-03-02 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device manufacturing method |
| CN107305846A (en) * | 2016-04-18 | 2017-10-31 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method thereof |
-
2018
- 2018-06-12 CN CN201810601536.7A patent/CN110600428A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050136632A1 (en) * | 2003-12-17 | 2005-06-23 | Rotondaro Antonio L. | Implementation of split gate transistor technology with high-k gate dielectrics |
| US20060078678A1 (en) * | 2004-10-13 | 2006-04-13 | Samsung Electronics Co., Ltd. | Method of forming a thin film by atomic layer deposition |
| CN101271840A (en) * | 2007-03-22 | 2008-09-24 | 中芯国际集成电路制造(上海)有限公司 | Production method of gate oxide layer and semiconductor device |
| CN102909204A (en) * | 2011-08-05 | 2013-02-06 | 美新半导体（无锡）有限公司 | Method for cleaning wafer after deep silicon etching process |
| CN102931203A (en) * | 2011-08-11 | 2013-02-13 | 台湾积体电路制造股份有限公司 | Multiple gate dielectric structures and methods of forming the same |
| JP2015079937A (en) * | 2014-07-18 | 2015-04-23 | 三井造船株式会社 | Film formation apparatus and film formation method |
| CN105374754A (en) * | 2014-08-28 | 2016-03-02 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device manufacturing method |
| CN107305846A (en) * | 2016-04-18 | 2017-10-31 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method thereof |
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Application publication date: 20191220 |