CN110581709A - 一种基于多级同步的零延时锁相环频率综合器 - Google Patents

一种基于多级同步的零延时锁相环频率综合器 Download PDF

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CN110581709A
CN110581709A CN201910812883.9A CN201910812883A CN110581709A CN 110581709 A CN110581709 A CN 110581709A CN 201910812883 A CN201910812883 A CN 201910812883A CN 110581709 A CN110581709 A CN 110581709A
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phase
synchronization module
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徐志伟
陈姜波
刘嘉冰
聂辉
丁凯杰
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Yantai Xin Yang Ju Array Microelectronics Co ltd
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Zhejiang University ZJU
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
    • H03L7/193—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number the frequency divider/counter comprising a commutable pre-divider, e.g. a two modulus divider
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0818—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter comprising coarse and fine delay or phase-shifting means
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
    • H04B1/40—Circuits

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Abstract

本发明公开了一种基于多级同步的零延时锁相环频率综合器，属于集成电路技术领域。该零延时锁相环频率综合器包括：鉴频鉴相器、电荷泵、环路滤波器、压控振荡器和多级同步分频器。所述鉴频鉴相器、电荷泵、环路滤波器以及压控振荡器依次连接；所述压控振荡器的输出OUT与所述多级同步分频器的输入IN相连，所述多级同步分频器的输出OUT与所述鉴频鉴相器的输入IN相连，形成反馈通路。本发明通过在反馈环路上对输出信号的多级同步，使得输出信号与参考信号的相位一致，来实现零延时锁相环的功能。与传统技术相比，本发明更为简单，不需要在锁相环电路中加入多个可调延时单元用以实现输出信号与参考信号的相位对齐，降低了电路复杂度和系统功耗。

Description

一种基于多级同步的零延时锁相环频率综合器
技术领域
本发明涉及集成电路技术领域，具体地涉及一种基于多级同步的零延时锁相环频率综合器。
背景技术
锁相环(phase locked loop)是一种频率控制系统，在电路设计中的应用非常广泛，包括时钟产生、时钟恢复、抖动与噪声降低、频率合成等等。PLL的操作都是基于参考时钟信号和压控振荡器(VCO)输出时钟信号的反馈之间的相位差进行的。传统PLL包含鉴频鉴相器(Phase Frequency Detector)，电荷泵(Charge Pump)，环路滤波器(Loop PassFilter)，压控振荡器(Voltage Control Oscillator)以及一个反馈环路上的分频器(Divider)。对于理想电路而言，分频器由压控振荡器输出的时钟信号边缘触发的，因此其输入输出的时钟信号应该是边缘对齐的，而压控振荡器经过分频器输出的反馈时钟信号与参考时钟信号之间则通过环路对齐，最终实现压控振荡器输出的时钟信号与参考时钟信号之间相位一致。但在实际电路中，由于分频器中各个模块存在大量的非线性延时，这就使得即使反馈的时钟信号与参考时钟信号相位一致了，也依然无法确定压控振荡器输出时钟信号的准确相位。
而为了克服这一问题，就有了零延时时钟技术。传统的零延时时钟技术是在反馈环路上加一个可调的延时单元，通过数字电路自动校准或者是人为的调整来得到零延时时钟。但这显然极大的增加了电路的复杂度。
发明内容
本发明的目的在于不增加电路复杂度的情况下，提供一个与参考时钟信号相位一致的输出时钟信号，本发明提供了一种基于多级同步的零延时锁相环频率综合器。
为实现上述目的，本发明使用了树状连接的多级同步结构，在一定程度上降低了对整体电路非线性延时的要求。本发明是通过以下技术方案实现的：一种基于多级同步的零延时锁相环频率综合器，所述零延时锁相环频率综合器包括：鉴频鉴相器、电荷泵、环路滤波器、压控振荡器和多级同步分频器。所述鉴频鉴相器的输出OP端连接电荷泵的输入IP端，所述鉴频鉴相器的输出ON端连接电荷泵的输入IN端，所述电荷泵的输出端连接所述环路滤波器的输入端，所述环路滤波器的输出端连接所述压控振荡器的输入端，所述压控振荡器的输出端与所述多级同步分频器的输入端相连，所述多级同步分频器的输出端与所述鉴频鉴相器的输入IN端相连，形成反馈通路。
进一步地，所述多级同步分频器采用PS计数器结构，具体包括：双模分频器、P计数器、S计数器和第一时钟同步模块SYN1、第二时钟同步模块SYN2、第三时钟同步模块SYN3。所述压控振荡器的输出端同时连接所述双模分频器的输入端a、第一时钟同步模块SYN1的同步端c和第三时钟同步模块SYN3的同步端c。所述双模分频器的输出端b连接第一时钟同步模块SYN1的输入端a，所述第一时钟同步模块SYN1的输出端b同时连接S计数器的输入端a、P计数器的输入端a和第二时钟同步模块SYN2的同步端c；所述S计数器的输出端b连接所述双模分频器的模式切换端c，所述P计数器的输出端b连接第二时钟同步模块SYN2的输入端a，所述第二时钟同步模块SYN2的输出端b与第三时钟同步模块SYN3的输入端a连接，所述第三时钟同步模块SYN3的输出端b连接所述鉴频鉴相器的输入IN端。压控振荡器的输出信号CLK_VCO还同时连接到同步模块SYN1的同步端c和同步模块SYN3的同步端c。
进一步地，所述压控振荡器的输出时钟信号CLK_VCO输入多级同步分频器，经双模分频器分频得到的时钟信号CLK1，输入第一时钟同步模块SYN1；所述第一时钟同步模块SYN1将CLK_VCO作为触发时钟获得输出信号CLK2，输入P计数器和S计数器；所述S计数器输出MC信号，所述P计数器输出脉冲信号CLK3；所述脉冲信号CLK3输入第二时钟同步模块SYN2，获得输出信号CLK4；所述脉冲信号CLK4输入第三时钟同步模块SYN3并获得CLK_DIV；所述CLK_DIV输入鉴频鉴相器(PFD)中，与参考时钟CLK_REF进行相位比较。
进一步地，所述第一时钟同步模块SYN1的延时Tsyn1、第二时钟同步模块SYN2的延时Tsyn2与压控振荡器的延时TCLK_VCO之间满足：Tsyn1+Tsyn2<TCLK_VCO。
本发明的有益效果在于，本发明所提出的一种零延时锁相环频率综合器，其使用了多级同步分频器结构，对压控振荡器的输出时钟信号进行逐级同步，并最终将分频器的相对延时控制在了Tsyn3，即一个门延时。同时，其在不增加额外可调延时单元的情况下，最大程度的实现了参考时钟信号与压控振荡器输出时钟信号的相位一致性，从而得到了零延时时钟信号。与传统技术相比，本发明电路更为简单，不需要在锁相环电路中加入多个可调延时单元用以实现输出信号与参考信号的相位对齐，降低了电路复杂度和系统功耗，进而得以应用于诸如通信、相控阵等更加广泛的领域当中。
附图说明
图1为传统锁相环电路的示意图；
图2为传统零延时锁相环频率综合器的示意图；
图3为传统零延时锁相环频率综合器各点的信号示意图；
图4为发明改进的零延时锁相环频率综合器的示意图；
图5为本发明改进的零延时锁相环频率综合器各点的信号示意图；
图6为本发明应用于多通路收发机系统。
具体实施方式
对于理想的分频器而言，其输入和输出时钟信号是天然相位一致的。但在实际的电路中，任何模块都会有一定的延时。而本发明则是将这一延时的影响降至最低。为了使本发明的目的和效果将变得更加明白，以下结合附图，对本发明进行进一步详细说明。应当理解，此处所描述的仅仅用以解释本发明，并不用于限定本发明。
图1-3为传统的零延时锁相环频率综合器电路，它通过可调延时单元来实现输出时钟信号与输入参考时钟信号的相位一致性，以此达成零延时的目的。
图4为发明改进的零延时锁相环频率综合器的示意图。与传统锁相环系统不同的是，在该锁相环频率综合器中加入了第一时钟同步模块SYN1、第二时钟同步模块SYN2、第三时钟同步模块SYN3。该锁相环频率综合器具体包括：鉴频鉴相器、电荷泵、环路滤波器、压控振荡器和多级同步分频器。所述鉴频鉴相器的输出OP端连接电荷泵的输入IP端，所述鉴频鉴相器的输出ON端连接电荷泵的输入IN端，所述电荷泵的输出端连接所述环路滤波器的输入端，所述环路滤波器的输出端连接所述压控振荡器的输入端，所述压控振荡器的输出端与所述多级同步分频器的输入端相连，所述多级同步分频器的输出端与所述鉴频鉴相器的输入IN端相连，形成反馈通路。
其中，所述多级同步分频器采用PS计数器结构，具体包括：双模分频器、P计数器、S计数器和第一时钟同步模块SYN1、第二时钟同步模块SYN2、第三时钟同步模块SYN3。所述压控振荡器的输出端同时连接所述双模分频器的输入端a、第一时钟同步模块SYN1的同步端c和第三时钟同步模块SYN3的同步端c。所述双模分频器的输出端b连接第一时钟同步模块SYN1的输入端a，所述第一时钟同步模块SYN1的输出端b同时连接S计数器的输入端a、P计数器的输入端a和第二时钟同步模块SYN2的同步端c；所述S计数器的输出端b连接所述双模分频器的模式切换端c，所述P计数器的输出端b连接第二时钟同步模块SYN2的输入端a，所述第二时钟同步模块SYN2的输出端b与第三时钟同步模块SYN3的输入端a连接,所述第三时钟同步模块SYN3的输出端b连接所述鉴频鉴相器的输入端IN。压控振荡器的输出信号CLK_VCO还同时连接到同步模块SYN1的同步端c和同步模块SYN3的同步端c。
首先，所述压控振荡器的输出时钟信号CLK_VCO输入多级同步分频器，经双模分频器分频，并在其中积累了大量非线性延时。输入到双模分频器的CLK_VCO经分频，得到的时钟信号CLK1，输入第一时钟同步模块SYN1；所述第一时钟同步模块SYN1将CLK_VCO作为触发时钟获得输出信号CLK2，使输出信号CLK2与CLK_VCO是边沿对齐。CLK2再输入P计数器和S计数器；所述S计数器计数到设定值时，输出MC信号到双模分频器，改变其分频比；所述P计数器继续计数，直到P计数器计数到设定值，输出脉冲信号CLK3；所述脉冲信号CLK3输入第二时钟同步模块SYN2，获得输出信号CLK4，第二时钟同步模块SYN2使用CLK1作为触发时钟，使得其输出信号CLK4与第一时钟同步模块SYN1的输出信号CLK1是边沿对齐的。所述脉冲信号CLK4输入第三时钟同步模块SYN3并获得CLK_DIV，第三时钟同步模块SYN3再一次使用CLK_VCO作为触发时钟，使得其输出信号CLK_DIV与CLK_VCO是边沿对齐的，即两者是相位一致的。所述CLK_DIV输入鉴频鉴相器(PFD)中，与参考时钟CLK_REF进行相位比较，在环路锁定后两者达成相位一致，而与CLK_DIV相位一致的CLK_VCO自然也与CLK_REF相位一致，从而实现零延时的锁相环频率综合器。
图5为本发明所述的基于多级同步的零延时锁相环频率综合器的信号示意图。CLK_VCO经过双模分频器后会积累一定的延时Tdelay1，使得CLK1与CLK_VCO产生一定的相位差。而在第一时钟同步模块SYN1中，经过CLK_VCO的同步，CLK2重新与CLK_VCO对齐，不过由于电路的非理想性，第一时钟同步模块SYN1本身也是同样存在延时的，即Tsyn1，但显然Tsyn1<<Tdelay1。而当CLK2再输入到P计数器，又会在其中积累大量的延时Tdelay2，因此CLK3与CLK_VCO之间的延时为Tsyn1+Tdelay2。而在第二时钟同步模块SYN2中经过CLK2的同步，使得到的CLK4与CLK2对齐，因此CLK4与CLK_VCO之间的延时降为Tsyn1+Tsyn2。同理，由于Tsyn2<<Tdelay2，因此Tsyn1+Tsyn2<<Tsyn1+Tdelay2的。而CLK4再经由第三时钟同步模块SYN3中CLK_VCO的同步，使得CLK4与CLK_VCO对齐，最终得到的CLK_DIV与CLK_VCO之间只有Tsyn3的延时，而CLK_DIV与CLK_REF又经由环路对齐，最终使得CLK_VCO与CLK_REF相位对齐。
同时，需要注意的是，所述第一时钟同步模块SYN1的延时Tsyn1、第二时钟同步模块SYN2的延时Tsyn2与压控振荡器的延时TCLK_VCO之间应满足：Tsyn1+Tsyn2<TCLK_VCO。即当CLK_VCO对CLK3进行采样时，两者之间的延时应小于TCLK_VCO。否则，由于电路的非理想因素，会出现CLK_VCO对CLK3的采样发生在其上升沿处，从而导致采样失败，进而使得分频器出现逻辑混乱。
图6为本发明所述的基于多级同步的零延时锁相环频率综合器应用于多通路收发机系统。由同一信号源提供一个参考时钟信号CLK_REF到TXPLL和RXPLL，而由于零延时锁相环的特性，其输出时钟CLK_TX和CLK_RX都是和参考时钟信号CLK_REF相位对齐的，而TXPLL以及RXPLL到各个TX、RX模块则通过信号通路的调整来实现到达各个模块时钟信号的相位一致性，并最终实现所有TX和RX通路的同步。

Claims (4)

1.一种基于多级同步的零延时锁相环频率综合器，其特征在于，所述零延时锁相环频率综合器包括：鉴频鉴相器、电荷泵、环路滤波器、压控振荡器和多级同步分频器。所述鉴频鉴相器的输出OP端连接电荷泵的输入IP端，所述鉴频鉴相器的输出ON端连接电荷泵的输入IN端，所述电荷泵的输出端连接所述环路滤波器的输入端，所述环路滤波器的输出端连接所述压控振荡器的输入端，所述压控振荡器的输出端与所述多级同步分频器的输入端相连，所述多级同步分频器的输出端与所述鉴频鉴相器的输入IN端相连，形成反馈通路。
2.如权利要求1所述零延时锁相环频率综合器，其特征在于，所述多级同步分频器采用PS计数器结构，具体包括：双模分频器、P计数器、S计数器和第一时钟同步模块SYN1、第二时钟同步模块SYN2、第三时钟同步模块SYN3。所述压控振荡器的输出端同时连接所述双模分频器的输入端a、第一时钟同步模块SYN1的同步端c和第三时钟同步模块SYN3的同步端c。所述双模分频器的输出端b连接第一时钟同步模块SYN1的输入端a，所述第一时钟同步模块SYN1的输出端b同时连接S计数器的输入端a、P计数器的输入端a和第二时钟同步模块SYN2的同步端c；所述S计数器的输出端b连接所述双模分频器的模式切换端c，所述P计数器的输出端b连接第二时钟同步模块SYN2的输入端a，所述第二时钟同步模块SYN2的输出端b与第三时钟同步模块SYN3的输入端a连接，所述第三时钟同步模块SYN3的输出端b连接所述鉴频鉴相器的输入IN端。压控振荡器的输出信号CLK_VCO还同时连接到同步模块SYN1的同步端c和同步模块SYN3的同步端c。
3.如权利要求1所述零延时锁相环频率综合器，其特征在于，所述压控振荡器的输出时钟信号CLK_VCO输入多级同步分频器，经双模分频器分频得到的时钟信号CLK1，输入第一时钟同步模块SYN1；所述第一时钟同步模块SYN1将CLK_VCO作为触发时钟获得输出信号CLK2，输入P计数器和S计数器；所述S计数器输出MC信号，所述P计数器输出脉冲信号CLK3；所述脉冲信号CLK3输入第二时钟同步模块SYN2，获得输出信号CLK4；所述脉冲信号CLK4输入第三时钟同步模块SYN3并获得CLK_DIV；所述CLK_DIV输入鉴频鉴相器(PFD)中，与参考时钟CLK_REF进行相位比较。
4.如权利要求3所述零延时锁相环频率综合器，其特征在于，所述第一时钟同步模块SYN1的延时Tsyn1、第二时钟同步模块SYN2的延时Tsyn2与压控振荡器的延时TCLK_VCO之间满足：Tsyn1+Tsyn2<TCLK_VCO。
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