CN110571261B - Metal oxide field effect transistor and manufacturing method thereof - Google Patents

Metal oxide field effect transistor and manufacturing method thereof Download PDF

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CN110571261B
CN110571261B CN201910806653.1A CN201910806653A CN110571261B CN 110571261 B CN110571261 B CN 110571261B CN 201910806653 A CN201910806653 A CN 201910806653A CN 110571261 B CN110571261 B CN 110571261B
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electrode
layer
metal oxide
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forming
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CN110571261A (en
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刘宇
刘明
胡媛
张凯平
张培文
路程
赵盛杰
刘琦
吕杭炳
谢常青
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Institute of Microelectronics of CAS
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

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Abstract

The invention relates to the technical field of semiconductors, in particular to a manufacturing method of a metal oxide field effect transistor, which comprises the following steps: an insulating layer, a first electrode, a sacrificial layer, a second electrode and a structural layer are sequentially formed on the substrate from bottom to top, and the thickness of the sacrificial layer is determined according to the preset length of the channel; etching the edge of the sacrificial layer to form a transverse groove at the edge of the sacrificial layer and between the first electrode and the second electrode; forming a metal oxide semiconductor layer in the transverse groove, so that the transverse groove forms a channel of the metal oxide; and forming a gate electrode in the region where the channel is located, controlling the length of the channel by the thickness of the sacrificial layer, and effectively controlling the operating voltage of the field effect transistor by controlling the length of the channel.

Description

Metal oxide field effect transistor and manufacturing method thereof
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to a metal oxide field effect transistor and a manufacturing method thereof.
Background
A Field Effect Transistor (FET) mainly includes a Junction Field-Effect Transistor (JFET) and a metal-oxide semiconductor Field-Effect Transistor (MOS-FET), and belongs to a voltage-controlled semiconductor device.
The existing planar MOS field effect transistor is limited by factors such as process conditions, equipment and the like, is limited by a planar area in the manufacturing process of forming a small-size channel, and has a relatively complex process, while the vertical channel field effect transistor can realize the formation of the small-size channel, so the vertical channel field effect transistor is one of the most potential novel devices following the planar MOS field effect transistor.
The existing vertical channel field effect transistor forms a channel by etching a silicon platform and ion implantation, but the junction depth of the implantation is difficult to control, so the size of the formed channel is difficult to control, and the control of a specific voltage cannot be realized.
Therefore, how to effectively control the size of a channel formed in a field effect transistor is a technical problem to be solved.
Disclosure of Invention
In view of the above problems, the present invention has been made to provide a metal oxide field effect transistor and a method of fabricating the same that overcome or at least partially solve the above problems.
In one aspect, an embodiment of the present invention provides a method for manufacturing a metal oxide field effect transistor, including:
sequentially forming an insulating layer, a first electrode, a sacrificial layer, a second electrode and a structural layer on a substrate from bottom to top, wherein the thickness of the sacrificial layer is determined according to the preset length of a channel;
etching the edge of the sacrificial layer so as to form a transverse groove at the edge of the sacrificial layer and between the first electrode and the second electrode;
forming a metal oxide semiconductor layer in the transverse groove, so that the transverse groove forms a channel of metal oxide;
and forming a gate electrode on the region where the channel is located.
Further, the forming a gate electrode in the region where the channel is located specifically includes:
forming a gate dielectric layer on a first projection area corresponding to a preset area above the structural layer;
and forming a gate electrode on the gate dielectric layer so that the gate electrode is positioned on the region where the channel is positioned.
Further, the first projection area corresponding to the preset area completely covers an overlapping area of the second projection area of the second electrode and the third projection area of the first electrode.
Further, an insulating layer, a first electrode, a sacrificial layer, a second electrode, and a structural layer are sequentially formed on the substrate from bottom to top, wherein the thickness of the sacrificial layer satisfies a preset thickness, and the method specifically includes:
forming an insulating layer on the substrate;
forming a groove on the insulating layer, and filling the groove with the first electrode;
forming the sacrificial layer on a plane formed by the first electrode and the insulating layer, wherein the thickness of the sacrificial layer is determined according to the preset length of the channel;
forming a second electrode on the sacrificial layer;
and forming a structural layer on the second electrode.
Further, after an insulating layer, a first electrode, a sacrificial layer, a second electrode, and a structural layer are sequentially formed on the substrate from bottom to top, the method further includes:
and patterning the sacrificial layer, the second electrode and the structural layer to form a patterned structure.
Further, the forming a metal oxide semiconductor layer in the lateral trench so that the lateral trench forms a channel of a metal oxide specifically includes:
forming a metal oxide semiconductor layer over the structural layer, the edge of the second electrode, within the lateral trench, over the first electrode, and over the insulating layer such that the lateral trench forms a channel of metal oxide;
and removing the metal oxide semiconductor layer in other areas except the transverse grooves, and reserving the metal oxide semiconductor layer in the transverse grooves.
Further, the sacrificial layer specifically adopts any one of the following:
SiO x layer and SiN x And (3) a layer.
On the other hand, an embodiment of the present invention further provides a metal oxide field effect transistor, including: the device comprises a substrate, an insulating layer, a first electrode, a sacrificial layer, a second electrode, a structural layer, a gate dielectric layer and a gate electrode from bottom to top, wherein the thickness of the sacrificial layer is determined according to the preset length of a channel;
forming a channel of metal oxide at an edge of the sacrificial layer and between the first electrode and the second electrode;
the gate electrode is located on a region where the channel is located.
Further, still include: a gate dielectric layer;
the gate dielectric layer is located in a first projection area corresponding to a preset area above the structural layer.
Further, the first projection area corresponding to the preset area completely covers an overlapping area of the second projection area of the second electrode and the third projection area of the first electrode.
One or more technical solutions in the embodiments of the present invention have at least the following technical effects or advantages:
the invention provides a manufacturing method of a metal oxide field effect transistor, which comprises the following steps: the method comprises the steps of sequentially forming an insulating layer, a first electrode, a sacrificial layer and a second electrode structure layer on a substrate from bottom to top, wherein the thickness of the sacrificial layer is determined according to the preset length of a channel, etching the edge of the sacrificial layer to enable the edge of the sacrificial layer and a transverse groove to be formed between the first electrode and the second electrode, forming a metal oxide semiconductor layer in the transverse groove to enable the transverse groove to form a metal oxide channel, forming a gate electrode in the area where the channel is located, forming the thickness of the sacrificial layer according to the preset length of the channel to enable the channel with the preset size to be obtained when the metal oxide channel is formed, and further controlling the size of the channel to effectively control the operating voltage of the metal oxide field effect transistor.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:
FIG. 1 is a flow chart illustrating steps of a method for fabricating a MOSFET in an embodiment of the present invention;
fig. 2 to 8 are schematic structural diagrams illustrating steps of forming the mosfet in the embodiment of the present invention;
fig. 9 shows a schematic top view structure of the mosfet in the embodiment of the present invention.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
Example one
An embodiment of the present invention provides a method for manufacturing a metal oxide field effect transistor, as shown in fig. 1, including: s101, sequentially forming an insulating layer, a first electrode, a sacrificial layer, a second electrode and a structural layer on a substrate from bottom to top, wherein the thickness of the sacrificial layer is determined according to the preset length of a channel; s102, etching the edge of the sacrificial layer to form two transverse grooves between the edge of the sacrificial layer and the first electrode and the second electrode; s103, forming a metal oxide semiconductor layer in the transverse groove, so that the transverse groove forms a channel of metal oxide; and S104, forming a gate electrode on the area where the channel is located.
The steps for forming the mosfet will be described in detail by way of illustration.
In S101, the method specifically includes: an insulating layer 902 is formed over a substrate 901 as shown in fig. 2. In a specific embodiment, an insulating layer 902 is deposited on a substrate 901, where the insulating layer 902 specifically employs any one of the following: siO 2 2 Layer and HfO x And (3) a layer.
Next, as shown in fig. 3, a trench 903 is formed in the insulating layer 902, and the trench 903 is filled with a first electrode 904.
Specifically, a trench 903 is formed in the insulating layer 902 by etching, and a first electrode 904 is filled in the trench 903, where the first electrode can serve as a source or a drain.
Then, as shown in fig. 4, a sacrificial layer 905 is formed on the plane formed by the first electrode 904 and the insulating layer 902 such that the thickness of the sacrificial layer 905 is determined according to a predetermined length of the channel.
The sacrificial layer 905 specifically adopts any one of the following: siO 2 X Layer and SiN X A layer.
Specifically, a sacrificial layer 905 is deposited on the plane formed by the first electrode 904 and the insulating layer 902, the predetermined thickness being determined according to the predetermined length of the channel.
Next, a second electrode 906 is formed on the sacrificial layer 905, then a structural layer 907 is formed on the second electrode 906, and the sacrificial layer 905, the second electrode 906 and the structural layer 907 are patterned to form a patterned structure, specifically the structure shown in fig. 4. S101 is completed.
The electrode materials of the first electrode 904 and the second electrode 906 are any one of the following:
au, pt, mo, ITO, and TiN.
If the first electrode 904 serves as a source, the second electrode 906 serves as a drain; if the first electrode 904 serves as a drain, the second electrode 906 serves as a source.
The structural layer 907 is specificallyIs HfO X Layer, siN X A layer or a SiC layer.
S102 is performed, the edge of the sacrificial layer 905 is etched, so that a lateral trench a is formed at the edge of the sacrificial layer 905 and between the first electrode 904 and the second electrode 906, as shown in fig. 5. The length of the formed lateral trench a is equal to the thickness of the sacrificial layer 905, and particularly, various isotropic etching methods may be used to etch the sacrificial layer 905.
Next, S103 is performed, and a metal oxide semiconductor layer 908 is formed in the lateral trench a, so that the lateral trench forms a channel B of the metal oxide.
Specifically, a metal oxide semiconductor layer 908 is formed over the structural layer 907, the edge of the second electrode 906, in the lateral trench a, over the first electrode 904 and over the insulating layer 902, so that the lateral trench a forms a channel B of metal oxide, and then the metal oxide semiconductor layer 908 in the other region except the lateral trench a is removed, leaving the metal oxide semiconductor layer 908 in the lateral trench a, as shown in fig. 6.
The metal oxide semiconductor layer 908 specifically employs any one of: an IGZO layer, a SnO layer and a ZnO layer.
Wherein the metal oxide semiconductor layer 908 is removed in other regions except the lateral trench a. Specifically, the metal oxide semiconductor layer 908 above the structural layer 907, the edge of the second electrode 906, above the first electrode 904 and above the insulating layer 906 is removed, leaving the metal oxide semiconductor layer 908 in the lateral trenches a, i.e. leaving the channels B of the metal oxide formed, as shown in fig. 7. When the excess metal oxide semiconductor layer 908 is removed, various anisotropic etching methods may be used for etching.
Finally, S104 is performed to form a gate electrode 909 in a region where the channel B is located.
Specifically, a gate dielectric layer 910 is formed on the first projection region corresponding to the predetermined region above the structural layer, so that the gate dielectric layer 910 covers the structural layer 907, the partial region of the first electrode 904, the edge and top of the second electrode 906, and the edge of the channel B. The first projection area corresponding to the preset area completely covers an overlapping area of the second projection area corresponding to the second electrode 906 and the third projection area corresponding to the first electrode 904. The gate dielectric layer 910 is used to isolate the gate electrode 909 from other electrodes.
Next, a gate electrode 909 is formed on the gate dielectric layer 910 so that the gate electrode 909 is located on the region where the channel B is located, as shown in fig. 8.
The gate electrode specifically adopts any one of the following:
au, pt, mo, ITO, and TiN.
Example two
Based on the same inventive concept, an embodiment of the present invention provides a metal oxide field effect transistor, as shown in fig. 8 and 9, including: the transistor comprises a substrate 901, an insulating layer 902, a first electrode 904, a sacrificial layer 905, a second electrode 906, a structural layer 907, a gate dielectric layer 910 and a gate electrode 909 from bottom to top, wherein the thickness of the sacrificial layer 905 is determined according to the preset length of a channel;
forming a channel B of a metal oxide semiconductor layer at an edge of the sacrificial layer 905 and between the first electrode 904 and the second electrode 906;
the gate electrode 909 is located on a region where the channel B is located.
In a preferred embodiment, the method further comprises: a gate dielectric layer 910;
the gate dielectric layer 910 is located in a first projection area corresponding to a preset area above the structural layer 907.
In a preferred embodiment, the first projection area corresponding to the preset area completely covers an overlapping area of the second projection area of the second electrode 906 and the third projection area of the first electrode 904.
In a specific embodiment, the sacrificial layer 905, the second electrode 906, and the structural layer 907 are patterned.
In a preferred embodiment, the first electrode 904 is disposed in a trench formed in the insulating layer 902, and the first electrode 904 and the insulating layer 902 form a plane.
In a preferred embodiment, the insulating layer 902 is embodied asAny one of the following is used: siO 2 2 Layer, hfO X Layer and AlO X And (3) a layer.
In a preferred embodiment, the electrode material of the first electrode 904 and the second electrode 906 is any one of the following:
au, pt, mo, ITO, and TiN.
In a preferred embodiment, the sacrificial layer 905 specifically adopts any one of the following: siO 2 X Layer and SiN X And (3) a layer.
In a preferred embodiment, the metal oxide semiconductor layer 908 is any one of: an IGZO layer, a SnO layer and a ZnO layer.
In a preferred embodiment, the structural layer 907 specifically adopts any one of the following: hfO X Layer, siN X A layer and a SiC layer.
One or more technical solutions in the embodiments of the present invention at least have the following technical effects or advantages:
the invention provides a manufacturing method of a metal oxide field effect transistor, which comprises the following steps: the method comprises the steps of sequentially forming an insulating layer, a first electrode, a sacrificial layer and a second electrode structure layer on a substrate from bottom to top, wherein the thickness of the sacrificial layer is determined according to the preset length of a channel, etching the edge of the sacrificial layer to enable the edge of the sacrificial layer and a transverse groove to be formed between the first electrode and the second electrode, forming a metal oxide semiconductor layer in the transverse groove to enable the transverse groove to form a metal oxide channel, forming a gate electrode in the area where the channel is located, forming the thickness of the sacrificial layer according to the preset length of the channel to obtain the channel with the preset size when the metal oxide channel is formed, and further controlling the size of the channel to effectively control the operating voltage of the metal oxide field effect transistor.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims (10)

1. A method for manufacturing a metal oxide field effect transistor is characterized by comprising the following steps:
sequentially forming an insulating layer, a first electrode, a sacrificial layer, a second electrode and a structural layer on a substrate from bottom to top, wherein the thickness of the sacrificial layer is determined according to the preset length of a channel;
etching the edge of the sacrificial layer so as to form a transverse groove at the edge of the sacrificial layer and between the first electrode and the second electrode;
forming a metal oxide semiconductor layer in the transverse groove, so that the transverse groove forms a channel of metal oxide;
and forming a gate electrode on the region where the channel is located.
2. The method of claim 1, wherein forming a gate electrode over a region in which the channel is located comprises:
forming a gate dielectric layer on a first projection area corresponding to a preset area above the structural layer;
and forming a gate electrode on the gate dielectric layer so that the gate electrode is positioned on the region where the channel is positioned.
3. The method of claim 2, wherein the first projection area corresponding to the predetermined area completely covers an overlapping area of the second projection area of the second electrode and the third projection area of the first electrode.
4. The method of claim 1, wherein an insulating layer, a first electrode, a sacrificial layer, a second electrode, and a structural layer are sequentially formed on the substrate from bottom to top, wherein the sacrificial layer has a thickness satisfying a predetermined thickness, and specifically comprises:
forming an insulating layer on the substrate;
forming a groove on the insulating layer, and filling the groove with the first electrode;
forming the sacrificial layer on a plane formed by the first electrode and the insulating layer, wherein the thickness of the sacrificial layer is determined according to the preset length of the channel;
forming a second electrode on the sacrificial layer;
and forming a structural layer on the second electrode.
5. The method as claimed in claim 1, wherein after the insulating layer, the first electrode, the sacrificial layer, the second electrode, and the structural layer are sequentially formed on the substrate from bottom to top, the method further comprises:
and patterning the sacrificial layer, the second electrode and the structural layer to form a patterned structure.
6. The method of claim 1, wherein forming a metal oxide semiconductor layer in the lateral trench such that the lateral trench forms a channel of metal oxide comprises:
forming a metal oxide semiconductor layer over the structural layer, the edge of the second electrode, within the lateral trench, over the first electrode, and over the insulating layer such that the lateral trench forms a channel of metal oxide;
and removing the metal oxide semiconductor layer in other areas except the transverse grooves, and reserving the metal oxide semiconductor layer in the transverse grooves.
7. The method of claim 1, wherein the sacrificial layer is specifically any one of:
SiO x layer and SiN x And (3) a layer.
8. A metal oxide field effect transistor fabricated by the method of any one of claims 1 to 7, comprising: the device comprises a substrate, an insulating layer, a first electrode, a sacrificial layer, a second electrode, a structural layer, a gate dielectric layer and a gate electrode from bottom to top, wherein the thickness of the sacrificial layer is determined according to the preset length of a channel;
forming a channel of metal oxide at an edge of the sacrificial layer and between the first electrode and the second electrode;
the gate electrode is located on a region where the channel is located.
9. The metal oxide field effect transistor of claim 8, further comprising: a gate dielectric layer;
the gate dielectric layer is located in a first projection area corresponding to a preset area above the structural layer.
10. The mosfet of claim 9, wherein the first projected area corresponding to the predetermined area completely covers an overlapping area of the second projected area of the second electrode and the third projected area of the first electrode.
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CN1992344A (en) * 2005-12-29 2007-07-04 东部电子股份有限公司 Transistor of semiconductor device and method for fabricating the same
CN103855214A (en) * 2012-12-05 2014-06-11 元太科技工业股份有限公司 Semiconductor element and manufacturing method thereof

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