CN214411205U

CN214411205U - Planar power device

Info

Publication number: CN214411205U
Application number: CN202120056790.0U
Authority: CN
Inventors: 夏志平; 叶青青; 陈洪雷; 赵志涌; 朱晓彤
Original assignee: Hangzhou Silan Integrated Circuit Co Ltd
Current assignee: Hangzhou Silan Integrated Circuit Co Ltd
Priority date: 2021-01-11
Filing date: 2021-01-11
Publication date: 2021-10-15
Anticipated expiration: 2031-01-11

Abstract

The utility model discloses a plane power device. The planar power device according to the present invention comprises a substrate; a drift region located on the substrate; etching the blocking region, which is positioned on the drift region; and the contact field plate is positioned on the etching barrier region and penetrates through part of the etching barrier region, wherein the etching barrier region comprises a first dielectric layer, a second dielectric layer, a third dielectric layer and a fourth dielectric layer which are sequentially stacked from bottom to top. According to the utility model discloses plane power device, the sculpture that has accurate contact field plate hole stops the terminal point and the sculpture of contact field plate below blocks district thickness, can improve plane power device's breakdown voltage effectively, reduces on-resistance.

Description

Planar power device

Technical Field

The utility model relates to a semiconductor device technical field, in particular to plane power device.

Background

Power devices can be classified into power IC (integrated circuit) devices and power discrete devices, which include power MOSFETs (metal-oxide semiconductor field effect transistors), DMOS (double-diffused metal-oxide semiconductor field effect transistors), high-power transistors, IGBTs (insulated gate bipolar transistors), and the like.

The DMOS includes a vertical double-diffused metal oxide semiconductor field effect transistor (VDMOS) and a lateral double-diffused metal oxide semiconductor field effect transistor (LDMOS), and taking an LDMOS device as an example, a conventional LDMOS device adopts a metal field plate structure and is far from the surface of a Drift region (Drift) of the LDMOS device. With the development of integrated circuit technology, a contact field plate is added between metal and a transistor, so that the on-resistance can be reduced, and the breakdown voltage of an LDMOS device can be improved. For the LDMOS device, how to accurately control the etching stop end point of the contact field plate hole and the thickness of the dielectric layer below the contact field plate is a problem to be solved.

It is therefore desirable to have a new planar power device that overcomes the above problems.

SUMMERY OF THE UTILITY MODEL

In view of the above, an object of the present invention is to provide a planar power device, which has the etching stop end point of the accurate contact field plate hole and the etching stop zone thickness below the contact field plate, thereby effectively improving the breakdown voltage of the planar power device and reducing the on-resistance.

According to an aspect of the present invention, there is provided a planar power device, comprising a substrate; a drift region located on the substrate; etching the blocking region, which is positioned on the drift region; and the contact field plate is positioned on the etching barrier region and penetrates through part of the etching barrier region, wherein the etching barrier region comprises a first dielectric layer, a second dielectric layer, a third dielectric layer and a fourth dielectric layer which are sequentially stacked from bottom to top.

Preferably, in the first dielectric layer, the second dielectric layer, the third dielectric layer and the fourth dielectric layer, materials of two adjacent dielectric layers are different.

Preferably, the first dielectric layer is a silicon dioxide layer; the second dielectric layer comprises one selected from a silicon nitride layer, a silicon carbide layer, a silicon oxycarbide layer and a silicon oxynitride layer; the third dielectric layer is a silicon dioxide layer; the fourth dielectric layer includes one selected from a silicon nitride layer, a silicon carbide layer, a silicon oxycarbide layer, and a silicon oxynitride layer.

Preferably, the etch stop region further comprises at least one dielectric layer stacked on the fourth dielectric layer.

Preferably, the bottom of the contact field plate is in contact with one of the first dielectric layer, the second dielectric layer, the third dielectric layer and the fourth dielectric layer in the etching blocking region.

Preferably, the thickness of the first dielectric layer is 400-1000 angstroms.

Preferably, the thickness of the second dielectric layer is 50-1000 angstroms.

Preferably, the thickness of the third dielectric layer is 50-1000 angstroms.

Preferably, the thickness of the fourth dielectric layer is 200-800 angstroms.

Preferably, the thickness of the etch stop region directly under the contact field plate is greater than 600 angstroms.

Preferably, the planar power device further comprises an epitaxial layer disposed on the substrate; the active region is arranged on the epitaxial layer, and the drift region is arranged on the active region; a source electrode disposed in the drift region; a drain disposed in the drift region; the grid electrode is arranged on the drift region and is positioned between the source electrode and the drain electrode; a well disposed in the active region, the drain being in the well; the side wall is arranged on the side surface of the grid; the self-aligned metal oxide is respectively arranged on the source electrode, the drain electrode and the grid electrode, wherein the etching blocking region is arranged on the drift region and the grid electrode; the etching blocking region transversely extends to a position between the grid and the drain from the upper part of the grid and covers the leading-out region of the source, the leading-out region of the drain and the region outside the leading-out region of the grid.

Preferably, the planar power device further includes a first isolation layer disposed on the etching blocking region, and the first isolation layer covers a portion of the source, the drain, the gate, and the etching blocking region; the thickness of the first isolation layer is 200-1000 angstroms; the first isolation layer and the fourth dielectric layer are made of different materials.

Preferably, the planar power device further comprises a second isolation layer disposed on the first isolation layer, wherein the second isolation layer has a thickness greater than 6000 angstroms.

Preferably, the planar power device further includes metal leads respectively disposed on the source electrode and the drain electrode, wherein the metal leads penetrate through the second isolation layer and the first isolation layer; the contact field plate penetrates through the second isolation layer, the first isolation layer and a part of the etching blocking region.

Preferably, the metal lead has a smaller diameter than the contact field plate.

Preferably, the planar power device comprises one selected from laterally diffused metal oxide semiconductor and high voltage metal oxide semiconductor field effect transistor.

According to the utility model discloses plane power device adopts the etching of the contact field board of four layers framework to block district (the etching stops the dielectric layer), has the etching that can accurate sculpture and blocks the district, and the etching that can accurately control the contact field board hole stops the terminal point to improve plane power device's breakdown voltage effectively, reduced on-resistance.

According to the utility model discloses planar power device, the contact field plate sculpture that has four layers of framework stops the district (the sculpture stops the dielectric layer), the structure that first to fourth dielectric layer is constituteed promptly, makes contact field plate sculpture technology possess the accurate process window that stops of capacity.

According to the utility model discloses plane power device, the sculpture blocks that the district has the multilayer dielectric layer, through the regulation and control to the sculpture selectivity between the adjacent dielectric layer, and the sculpture that can accurate control contact field plate hole stops terminal point and the sculpture of contact field plate below and blocks the thickness in district.

According to the utility model discloses plane power device adopts four layers and above contact field board sculpture to block district (sculpture stops the dielectric layer), through adjusting the sculpture selectivity between the different dielectric layers for the sculpture stops that the terminal point and the sculpture of contact field board below block the stable controllable of thickness in district, thereby improves plane power device's breakdown voltage, reduces on-resistance.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

fig. 1 shows a schematic structural diagram of a planar power device according to a first embodiment of the present invention;

fig. 2 shows a method flowchart of a method for manufacturing a planar power device according to a second embodiment of the present invention;

fig. 3-5 show schematic structural diagrams in the manufacturing process of the planar power device according to the second embodiment of the present invention.

Detailed Description

Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by the same or similar reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. Moreover, certain well-known elements may not be shown in the figures.

The following detailed description of the embodiments of the present invention is provided with reference to the accompanying drawings and examples. Numerous specific details of the invention, such as structure, materials, dimensions, processing techniques and techniques of components, are set forth in the following description in order to provide a more thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.

It will be understood that when a layer, region or layer is referred to as being "on" or "over" another layer, region or layer in describing the structure of the component, it can be directly on the other layer, region or layer or intervening layers or regions may also be present. Also, if the component is turned over, one layer or region may be "under" or "beneath" another layer or region.

According to an aspect of the utility model, a plane power device is provided. The planar power device includes a substrate; a drift region on the substrate for expansion of an electric field; etching the blocking region on the drift region; and the contact field plate is positioned on the etching barrier region, penetrates through part of the etching barrier region and is used for voltage division. The etching blocking area comprises a first dielectric layer, a second dielectric layer, a third dielectric layer and a fourth dielectric layer which are sequentially stacked from bottom to top.

Fig. 1 shows a schematic structural diagram of a planar power device according to a first embodiment of the present invention. As shown in fig. 1, a planar power device according to the first embodiment of the present invention includes a substrate 10, a drift region 40, an etch stop region 60, and a contact field plate 70.

In particular, the substrate 10 serves as a substrate of a planar power device. The substrate may be a silicon substrate, a silicon germanium substrate, a group III-V compound substrate, or other semiconductor material substrate known to those skilled in the art.

A drift region 40 is located on the substrate 10 for electric field expansion.

The barrier region 60 is etched over the drift region 40.

A contact field plate 70 is located on the etch barrier region 60, the contact field plate 70 extending through a portion of the etch barrier region 60. The contact field plate 70 is used for voltage division.

The etching barrier region 60 includes a first dielectric layer 61, a second dielectric layer 62, a third dielectric layer 63, and a fourth dielectric layer 64, which are sequentially stacked from bottom to top.

In an alternative embodiment of the present invention, the first dielectric layer 61 is a silicon dioxide layer. The second dielectric layer 62 includes one selected from a silicon nitride layer, a silicon carbide layer, a silicon oxycarbide layer, and a silicon oxynitride layer. The third dielectric layer 63 is a silicon dioxide layer. The fourth dielectric layer 64 includes one selected from a silicon nitride layer, a silicon carbide layer, a silicon oxycarbide layer, and a silicon oxynitride layer. Optionally, the second dielectric layer 62 and the fourth dielectric layer 64 are the same material. Optionally, the second dielectric layer 62 and the fourth dielectric layer 64 are of different materials.

In an alternative embodiment of the present invention, the materials of two adjacent dielectric layers of the first dielectric layer 61, the second dielectric layer 62, the third dielectric layer 63 and the fourth dielectric layer 64 are different.

The utility model discloses an in the above-mentioned embodiment, through the selection to the dielectric layer material, can realize the regulation and control to the sculpture selectivity between the dielectric layer, the sculpture that can accurate control contact field plate hole stops terminal point and the sculpture of contact field plate below and blocks district thickness, improves the breakdown voltage of plane power device effectively, reduces on-resistance.

In an alternative embodiment of the present invention, the planar power device is a structure having a CNT (carbon nanotube) contact field plate.

In an alternative embodiment of the present invention, the bottom of the contact field plate contacts one of the first, second, third and fourth dielectric layers in the etch stop region. Optionally, the position of the etching stop end point of the contact field plate hole (i.e. the position of the bottom of the contact field plate) is not limited to a certain dielectric layer, and may vary according to the thickness of the first to fourth dielectric layers, and each layer may be an etching stop end point, for example, the bottom of the contact field plate is selected to contact with the first dielectric layer 61, the second dielectric layer 62, the third dielectric layer 63, or the fourth dielectric layer 64 according to actual circumstances. Optionally, the material of the third dielectric layer 63 is different from that of the fourth dielectric layer 64, the contact field plate 70 penetrates through the fourth dielectric layer 64, and the bottom of the contact field plate 70 is in contact with the third dielectric layer 63. Optionally, the contact field plate 70 penetrates through the fourth dielectric layer 64, the third dielectric layer 63 and the second dielectric layer 62, and the bottom of the contact field plate 70 is in contact with the first dielectric layer 61.

In the above embodiments of the present invention, a four-layer etching blocking region 60 (etching stop dielectric layer), i.e. a structure of a first dielectric layer-a second dielectric layer-a third dielectric layer-a fourth dielectric layer, is provided, so that the contact field plate etching process has a process window for precisely stopping.

In an alternative embodiment of the present invention, a first isolation layer for isolation is disposed on the etching blocking region 60. Optionally, a first isolation layer is disposed on the fourth dielectric layer 64. The etch selectivity of the first isolation layer is similar to that of the fourth dielectric layer 64. Optionally, the first isolation layer and the fourth dielectric layer 64 are different in material.

In an optional embodiment of the present invention, a second isolation Layer (e.g., an Inter Layer Dielectric, ILD) for electrical isolation is disposed on the etching blocking region 60. Optionally, a second isolation layer is disposed on the first isolation layer.

In an alternative embodiment of the present invention, a source and a drain are disposed in the drift region 40. The planar power device further includes a metal lead. The metal leads are respectively arranged on the source electrode and the drain electrode. The metal lead penetrates through the second isolation layer and the first isolation layer and is electrically connected with the source electrode and the drain electrode respectively. The contact field plate penetrates through the second isolation layer, the first isolation layer and a part of the etching blocking region. Optionally, the metal lead has a smaller diameter than the contact field plate.

Fig. 2 shows a method flowchart of a method for manufacturing a planar power device according to a second embodiment of the present invention. According to the present invention, the planar power device of the second embodiment is, for example, an LDMOS (laterally-diffused Metal-Oxide Semiconductor) device, a high-voltage MOS (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET, Metal-Oxide Semiconductor Field-Effect Transistor) device, or other MOS device having a contact Field plate structure. As shown in fig. 2, the method for manufacturing the planar power device includes:

in step S201, a substrate is provided;

a substrate is provided. The substrate may be a silicon substrate, a silicon germanium substrate, a group III-V compound substrate, or other semiconductor material substrate known to those skilled in the art.

In step S202, an epitaxial layer, an active region, and a drift region are sequentially formed on a substrate;

an epitaxial layer, an active region and a drift region are sequentially formed on a substrate. For example, forming an epitaxial layer on a substrate; forming an active region on the epitaxial layer and the substrate; a drift region is formed over the active region.

In step S203, a source, a drain and a gate are respectively provided, and a well is injected;

a source and a drain are respectively disposed in the drift region and are implanted into the well. A gate, such as a polysilicon gate, is disposed over the drift region. Optionally, a well is implanted in the active region. Optionally, a side wall is disposed on a side surface of the gate.

In an alternative embodiment of the present invention, after the epitaxial layer, the active region and the drift region are sequentially formed on the substrate, the above structures are collectively referred to as a substrate. A source and a drain are fabricated in the substrate, and a well is implanted in the substrate. And manufacturing a grid electrode on the substrate.

In step S204, an etching blocking region is disposed on the drift region and the gate;

and an etching blocking region is arranged on the drift region and the grid electrode. Optionally, the etching blocking region includes first to fourth dielectric layers stacked in sequence from bottom to top. And depositing a first dielectric layer for forming an etching stop end point of the contact field plate hole on the drift region and the grid electrode, wherein the first dielectric layer is used as a fourth stop end point of the contact field plate etching, and the thickness of the first dielectric layer is 400-1000 angstroms, for example. And depositing a second dielectric layer for forming an etching stop endpoint of the contact field plate hole on the first dielectric layer to serve as a third stop endpoint of the contact field plate etching, wherein the thickness of the second dielectric layer is 50-1000 angstroms, for example. And depositing a third dielectric layer for forming an etching stop endpoint of the contact field plate hole on the second dielectric layer, wherein the third dielectric layer is used as a second stop endpoint of the contact field plate etching, and the thickness of the third dielectric layer is 50-1000 angstroms, for example. And depositing a fourth dielectric layer for forming an etching stop end point of the contact field plate hole on the third dielectric layer, wherein the fourth dielectric layer is used as the first stop end point of the contact field plate etching, and the thickness of the fourth dielectric layer is 200-800 angstroms, for example. Optionally, the materials of two adjacent dielectric layers are different. It should be noted that, according to the utility model discloses the sculpture stops the district and is not limited to the scheme of four layers of dielectric layers, and the sculpture stops the district and can also include at least one dielectric layer of piling up on the fourth dielectric layer, for example can also continue to set up fifth dielectric layer, sixth dielectric layer etc. on the fourth dielectric layer, the utility model discloses do not limit to this.

In step S205, exposing a region where a salicide needs to be deposited by photolithography and etching, and depositing the salicide;

and photoetching and etching to expose the area needing to be deposited with the self-aligned metal silicide, and depositing the self-aligned metal silicide. Specifically, the etching blocking regions (the first to fourth dielectric layers) are subjected to photoetching and etching to expose at least one part of the source electrode, the drain electrode and the grid electrode (a region where self-aligned metal silicide needs to be deposited), and the self-aligned metal silicide is deposited on the source electrode, the drain electrode and the grid electrode.

In step S206, a first isolation layer is provided;

and arranging a first isolation layer on the etching blocking region, the source electrode, the drain electrode, the grid electrode and the drift region to isolate the existing structure and the structure deposited subsequently. Optionally, a dielectric layer with a thickness of 200-. Preferably, the etching selection ratio of the first isolation layer to the fourth dielectric layer is close, and the etching stop end point of the contact field plate hole is not affected.

In step S207, a second spacer is provided on the first spacer;

a second isolation layer (electrical isolation layer) is provided on the first isolation layer for electrical isolation of the existing structure from the subsequently deposited structure (metal). Optionally, a dielectric layer with a thickness greater than 6000 a is covered on the first isolation layer to serve as an electrical isolation layer (second isolation layer) between the existing structure and the metal deposited subsequently.

In step S208, metal interconnect material is etched, and implanted to form metal leads and contact field plates.

And forming metal lead wires and contact field plates with different diameters by photoetching, etching and injecting metal interconnection materials. Optionally, the metal leads and the contact field plate are of different diameters. Preferably, the contact field plate diameter is greater than the diameter of the metal lead. Optionally, the thickness of the etch barrier region directly under the contact field plate is greater than 600 angstroms, i.e. the thickness of the etch barrier region under the contact field plate is at least 600 angstroms.

In an optional embodiment of the present invention, the second isolation layer and the first isolation layer are subjected to photolithography and etching to form a contact hole, and the contact hole is filled with a metal interconnection material to form a metal lead. Optionally, one end of the contact hole is located on the surface of the source electrode and/or the drain electrode.

In an optional embodiment of the present invention, the second isolation layer, the first isolation layer and the etching blocking region are subjected to photolithography and etching to form a contact field plate hole, and the contact field plate hole is filled with a metal interconnection material to form a contact field plate. Optionally, the etching blocking region includes first to fourth dielectric layers, and the fourth dielectric layer is etched, so that the etching stop end point of the contact field plate hole stops on the third dielectric layer. Optionally, the etching blocking region includes first to fourth dielectric layers, and the second to fourth dielectric layers are etched, so that the etching stop end point of the contact field plate hole stops on the first dielectric layer.

The following describes the planar power device in detail with reference to the manufacturing method of the planar power device and the schematic structural diagrams in the manufacturing process shown in fig. 3 to 5. The planar power device shown in fig. 5 is, for example, a structure of a final product (planar power device).

Performing steps S201-S205, providing a substrate 10; sequentially forming an epitaxial layer 20, an active region 30 and a drift region 40 on a substrate 10; a source 51, a drain 52 and a gate 53 are provided, respectively, and a well 54 is implanted; an etch stop region 60 is provided over the drift region 40 and the gate 53; and photoetching and etching are carried out to expose the area needing to be deposited with the self-aligned metal silicide, and the self-aligned metal silicide 56 is deposited. The planar power device obtained through the above steps is shown in fig. 3.

As shown in fig. 3, the planar power device according to the embodiment of the present invention includes a substrate 10, an epitaxial layer 20, an active region 30, a drift region 40, a source 51, a drain 52, a gate 53, a well 54, a sidewall 55, a self-aligned metal oxide 56, a gate dielectric layer 57, and an etch stop region 60. The etching blocking region 60 includes a first dielectric layer 61, a second dielectric layer 62, a third dielectric layer 63, and a fourth dielectric layer 64.

An epitaxial layer 20 is disposed on the substrate 10. An active region 30 is disposed on the epitaxial layer 20. And a drift region 40 disposed on the active region 30.

And a source 51 disposed in the drift region 40. And a drain 52 disposed in the drift region 40. And a gate 53 disposed on the drift region 40 and between the source 51 and the drain 52. And a well 54 disposed (implanted) in the active region 30, and the drain 51 is implanted in the well 54.

And a gate dielectric layer 57 located below the gate 53 (between the gate 53 and the drift region 40) and on the sidewall.

And a sidewall spacer 55 disposed at a side of the gate electrode 53. For example, outside of gate dielectric layer 57 on the sidewalls of gate 53.

Self-aligned metal oxide 56 is disposed on the source 51, drain 52 and gate 53, respectively. The salicide 56 is used to reduce the series resistance.

The barrier region 60 is etched and disposed over the drift region 40 and the gate 53. The etching stopper region 60 extends from above the gate electrode 53 to between the gate electrode 53 and the drain electrode 52, and covers the region other than the lead-out region of the source electrode 51, the lead-out region of the drain electrode 52, and the lead-out region of the gate electrode 53. The etching barrier region 60 includes a first dielectric layer 61, a second dielectric layer 62, a third dielectric layer 63, and a fourth dielectric layer 64, which are sequentially stacked from bottom to top. Optionally, the thickness of the first dielectric layer 61 is 400-1000 angstroms. The second dielectric layer 62 is 50-1000 angstroms thick. The thickness of the third dielectric layer 63 is 50-1000 angstroms. The thickness of the fourth dielectric layer 64 is 200-800 angstroms.

In an optional embodiment of the present invention, the materials of two adjacent dielectric layers of the first to fourth dielectric layers are different. In an alternative embodiment of the present invention, the first dielectric layer 61 is a silicon dioxide layer. The second dielectric layer 62 includes one selected from a silicon nitride layer, a silicon carbide layer, a silicon oxycarbide layer, and a silicon oxynitride layer. The third dielectric layer 63 is a silicon dioxide layer. The fourth dielectric layer 64 includes one selected from a silicon nitride layer, a silicon carbide layer, a silicon oxycarbide layer, and a silicon oxynitride layer. Optionally, the growth manner of silicon dioxide in the first dielectric layer 61 and/or the third dielectric layer 63 may be LPTEOS, PETEOS, or the like.

In an alternative embodiment of the present invention, the bottom of the contact field plate contacts one of the first, second, third and fourth dielectric layers in the etch stop region. Optionally, the position of the etching stop end point of the contact field plate hole (i.e. the position of the bottom of the contact field plate) is not limited to a certain dielectric layer, and may vary according to the thickness of the first to fourth dielectric layers, and each layer may be an etching stop end point, for example, the bottom of the contact field plate is selected to contact with the first dielectric layer 61, the second dielectric layer 62, the third dielectric layer 63, or the fourth dielectric layer 64 according to actual circumstances. Optionally, the first dielectric layer may serve as a fourth stop endpoint for etching the contact field plate hole, the second dielectric layer may serve as a third stop endpoint for etching the contact field plate hole, the third dielectric layer may serve as a second stop endpoint for etching the contact field plate hole, and the fourth dielectric layer may serve as a first stop endpoint for etching the contact field plate hole. Preferably, as shown in fig. 5, the contact field plate 70 extends through the fourth dielectric layer 64, the third dielectric layer 63 and a portion of the second dielectric layer 62, and the bottom of the contact field plate 70 contacts the second dielectric layer 62. Due to the fact that the materials of the adjacent dielectric layers are different, the etching rates of the etching gas to the dielectric layers are different, and the etching stop end point of the contact field plate hole can be easily stopped at the second dielectric layer 62 by adjusting the thickness of each dielectric layer. Similarly, the thicknesses and materials of the first to fourth dielectric layers may be adjusted so that the etching stop endpoint of the contact field plate hole stops at the first dielectric layer 61, the second dielectric layer 62, the third dielectric layer 63, or the fourth dielectric layer 64.

The utility model discloses an in the above-mentioned embodiment, adopt the structure of contact field board, it is nearer apart from the drift region surface of plane power device (LDMOS), and regard as the etching of contact field board with four layers and above dielectric layer and block the district, through adjusting the etching selectivity between the adjacent dielectric layer, the etching of accurate regulation and control contact field plate hole stops terminal point and the etching of contact field board below and blocks district thickness, reduces the breakdown voltage of plane power device (LDMOS).

Performing steps S206 and S207, disposing the first isolation layer 81; a second spacer layer 82 is provided. The planar power device obtained through the above steps is shown in fig. 4.

As shown in fig. 4, the planar power device according to the embodiment of the present invention further includes a first isolation layer 81 and a second isolation layer 82.

Specifically, the first isolation layer 81 is disposed on the etch barrier region 60. Optionally, a first isolation layer 81 is disposed on the source 51, drain 52, gate 53 and etch stop region 60. Optionally, the thickness of the first isolation layer 81 is 200-1000 angstroms. Optionally, the first isolation layer 81 and the fourth dielectric layer 64 are made of different materials and have similar etching selectivity.

And a second spacer 82 disposed on the first spacer 81. Optionally, the second barrier layer 82 is provided in two layers. Optionally, the second isolation layer 82 has a thickness greater than 6000 angstroms and serves as an electrical isolation layer with the upper metal layer. Optionally, the top of the second isolation layer 82 is planarized by Chemical Mechanical Polishing (CMP).

In the above embodiment of the present invention, the second isolation layer 82 is disposed in two layers, for example, a lower isolation layer and an upper isolation layer located above the lower isolation layer. The lower isolation layer contains boron and phosphorus, and the upper isolation layer can avoid direct contact between the lower isolation layer and the upper metal layer.

Step S208 is performed to form the metal wire 90 and the contact field plate 70 by photolithography, etching, and injecting metal interconnect material. The planar power device obtained through the above steps is shown in fig. 5.

As shown in fig. 5, the planar power device according to the embodiment of the present invention further includes a metal lead 90 and a contact field plate 70.

And metal wires 90 disposed on the source and drain

electrodes

51 and 52, respectively. Alternatively, the metal wire 90 penetrates through the second isolation layer 82 and the first isolation layer 81 to be connected to the source electrode 51 or the drain electrode 52.

A contact field plate 70 is disposed on the etch stop region 60. Optionally, the contact field plate 70 extends through the second isolation layer 82, the first isolation layer 81 and the partial etch stop region 60. The bottom of the contact field plate 70 contacts the etch stop region 60, and in particular, the second dielectric layer 62. Optionally, the bottom of the contact field plate 70 may also be in contact with the first dielectric layer 61 or the second dielectric layer 62 or the third dielectric layer 63 or the fourth dielectric layer 64.

The utility model discloses an in the above-mentioned embodiment, fourth dielectric layer 64 and basement are stamped first isolation layer 81, first isolation layer 81 can avoid with follow-up sedimentary structure (second isolation layer 82) direct contact as the basement isolation layer, and the etching selectivity of first isolation layer 81 and fourth dielectric layer 64 is close, can not influence the etching stop terminal point that contacts the field plate hole.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

In accordance with the embodiments of the present invention as set forth above, these embodiments are not exhaustive and do not limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, to thereby enable others skilled in the art to best utilize the invention and its various embodiments with various modifications as are suited to the particular use contemplated. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A planar power device, comprising:

a substrate;

a drift region located on the substrate;

etching the blocking region, which is positioned on the drift region; and

a contact field plate on the etch barrier region, the contact field plate extending through a portion of the etch barrier region,

the etching blocking area comprises a first dielectric layer, a second dielectric layer, a third dielectric layer and a fourth dielectric layer which are sequentially stacked from bottom to top.

2. The planar power device as claimed in claim 1, wherein the materials of two adjacent dielectric layers of the first dielectric layer, the second dielectric layer, the third dielectric layer and the fourth dielectric layer are different.

3. The planar power device as claimed in claim 1, wherein the first dielectric layer is a silicon dioxide layer;

the second dielectric layer comprises one selected from a silicon nitride layer, a silicon carbide layer, a silicon oxycarbide layer and a silicon oxynitride layer;

the third dielectric layer is a silicon dioxide layer;

the fourth dielectric layer includes one selected from a silicon nitride layer, a silicon carbide layer, a silicon oxycarbide layer, and a silicon oxynitride layer.

4. The planar power device as claimed in claim 1, wherein the etch stop region further comprises:

at least one dielectric layer stacked on the fourth dielectric layer.

5. The planar power device of claim 1, wherein a bottom of the contact field plate contacts one of the first, second, third and fourth dielectric layers in the etch stop region.

6. The planar power device as claimed in claim 1, wherein the thickness of the first dielectric layer is 400-1000 angstroms.

7. The planar power device as claimed in claim 1, wherein the thickness of the second dielectric layer is 50-1000 angstroms.

8. The planar power device as claimed in claim 1, wherein the thickness of the third dielectric layer is 50-1000 angstroms.

9. The planar power device as claimed in claim 1, wherein the thickness of the fourth dielectric layer is 200-800 angstroms.

10. The planar power device of claim 1, wherein the thickness of the etch stop region directly below the contact field plate is greater than 600 angstroms.

11. The planar power device as claimed in claim 1, further comprising:

an epitaxial layer disposed on the substrate;

the active region is arranged on the epitaxial layer, and the drift region is arranged on the active region;

a source electrode disposed in the drift region;

a drain disposed in the drift region;

the grid electrode is arranged on the drift region and is positioned between the source electrode and the drain electrode;

a well disposed in the active region, the drain being in the well;

the side wall is arranged on the side surface of the grid; and

self-aligned metal oxides respectively disposed on the source electrode, the drain electrode and the gate electrode,

the etching blocking region is arranged on the drift region and the grid electrode;

the etching blocking region transversely extends to a position between the grid and the drain from the upper part of the grid and covers the leading-out region of the source, the leading-out region of the drain and the region outside the leading-out region of the grid.

12. The planar power device as claimed in claim 11, further comprising:

the first isolating layer is arranged on the etching blocking region and covers a part of the source electrode, the drain electrode, the grid electrode and the etching blocking region;

the thickness of the first isolation layer is 200-1000 angstroms;

the first isolation layer and the fourth dielectric layer are made of different materials.

13. The planar power device as claimed in claim 12, further comprising:

a second isolation layer disposed on the first isolation layer,

wherein the thickness of the second isolation layer is greater than 6000 angstroms.

14. The planar power device as claimed in claim 13, further comprising:

metal leads respectively disposed on the source electrode and the drain electrode,

wherein the metal lead penetrates the second isolation layer and the first isolation layer;

the contact field plate penetrates through the second isolation layer, the first isolation layer and a part of the etching blocking region.

15. The planar power device of claim 14, wherein the metal lead wire has a smaller diameter than the contact field plate.

16. The planar power device as claimed in claim 1, wherein the planar power device comprises one selected from laterally diffused metal oxide semiconductor, high voltage metal oxide semiconductor field effect transistor.