CN110534442B - Forming method of packaging structure - Google Patents
Forming method of packaging structure Download PDFInfo
- Publication number
- CN110534442B CN110534442B CN201910681470.1A CN201910681470A CN110534442B CN 110534442 B CN110534442 B CN 110534442B CN 201910681470 A CN201910681470 A CN 201910681470A CN 110534442 B CN110534442 B CN 110534442B
- Authority
- CN
- China
- Prior art keywords
- shielding layer
- layer
- forming
- semiconductor chip
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 96
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 25
- 239000004065 semiconductor Substances 0.000 claims abstract description 154
- 239000000758 substrate Substances 0.000 claims abstract description 80
- 238000011049 filling Methods 0.000 claims abstract description 13
- 229920003023 plastic Polymers 0.000 claims abstract description 7
- 239000004033 plastic Substances 0.000 claims abstract description 7
- 239000011248 coating agent Substances 0.000 claims abstract description 6
- 238000000576 coating method Methods 0.000 claims abstract description 6
- 230000008569 process Effects 0.000 claims description 71
- 238000002955 isolation Methods 0.000 claims description 52
- 239000000463 material Substances 0.000 claims description 52
- 229910052751 metal Inorganic materials 0.000 claims description 40
- 239000002184 metal Substances 0.000 claims description 40
- 230000005684 electric field Effects 0.000 claims description 32
- 229910000679 solder Inorganic materials 0.000 claims description 31
- 230000002093 peripheral effect Effects 0.000 claims description 19
- 239000007769 metal material Substances 0.000 claims description 16
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 15
- 238000005530 etching Methods 0.000 claims description 15
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 14
- 229910052802 copper Inorganic materials 0.000 claims description 14
- 239000010949 copper Substances 0.000 claims description 14
- 238000007650 screen-printing Methods 0.000 claims description 13
- 229910052782 aluminium Inorganic materials 0.000 claims description 12
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 12
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 12
- 229910052721 tungsten Inorganic materials 0.000 claims description 12
- 239000010937 tungsten Substances 0.000 claims description 12
- 238000004544 sputter deposition Methods 0.000 claims description 11
- 229910045601 alloy Inorganic materials 0.000 claims description 7
- 239000000956 alloy Substances 0.000 claims description 7
- 238000009713 electroplating Methods 0.000 claims description 7
- 238000005520 cutting process Methods 0.000 claims description 6
- 229910019236 CoFeB Inorganic materials 0.000 claims description 5
- 229910000531 Co alloy Inorganic materials 0.000 claims description 3
- 229910000640 Fe alloy Inorganic materials 0.000 claims description 3
- 229910000990 Ni alloy Inorganic materials 0.000 claims description 3
- 230000000694 effects Effects 0.000 abstract description 18
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 449
- 238000004519 manufacturing process Methods 0.000 description 17
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 8
- 229920005989 resin Polymers 0.000 description 7
- 239000011347 resin Substances 0.000 description 7
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 5
- 229910052709 silver Inorganic materials 0.000 description 5
- 239000004332 silver Substances 0.000 description 5
- 239000011135 tin Substances 0.000 description 5
- 229910052718 tin Inorganic materials 0.000 description 5
- 230000008878 coupling Effects 0.000 description 4
- 238000010168 coupling process Methods 0.000 description 4
- 238000005859 coupling reaction Methods 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- 229910052759 nickel Inorganic materials 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 4
- -1 polybutylene terephthalate Polymers 0.000 description 4
- NTSDHVIXFWZYSM-UHFFFAOYSA-N [Ag].[Sb].[Sn] Chemical compound [Ag].[Sb].[Sn] NTSDHVIXFWZYSM-UHFFFAOYSA-N 0.000 description 3
- QCEUXSAXTBNJGO-UHFFFAOYSA-N [Ag].[Sn] Chemical compound [Ag].[Sn] QCEUXSAXTBNJGO-UHFFFAOYSA-N 0.000 description 3
- PQIJHIWFHSVPMH-UHFFFAOYSA-N [Cu].[Ag].[Sn] Chemical compound [Cu].[Ag].[Sn] PQIJHIWFHSVPMH-UHFFFAOYSA-N 0.000 description 3
- PSMFTUMUGZHOOU-UHFFFAOYSA-N [In].[Sn].[Bi] Chemical compound [In].[Sn].[Bi] PSMFTUMUGZHOOU-UHFFFAOYSA-N 0.000 description 3
- HRPKYGWRFPOASX-UHFFFAOYSA-N [Zn].[Ag].[Sn] Chemical compound [Zn].[Ag].[Sn] HRPKYGWRFPOASX-UHFFFAOYSA-N 0.000 description 3
- WGCXSIWGFOQDEG-UHFFFAOYSA-N [Zn].[Sn].[In] Chemical compound [Zn].[Sn].[In] WGCXSIWGFOQDEG-UHFFFAOYSA-N 0.000 description 3
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical compound [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- JVPLOXQKFGYFMN-UHFFFAOYSA-N gold tin Chemical compound [Sn].[Au] JVPLOXQKFGYFMN-UHFFFAOYSA-N 0.000 description 3
- 238000001746 injection moulding Methods 0.000 description 3
- LQBJWKCYZGMFEV-UHFFFAOYSA-N lead tin Chemical compound [Sn].[Pb] LQBJWKCYZGMFEV-UHFFFAOYSA-N 0.000 description 3
- 238000000465 moulding Methods 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 239000002356 single layer Substances 0.000 description 3
- 229910000969 tin-silver-copper Inorganic materials 0.000 description 3
- 238000001721 transfer moulding Methods 0.000 description 3
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 238000000277 atomic layer chemical vapour deposition Methods 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 239000011651 chromium Substances 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 238000005034 decoration Methods 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 238000001914 filtration Methods 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 229910052742 iron Inorganic materials 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 229920002577 polybenzoxazole Polymers 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 239000009719 polyimide resin Substances 0.000 description 2
- 229920000098 polyolefin Polymers 0.000 description 2
- 229920002635 polyurethane Polymers 0.000 description 2
- 239000004814 polyurethane Substances 0.000 description 2
- 238000011160 research Methods 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 239000004952 Polyamide Substances 0.000 description 1
- 239000004695 Polyether sulfone Substances 0.000 description 1
- 239000004698 Polyethylene Substances 0.000 description 1
- 239000004743 Polypropylene Substances 0.000 description 1
- 239000004372 Polyvinyl alcohol Substances 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 238000010923 batch production Methods 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000001680 brushing effect Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000005038 ethylene vinyl acetate Substances 0.000 description 1
- 230000009969 flowable effect Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000015654 memory Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 239000013307 optical fiber Substances 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229920001200 poly(ethylene-vinyl acetate) Polymers 0.000 description 1
- 229920002647 polyamide Polymers 0.000 description 1
- 229920001707 polybutylene terephthalate Polymers 0.000 description 1
- 229920000515 polycarbonate Polymers 0.000 description 1
- 239000004417 polycarbonate Substances 0.000 description 1
- 229920006393 polyether sulfone Polymers 0.000 description 1
- 229920000573 polyethylene Polymers 0.000 description 1
- 229920000139 polyethylene terephthalate Polymers 0.000 description 1
- 239000005020 polyethylene terephthalate Substances 0.000 description 1
- 229920001155 polypropylene Polymers 0.000 description 1
- 229920002451 polyvinyl alcohol Polymers 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000001228 spectrum Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Health & Medical Sciences (AREA)
- Electromagnetism (AREA)
- Toxicology (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
Abstract
A method for forming a packaging structure comprises flip-mounting a plurality of semiconductor chips on the front surface of a substrate; forming a first shielding layer for coating the surface of the non-functional surface and the side wall of the semiconductor chip and the surface of the side surface of the bottom filling layer, wherein the surface of the first shielding layer is in an ellipsoid shape; forming a second shielding layer on the first shielding layer; forming a plastic packaging layer on the second shielding layer and the substrate between the semiconductor chips; and forming an external contact structure connected with the output port on the back surface of the substrate. The first shielding layer that has the ellipsoid surface of formation can be even and complete cover the non-functional face and the lateral wall surface of semiconductor chip to when the ellipsoid surface of first shielding layer formed the second shielding layer, the problem that thickness is inhomogeneous and the edge covers not well can not appear in the second shielding layer, thereby makes the whole shielding layer that first shielding layer and the second shielding layer that forms both constitute complete, has improved shielded effect.
Description
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a forming method of a packaging structure with electromagnetic shielding.
Background
The rapid development of a new generation of electronic products pushes the integrated circuit package to develop in the direction of high density, high frequency, miniaturization and high integration, and the high frequency chip often generates strong electromagnetic waves to cause undesirable interference or noise inside and outside the package and the chip; in addition, the density of electronic components is increasing, and the distance of transmission lines is becoming closer, so that the problem of electromagnetic interference from inside and outside the integrated circuit package is becoming more serious, and the quality, the service life and the like of the integrated circuit are also being reduced.
In electronic devices and products, electromagnetic Interference (Electromagnetic Interference) energy is transmitted by conductive coupling and radiative coupling. In order to meet the requirement of electromagnetic compatibility, a filtering technology is required to be adopted for conductive coupling, namely an EMI filtering device is adopted for inhibiting; the radiation coupling is suppressed by shielding. The importance of the electromagnetic wave is more prominent under the conditions that the electromagnetic environment of equipment and a system is increasingly deteriorated due to the factors that the electromagnetic spectrum is increasingly dense, the electromagnetic power density in a unit volume is sharply increased, and a large number of high-level devices and low-level devices or equipment are mixed for use.
An existing electromagnetic shielding solution is mainly to provide a magnetic field shielding layer on a semiconductor package structure for shielding electromagnetic interference between chips, but the existing electromagnetic shielding effect still needs to be improved.
Disclosure of Invention
The technical problem to be solved by the invention is how to improve the electromagnetic shielding effect of the existing packaging structure.
The invention provides a forming method of a packaging structure, which comprises the following steps: providing a plurality of semiconductor chips, wherein each semiconductor chip comprises a functional surface and a non-functional surface opposite to the functional surface, the functional surface is provided with a plurality of bonding pads, and metal bumps are formed on the surfaces of the bonding pads;
providing a substrate, wherein the substrate is provided with a plurality of circuit structures, the front surface of the substrate is provided with a plurality of input ports, the back surface of the substrate is provided with a plurality of output ports, and the input ports and the output ports are respectively connected with the corresponding circuit structures;
the semiconductor chips are inversely arranged on the surface of the front surface of the substrate, so that the metal lug on each semiconductor chip is connected with the corresponding input port on the front surface of the substrate;
forming an underfill layer between the functional surface of the semiconductor chip and the front surface of the substrate;
forming a first shielding layer for coating the surface of the non-functional surface and the side wall of the semiconductor chip and the surface of the side surface of the bottom filling layer, wherein the surface of the first shielding layer is in an ellipsoid shape;
forming a second shielding layer on the first shielding layer;
forming a plastic packaging layer on the second shielding layer and the substrate between the semiconductor chips;
and forming an external contact structure connected with the output port on the back surface of the substrate.
Optionally, the first shielding layer is directly formed on the non-functional surface and the sidewall surface of the semiconductor chip through a dispensing process or a screen printing process; the second shielding layer is formed through sputtering, a selective electroplating process, a dispensing process or a screen printing process.
Optionally, the first shielding layer is made of solder or conductive silver paste, and the second shielding layer is made of copper, tungsten, aluminum, solder or conductive silver paste.
Optionally, the method further includes: forming an intermediate material layer on the non-functional surface and the surface of the side wall of the semiconductor chip, wherein the intermediate material layer has an ellipsoidal surface; and forming a first shielding layer on the surface of the intermediate material layer, wherein the first shielding layer also has an ellipsoidal surface.
Optionally, the first shielding layer is a magnetic field shielding layer, and the second shielding layer is an electric field shielding layer; or the first shielding layer is an electric field shielding layer, and the second shielding layer is a magnetic field shielding layer.
Optionally, the electric field shielding layer is made of copper, tungsten, or aluminum; the magnetic field shielding layer is made of CoFeB alloy, coFeTa, niFe, co, coFe, coPt or Ni, co and Fe alloy.
Optionally, the functional surface of the semiconductor chip is further provided with a bottom shielding layer, the bottom shielding layer covers the whole functional surface of the semiconductor chip, the peripheral edge of the bottom shielding layer is flush with the peripheral side walls of the semiconductor chip, the plurality of bonding pads penetrate through the bottom shielding layer, and the bonding pads are isolated from the bottom shielding layer through an isolation layer; when the first shielding layer is formed, the first shielding layer is connected with the peripheral edge of the bottom shielding layer.
Optionally, the forming process of the semiconductor chip with the bottom shielding layer is as follows: providing a wafer, wherein a plurality of semiconductor chips are formed on the wafer, and each semiconductor chip comprises a top dielectric layer and a top interconnection structure positioned in the top dielectric layer; forming an isolation layer on the top dielectric layer; etching the isolation layer, forming a plurality of first openings and second openings surrounding the first openings in the isolation layer, wherein the rest of the isolation layer is only positioned between the first openings and the second openings, and the first openings and the second openings are separated; filling metal materials into the first openings to form a plurality of bonding pads, and filling metal materials into the second openings to form a bottom shielding layer; forming a metal bump on the pad; and after the metal bump is formed, cutting the wafer to form a plurality of discrete semiconductor chips with bottom shielding layers.
Optionally, the pads and the bottom shielding layer are formed by the same process, including the steps of: forming a metal material layer in the first opening and the second opening and on the surface of the isolation layer; and removing the metal material layer higher than the surface of the isolation layer in a planarization manner, forming a bonding pad in the first opening, and forming a bottom shielding layer in the second opening.
Optionally, the external contact structure is a solder ball, or the external contact structure includes a metal pillar and a solder ball located on the metal pillar.
Optionally, the method further includes: a conductive contact structure in the substrate, the conductive contact structure being electrically connected to the first shielding layer.
Optionally, after the forming the external contact structure, the method further includes: and cutting the substrate to form a plurality of separated packaging structures.
Compared with the prior art, the technical scheme of the invention has the following advantages:
the forming method of the packaging structure comprises the steps of inversely installing a plurality of semiconductor chips on the surface of the front side of a substrate, and forming an underfill layer between the functional surface of the semiconductor chips and the surface of the front side of the substrate; forming a first shielding layer for coating the surface of the non-functional surface and the side wall of the semiconductor chip and the surface of the side surface of the bottom filling layer, wherein the surface of the first shielding layer is in an ellipsoid shape; forming a second shielding layer on the first shielding layer; forming a plastic packaging layer on the second shielding layer and the substrate between the semiconductor chips; and forming an external contact structure connected with the output port on the back surface of the substrate. The first shielding layer that has ellipsoid form surface that forms not only first shielding layer itself can be even and complete cover semiconductor chip's non-functional face and lateral wall surface to when the ellipsoid form surface of first shielding layer formed the second shielding layer, the problem that thickness is inhomogeneous and the edge covers is not good can not appear in the second shielding layer, thereby makes the whole shielding layer of first shielding layer and second shielding layer both constitutions of formation complete, has improved shielded effect. And the integrated packaging manufacture of the substrate and the semiconductor chip with the first shielding layer and the second shielding layer is realized.
Further, forming an intermediate material layer on the surface of the non-functional surface and the sidewall of the semiconductor chip, wherein the intermediate material layer has an ellipsoidal surface; and forming a first shielding layer on the surface of the intermediate material layer, wherein the first shielding layer also has an ellipsoidal surface. Through forming the intermediate material layer that has ellipsoid form surface, can form the first shielding layer that has different materials through multiple technology on the intermediate material layer, and the first shielding layer that forms also has the surface of ellipsoid type, and when forming first shielding layer on the surface of the ellipsoid form of intermediate material layer, first shielding layer can not receive the influence of closed angle or precipitous lateral wall, make the uneven and not good problem of edge coverage of thickness can not appear in forming first shielding layer, thereby improved the integrality of shielding layer.
Further, the first shielding layer is a magnetic field shielding layer, and the formed second shielding layer is an electric field shielding layer; or first shielding layer is the electric field shielding layer, and then the second shielding layer that forms is the magnetic field shielding layer, through the first shielding layer and the second shielding layer that form aforementioned structure for first shielding layer and second shielding layer shield to electric field or magnetic field respectively, thereby have improved the shielding effect of shielding layer, and the second shielding layer can cover place that thickness is inhomogeneous and edge cover is not good in the first shielding layer, thereby make the whole shielding layer of both constitutions of first shielding layer and second shielding layer complete, further improved the effect of shielding.
Furthermore, after the external contact structure is formed, the pre-sealing panel is cut to form a plurality of separated packaging structures, so that batch manufacturing of the packaging structures with the first shielding layer and the second shielding layer is realized, and production efficiency is improved.
Furthermore, a bottom shielding layer is further arranged on the functional surface of the semiconductor chip and covers the whole functional surface of the semiconductor chip, the peripheral edge of the bottom shielding layer is flush with the peripheral side wall of the semiconductor chip, a plurality of bonding pads penetrate through the bottom shielding layer, and the bonding pads are isolated from the bottom shielding layer through an isolation layer; when the first shielding layer is formed, the first shielding layer is connected with the peripheral edge of the bottom shielding layer. That is, in this embodiment, not only after the first shielding layer is formed, the second shielding layer is formed on the first shielding layer, so that the second shielding layer can cover the place where the thickness of the first shielding layer is not uniform and the edge of the first shielding layer is not good, so that the whole shielding layer formed by the first shielding layer and the second shielding layer is complete, and the shielding effect is improved.
Further, the forming process of the semiconductor chip with the bottom shielding layer is as follows: providing a wafer, wherein a plurality of semiconductor chips are formed on the wafer, and each semiconductor chip comprises a top dielectric layer and a top interconnection structure positioned in the top dielectric layer; forming an isolation layer on the top dielectric layer; etching the isolation layer, forming a plurality of first openings and second openings surrounding the first openings in the isolation layer, wherein the rest of the isolation layer is only positioned between the first openings and the second openings, and the first openings and the second openings are separated; filling metal materials into the first openings to form a plurality of bonding pads, and filling metal materials into the second openings to form a bottom shielding layer; forming a metal bump on the pad; and after the metal bumps are formed, cutting the wafer to form a plurality of discrete semiconductor chips with bottom shielding layers. The bottom shielding layer can be formed in the process, the process of forming the bottom shielding layer is integrated with the existing semiconductor chip manufacturing process, the manufacturing process of the bottom shielding layer can be synchronously carried out with the manufacturing process of the bonding pad, the manufacturing process is simplified, the process difficulty is reduced, and the efficiency is improved.
Drawings
Fig. 1-12 are schematic structural views illustrating a process of forming a package structure according to a first embodiment of the invention;
fig. 13-18 are schematic structural views illustrating a process of forming a package structure according to a second embodiment of the invention.
Detailed Description
As mentioned in the background, the effect of the conventional electromagnetic shielding still needs to be improved.
Research finds that the existing magnetic field shielding layer is generally formed through a sputtering process, and because the thickness of the semiconductor packaging structure is generally thick and the semiconductor packaging structure is generally rectangular, the semiconductor packaging structure is provided with a plurality of top angles and has steep side walls, when the magnetic field shielding layer covering the semiconductor packaging structure is formed through the sputtering process, the thickness of the formed magnetic field shielding layer is easily uneven, and the edge of the semiconductor packaging structure can have an uncovered condition, so that the shielding effect of the magnetic field shielding layer is difficult to guarantee.
To this end, the invention provides a packaging structure and a forming method thereof, wherein the forming method is that the plurality of semiconductor chips are reversely arranged on the front surface of the substrate, and an underfill layer is formed between the functional surface of the semiconductor chips and the front surface of the substrate; forming a first shielding layer for coating the surface of the non-functional surface and the side wall of the semiconductor chip and the surface of the side surface of the bottom filling layer, wherein the surface of the first shielding layer is in an ellipsoid shape; forming a second shielding layer on the first shielding layer; forming a plastic packaging layer on the second shielding layer and the substrate between the semiconductor chips; and forming an external contact structure connected with the output port on the back surface of the substrate. The first shielding layer that has the ellipsoid surface that forms not only first shielding layer itself can be even and complete cover semiconductor chip's non-functional face and lateral wall surface to when the ellipsoid surface of first shielding layer formed the second shielding layer, the problem that thickness is inhomogeneous and the edge covers is not good can not appear in the second shielding layer, thereby makes the whole shielding layer that first shielding layer and the second shielding layer that forms both complete, has improved shielded effect.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below. In describing the embodiments of the present invention in detail, the drawings are not to be taken as an ordinary scale, and the drawings are for illustrative purposes only and should not be construed as limiting the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
Fig. 1-12 are schematic structural views illustrating a process of forming a package structure according to a first embodiment of the invention.
Referring to fig. 1-4, fig. 2 is a schematic cross-sectional view along a cutting line AB in fig. 1, a plurality of semiconductor chips 101 are provided, each semiconductor chip 101 includes a functional surface and a non-functional surface opposite to the functional surface, the functional surface has a plurality of bonding pads 102, and metal bumps 130 are formed on the bonding pads 102.
An integrated circuit (not shown) is formed in the functional surface of the semiconductor chip 101, the functional surface of the semiconductor chip 101 has a plurality of pads 102, the pads 102 are electrically connected to the integrated circuit in the semiconductor chip 101, and the pads 102 serve as ports for electrically connecting the integrated circuit in the semiconductor chip 101 to the outside.
The functional surface of the semiconductor chip 101 is a surface for forming an integrated circuit, the non-functional surface is a surface opposite to the functional surface, and the peripheral surface between the functional surface and the non-functional surface is a sidewall of the semiconductor chip 101.
The semiconductor chip 101 is formed by a semiconductor integrated manufacturing process, specifically referring to fig. 1 and 2, a wafer 100 is provided, and the wafer 100 includes a plurality of chip regions arranged in rows and columns and scribe line regions located between the chip regions; correspondingly forming a plurality of semiconductor chips 101 in a plurality of chip areas of the wafer 100; forming a plurality of bonding pads 102 on a functional surface of the semiconductor chip 101; referring to fig. 3, a metal bump 130 is formed on the surface of the pad 102, the material of the metal bump 130 is one or more of aluminum, nickel, tin, tungsten, platinum, copper, titanium, chromium, tantalum, gold, and silver, the forming process of the metal bump 130 may be electroplating, sputtering, or a physical vapor deposition process, the purpose of forming the metal bump 130 is to raise the pad 102 for subsequent wiring, and the metal bump 130 also has the functions of protecting the pad and conducting heat; referring to fig. 4, the wafer 100 is diced along dicing streets to form a plurality of discrete semiconductor chips 101.
In one embodiment, the material of the wafer 100 may be single crystal silicon (Si), single crystal germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); or silicon-on-insulator (SOI), germanium-on-insulator (GOI); or may be other materials such as group iii-v compounds such as gallium arsenide.
In an embodiment, the integrated circuit in the semiconductor chip 101 may include several semiconductor devices (such as transistors, memories, diodes and/or transistors, etc.) and an interconnection structure (including metal lines and metal plugs) for connecting the semiconductor devices.
In this embodiment, the semiconductor chip 101 is a semiconductor chip that needs to be electromagnetically shielded.
Referring to fig. 5, a substrate 301 is provided, where the substrate 301 has a plurality of circuit structures therein, the front surface of the substrate 301 has a plurality of input ports, and the back surface of the substrate has a plurality of output ports, where the input ports and the output ports are respectively connected to the corresponding circuit structures; the flip-chip mounting of the plurality of semiconductor chips 101 is performed on the front surface of the substrate such that the metal bumps 130 on each of the semiconductor chips 101 are connected to corresponding input ports on the front surface of the substrate.
The substrate 301 may be a PCB substrate or a circuit carrier. The substrate 301 has a plurality of circuit structures therein, which may be in substantially row and column portions, each of which is connected to an input port and an output port of the drink. In the present embodiment, an integrated package of the substrate 301 and the semiconductor chip having the first shielding layer and the second shielding layer is subsequently implemented.
When the semiconductor chips 101 are flip-chip mounted on the front surface of the substrate, the metal bumps 130 on each semiconductor chip 101 are connected to the corresponding input ports on the substrate 301 through a solder layer.
The solder layer is made of one or more of tin, tin-silver, tin-lead, tin-silver-copper, tin-silver-zinc, tin-bismuth-indium, tin-gold, tin-copper, tin-zinc-indium or tin-silver-antimony.
In one embodiment, the method further comprises: the substrate 301 further has a conductive contact structure (not shown in the figure), which is electrically connected to a first shielding layer formed subsequently, so that the shielding layer can discharge electricity through a part of the redistribution layer 123 or block external electrostatic interference.
Referring to fig. 6, an underfill layer 132 is formed between the functional surface of the semiconductor chip 101 and the front surface of the substrate 301.
The underfill layer 132 covers the sides of the metal bump 130.
The forming process of the underfill layer 132 is an injection molding or transfer molding process, the material of the underfill layer 132 is resin, and the resin may be epoxy resin, polyimide resin, benzocyclobutene resin or polybenzoxazole resin.
Referring to fig. 7, the first shielding layer 103 is formed to cover the non-functional surface and sidewall surface of the semiconductor chip 101 and the side surface of the underfill layer 132, and the surface of the first shielding layer 103 is ellipsoidal.
In this embodiment, the first shielding layer 103 may be formed to cover only the non-functional surface and the sidewall surface (and the side surface of the underfill layer 132) of the semiconductor chip 101.
The first shielding layer 103 is directly formed on the non-functional surface and the sidewall surface of the semiconductor chip 103 through a dispensing process or a screen printing process, the first shielding layer is not formed on the carrier plates on both sides of the semiconductor chip 101, and the formed first shielding layer 103 can uniformly and completely cover the non-functional surface and the sidewall surface of the semiconductor chip. The material of the first shielding layer 103 may be solder or conductive silver paste, and the solder or the conductive silver paste is dispensed on the surface of the non-functional surface and the sidewall of the semiconductor chip 101 by a dispensing process to form the first shielding layer 103 with an ellipsoidal surface. A solder layer is formed on the nonfunctional surface and the sidewall surface of the semiconductor chip 101 by a screen printing process, and a reflow process is performed to form the first shielding layer 103 having an ellipsoidal surface. The solder is one or more of tin, tin-silver, tin-lead, tin-silver-copper, tin-silver-zinc, tin-bismuth-indium, tin-gold, tin-copper, tin-zinc-indium or tin-silver-antimony.
The surface of the first shielding layer 103 is ellipsoidal, which means that the surface of the first shielding layer 103 has no sharp corner, the surface of the first shielding layer 103 is arc-shaped, the formed first shielding layer 103 with the ellipsoidal surface can not only uniformly and completely cover the first shielding layer 103 itself but also cover the non-functional surface and the side wall surface of the semiconductor chip 101, and subsequently, when the ellipsoidal surface of the first shielding layer 103 forms the second shielding layer, the problems of non-uniform thickness and poor edge coverage can not occur in the second shielding layer, so that the whole shielding layers formed by the first shielding layer 103 and the subsequently formed second shielding layer are complete, and the shielding effect is improved.
In other embodiments, an intermediate material layer (not shown) is formed on the surface of the non-functional surface and the sidewall of the semiconductor chip 101, and the intermediate material layer has an ellipsoidal surface; and forming a first shielding layer on the surface of the intermediate material layer, wherein the first shielding layer also has an ellipsoidal surface. By forming the intermediate material layer having an ellipsoidal surface, the first shield layer having a different material can be formed by various processes on the intermediate material layer, and the formed first shield layer also has an ellipsoidal surface.
Specifically, the material of the intermediate material layer may be non-conductive glue, conductive silver glue, flowable resin, or solder, and the material forming the intermediate material layer may be a dispensing process or a screen printing process. The first shielding layer with the ellipsoidal surface formed on the intermediate material layer may be formed by sputtering, a selective plating process, a dispensing process, or a screen printing process, and the corresponding material of the first shielding layer may be copper, tungsten, aluminum, solder, or conductive silver paste, or may be a magnetic field shielding layer and an electric field shielding layer mentioned later.
When the formed first shielding layer also covers the surfaces of the substrates at the two sides of the semiconductor chip, the first shielding layer on the substrates at the two sides of the semiconductor chip can be removed through an etching process after the second shielding layer is formed subsequently. In this embodiment, the first shielding layer 103 is formed as a shielding layer for an electric field and a magnetic field, the first shielding layer 103 is used for shielding the electric field and the magnetic field, the second shielding layer formed subsequently is also used for shielding the electric field and the magnetic field, and the second shielding layer is used for shielding the electric field and the magnetic field.
Research shows that the existing shielding layer needs to shield both an electric field and a magnetic field, while the existing single-layer shielding layer made of a specific material or multiple layers of shielding layers made of the same material or similar materials only have a good shielding effect on the electric field, and the shielding effect on the magnetic field is relatively weak, so that the shielding effect of the shielding layer is influenced. Thus, in other embodiments, the first shielding layer 103 is a magnetic field shielding layer for shielding a magnetic field, and the second shielding layer formed subsequently is an electric field shielding layer for shielding an electric field; or the first shielding layer is an electric field shielding layer, the first shielding layer is used for shielding an electric field, the second shielding layer is a magnetic field shielding layer, the second shielding layer is used for shielding a magnetic field, and the first shielding layer and the second shielding layer are respectively used for shielding the electric field or the magnetic field by forming the first shielding layer and the second shielding layer with the structures, so that the shielding effect of the shielding layers is improved. When the first shielding layer 103 is an electric field shielding layer, the material of the first shielding layer 103 (electric field shielding layer) is copper, tungsten, or aluminum; when the first shielding layer 103 is a magnetic field shielding layer, the material of the first shielding layer 103 (magnetic field shielding layer) is CoFeB alloy, coFeTa, niFe, co, coFe, coPt, or an alloy of Ni, co, and Fe. The first shielding layer 103 may be formed by sputtering, physical vapor deposition, atomic layer deposition, or chemical vapor deposition, or other suitable processes.
Referring to fig. 8, a second shield layer 104 is formed on the first shield layer 103.
In this embodiment, the second shielding layer 104 is formed by sputtering, the material of the second shielding layer 104 is metal such as copper, tungsten, aluminum, etc., the formed second shielding layer 104 is not only located on the surface of the first shielding layer 103 covering the non-functional surface and the sidewall surface of the semiconductor chip 101, but also located on the surface of the carrier board 201 at both sides of the semiconductor chip 101.
In other embodiments, the second shielding layer may be only located on the surface of the first shielding layer 103 covering the non-functional surface and the sidewall surface of the semiconductor chip, and the surface of the second shielding layer is ellipsoidal, and the second shielding layer is formed by a selective plating process, a dispensing process or a screen printing process, so that the formed second shielding layer can better cover the first shielding layer, thereby preventing the second shielding layer from having a place with uneven thickness or poor coverage, further ensuring the integrity of the whole shielding layer formed by the first shielding layer 103 and the second shielding layer, and removing the semiconductor chip without an additional mask or an etching process.
The material of the second shielding layer can be copper, solder or conductive silver adhesive. When the material of the second shielding layer is copper, the second shielding layer is formed through a selective electroplating process, specifically: forming a mask layer (not shown) on the substrate 301, wherein the mask layer has an opening exposing the non-functional surface of the semiconductor chip 101 and the first shielding layer 103 on the sidewall surface; electroplating to form a second shielding layer in the opening by taking the first shielding layer 103 as a conductive layer during electroplating; and removing the mask layer.
The second shielding layer is made of solder or conductive silver adhesive, and can be formed through a dispensing process or a screen printing process. Specifically, when the dispensing process is performed, solder or conductive silver paste is dispensed on the sidewall of the semiconductor chip 101 and the surface of the first shielding layer 103 on the nonfunctional surface. When screen printing is carried out, firstly, a screen with meshes is arranged on the substrate 301, and each semiconductor chip 101 is correspondingly positioned in one mesh in the screen; brushing solder into the mesh, the solder covering the side wall of the semiconductor chip 101 and the surface of the first shielding layer 103 on the non-functional surface; removing the mesh plate; the solder is reflowed to form a second shield layer on the first shield layer 103.
In one embodiment, the solder is one or more of tin, tin-silver, tin-lead, tin-silver-copper, tin-silver-zinc, tin-bismuth-indium, tin-gold, tin-copper, tin-zinc-indium, or tin-silver-antimony.
In other embodiments, the first shielding layer 103 is a magnetic field shielding layer, and the formed second shielding layer 104 is an electric field shielding layer; or the first shielding layer 103 is an electric field shielding layer, the formed second shielding layer 104 is a magnetic field shielding layer, and the first shielding layer and the second shielding layer are formed by the first shielding layer and the second shielding layer with the above structures, so that the first shielding layer and the second shielding layer are respectively shielded against an electric field or a magnetic field, and the shielding effect of the shielding layer is improved. When the second shielding layer 104 is an electric field shielding layer, the material of the second shielding layer 104 (electric field shielding layer) is copper, tungsten, or aluminum; when the second shielding layer 104 is a magnetic field shielding layer, the material of the second shielding layer 104 (magnetic field shielding layer) is CoFeB alloy, coFeTa, niFe, co, coFe, coPt, or an alloy of Ni, co, and Fe. The second shielding layer 104 may be formed by sputtering, physical vapor deposition, atomic layer deposition, or chemical vapor deposition, or other suitable processes.
In an embodiment, after the second shielding layer 104 is formed, the first shielding layer on the substrate between the adjacent semiconductor chips 101 may be removed through an etching process.
Referring to fig. 9, the second shielding material layer 104 on the substrate 301 at both sides of the semiconductor chip 101 is removed.
The second shielding material layer 104 on the substrate 301 at both sides of the semiconductor chip 101 may be removed using a dry etching process, such as a plasma etching process.
Referring to fig. 10, a molding layer 105 is formed on the second shielding layer 104 and on the substrate 301 between the semiconductor chips 101.
The molding compound layer 105 is used to seal and fix the semiconductor chip 101, so as to form a pre-packaged panel in the following.
The plastic sealing layer 105 may be made of one or more of epoxy resin, polyimide resin, benzocyclobutene resin, polybenzoxazole resin, polybutylene terephthalate, polycarbonate, polyethylene terephthalate, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyethersulfone, polyamide, polyurethane, ethylene-vinyl acetate copolymer, or polyvinyl alcohol.
The molding layer 105 may be formed by injection molding (injection molding) or transfer molding (transfer molding) or other suitable processes.
Referring to fig. 11, an external contact structure 124 connected to an output port is formed on the rear surface of the substrate 301.
The external contact structures 124 are solder balls in this embodiment, and in other embodiments, the external contact structures include metal posts and solder balls on the metal posts.
Referring to fig. 11 and 12, after the external contact structure 124 is formed, the pre-cover board 10 is cut to form a plurality of separated package structures 11.
Referring to fig. 12, each package structure 11 includes a substrate 301, the substrate 301 has a circuit structure therein, the front surface of the substrate has a plurality of input ports, the back surface of the substrate has a plurality of output ports, and the input ports and the output ports are respectively connected to the circuit structure;
the semiconductor chip 101 is flip-chip mounted on the front surface of the substrate 301, the semiconductor chip 101 includes a functional surface and a non-functional surface opposite to the functional surface, the functional surface has a plurality of pads 102 thereon, the pads 102 have metal bumps 130 thereon, and the metal bumps 130 on each semiconductor chip 101 are connected to corresponding input ports on the front surface of the substrate;
an underfill layer 132 between the functional surface of the semiconductor chip 101 and the front surface of the substrate 301;
the first shielding layer 103 covers the surface of the non-functional surface and the sidewall of the semiconductor chip 101 and the surface of the side surface of the underfill layer 132, and the surface of the first shielding layer 103 is ellipsoidal;
a second shielding layer 104 on the first shielding layer 103
An external contact structure 124 on the back side of the substrate 301 connected to an output port.
The external contact structure 124 is a solder ball, or the external contact structure includes a metal pillar and a solder ball on the metal pillar.
The invention realizes the batch production of the packaging structure 11 with the first shielding layer 103 and the second shielding layer 104 by the semiconductor integrated manufacturing process, and improves the production efficiency.
Fig. 13-18 are schematic structural views illustrating a process of forming a package structure according to a second embodiment of the invention. The second embodiment differs from the first embodiment in that: the semiconductor chip comprises a semiconductor chip, a plurality of bonding pads and a bottom shielding layer, wherein the functional surface of the semiconductor chip is also provided with the bottom shielding layer, the bottom shielding layer covers the whole functional surface of the semiconductor chip, the peripheral edge of the bottom shielding layer is flush with the peripheral side wall of the semiconductor chip, the bonding pads penetrate through the bottom shielding layer, and the bonding pads are isolated from the bottom shielding layer through an isolation layer; when the first shielding layer is formed, the first shielding layer is connected with the peripheral edge of the bottom shielding layer. That is to say, in this embodiment, the second shielding layer is formed on the first shielding layer after the first shielding layer is formed, so that the second shielding layer can cover the place where the thickness of the first shielding layer is not uniform and the edge of the first shielding layer is not good, so that the whole shielding layer formed by the first shielding layer and the second shielding layer is complete, and the shielding effect is improved.
The forming process of the semiconductor chip with the bottom shielding layer comprises the following steps: referring to fig. 13, a wafer 100 is provided, a plurality of semiconductor chips 101 are formed on the wafer 100, the semiconductor chips 101 include a top dielectric layer 108 and a top interconnection structure 109 located in the top dielectric layer 108, the semiconductor chips further include a plurality of semiconductor devices (such as transistors, etc.) formed on a surface of the wafer (or semiconductor substrate), a plurality of interlayer dielectric layers located between the top dielectric layer 108 and the surface of the wafer 100, each interlayer dielectric layer has a corresponding interconnection structure therein, the interconnection structures in the interlayer dielectric layers can be interconnected with each other from top to bottom or electrically connected to the semiconductor devices, and the top interconnection structure 109 in the top dielectric layer 108 can be electrically connected to the interconnection structure in the interlayer dielectric layer of the adjacent layer; an isolation layer is formed on the top dielectric layer 108.
In this embodiment, the isolation layer is a double-layer stacked structure, and includes a first isolation layer 110 and a second isolation layer 111 located on the first isolation layer 110, where the materials of the first isolation layer 110 and the second isolation layer 111 are different, and the materials of the first isolation layer 110 and the second isolation layer 111 may be one of silicon oxide, silicon nitride, and silicon oxynitride, so as to facilitate accurate control of the depth of the formed second opening, and prevent over-etching of the isolation layer when the second opening is formed, so that the second opening exposes a part of the surface of the top-layer interconnect structure 109 in the top-layer dielectric layer 108, and subsequently cause a short circuit between the top-layer interconnect structures 109 when the bottom shielding layer is formed in the second opening. In other embodiments, the isolation layer may be a single layer structure.
Referring to fig. 14, the isolation layer is etched, a plurality of first openings 112 and a second opening 113 surrounding the plurality of first openings 112 are formed in the isolation layer, and the remaining isolation layer 111 is only located between the first openings 112 and the second openings 112, separating the first openings 112 and the second openings 111.
The first openings 112 are discrete, the first openings 112 penetrate the isolation layer, each first opening 112 may correspondingly expose a portion of the surface of the top-level interconnect structure 109, and a pad is formed by filling metal into the first opening 112.
The second opening 113 surrounds the first opening 112, the second opening 113 and the first opening 112 are separated by the isolation layer 111, and the depth of the second opening 113 is smaller than the thickness of the isolation layer, all the areas of the first opening 112 and the isolation layer 111 surrounding the first opening 112 correspond to the area of the second opening 113, the third opening 113 is communicated, and when a bottom shielding layer is formed in the third opening 113, the bottom shielding layer can cover all the areas of the functional surface of the semiconductor chip 101 except for the pad (formed in the first opening 112) and the isolation layer surrounding the pad, and when the first shielding layer is formed on the surface of the non-functional surface and the surface of the sidewall of the semiconductor chip 101, the first shielding layer is connected with the peripheral edge of the bottom shielding layer, so that the semiconductor chip in the package structure is completely or omnidirectionally covered by the bottom shielding layer and the first shielding layer, and thus an electric field and a magnetic field cannot enter the package structure through the bottom of the package structure to bring electromagnetic interference to the semiconductor chip, thereby achieving electromagnetic shielding of the semiconductor chip and further improving the electromagnetic shielding effect.
In this embodiment, a first etching process is used to etch the second isolation layer 111, and the first isolation layer 110 is used as a stop layer, so as to form a second opening in the second isolation layer 111; then, a second etching process is performed to etch the second isolation layer 111 and the first isolation layer 110, a first opening is formed in the second isolation layer 111 and the first isolation layer 110, and a corresponding mask layer may be formed on the surface of the second isolation layer 110 before the first etching process or the second etching process is performed. It should be noted that the second etching process may also be performed before the first etching process.
In other embodiments, when the isolation layer is a single-layer structure, two etching processes may be performed to form the first opening and the second opening, respectively, and the depth of the formed second opening is controlled by controlling the time of the etching process (the depth of the second opening is smaller than the thickness of the isolation layer).
Referring to fig. 15, a metal material is filled in the first openings to form pads 102, and a metal material is filled in the second openings to form a bottom shielding layer 114; forming a metal bump 130 on the pad 102; referring to fig. 16, after forming the metal bumps 130, the wafer is diced to form a plurality of discrete semiconductor chips 101 having an underlying shielding layer 114.
In one embodiment, the pads 102 and the bottom shield layer 114 are formed by the same process, including the steps of: forming a metal material layer in the first opening and the second opening and on the surface of the isolation layer, wherein the metal material layer is formed by physical vapor deposition, sputtering or electroplating technology, and the metal material layer can be made of one or more of aluminum, nickel, tin, tungsten, platinum, copper, titanium, chromium, tantalum, gold and silver; the metal material layer higher than the surface of the isolation layer is removed by planarization, the pad 102 is formed in the first opening, and the bottom shielding layer 114 is formed in the second opening.
Referring to fig. 17, fig. 17 is a schematic top view structure diagram of the pads 102 and the bottom shielding layer 114 in fig. 16, and referring to fig. 16 and fig. 17 in combination, the functional surface of the semiconductor chip 101 has the bottom shielding layer 114, the bottom shielding layer 114 covers the entire functional surface of the semiconductor chip 101, the peripheral edge of the bottom shielding layer 114 is flush with the peripheral sidewall of the semiconductor chip 101, the pads 102 penetrate through the bottom shielding layer 114, and the pads 102 and the bottom shielding layer 114 are isolated by the isolation layer 111.
In the present application, the process of forming the bottom shielding layer 114 is integrated with the existing semiconductor chip manufacturing process, and the manufacturing process of the bottom shielding layer 114 can be performed synchronously with the manufacturing process of the bonding pad 102, so that the manufacturing process is simplified, the process difficulty is reduced, and the efficiency is improved.
Referring to fig. 18, the semiconductor chip 101 having the bottom shield layer 114 is flip-chip mounted on the substrate 301 such that the metal bump 130 on each semiconductor chip 101 is connected to the corresponding input port on the front surface of the substrate 301; forming an underfill layer 132 between the functional surface of the semiconductor chip 101 and the front surface of the substrate 301; forming a first shielding layer 103 for coating the surface of the non-functional surface and the sidewall of the semiconductor chip 101 and the surface of the side surface of the bottom filling layer 132, wherein the surface of the first shielding layer 103 is ellipsoidal; forming a second shield layer 104 on the first shield layer 103; forming a plastic packaging layer 105 on the second shielding layer 104 and the substrate 301 between the semiconductor chips 101; an external contact structure 124 connected to an output port is formed on the back surface of the substrate 301.
It should be noted that other definitions or descriptions of the same or similar structures in the second embodiment as in the first embodiment are not repeated in the second embodiment, and specific reference is made to the definitions or descriptions of corresponding parts in the first embodiment.
An embodiment of the present invention further provides a package structure, please refer to fig. 11 or fig. 18, including:
the circuit board comprises a substrate 301, wherein the substrate 301 is provided with a plurality of circuit structures, the front surface of the substrate 301 is provided with a plurality of input ports, the back surface of the substrate is provided with a plurality of output ports, and the input ports and the output ports are respectively connected with the corresponding circuit structures;
a plurality of semiconductor chips 101 flip-chip mounted on the front surface of the substrate 301, each semiconductor chip 101 including a functional surface and a non-functional surface opposite to the functional surface, the functional surface having a plurality of pads 102 thereon, the pads 102 having metal bumps 130 thereon, the metal bumps 130 on each semiconductor chip 101 being connected to corresponding input ports on the front surface of the substrate 301;
an underfill layer 132 between the functional surface of the semiconductor chip 101 and the front surface of the substrate 301;
the first shielding layer 103 covers the surface of the non-functional surface and the sidewall of the semiconductor chip 101 and the surface of the side surface of the underfill layer 132, and the surface of the first shielding layer 103 is ellipsoidal;
a second shield layer 104 on the first shield layer 103;
an external contact structure 124 on the back side of the substrate 301 connected to an output port.
In one embodiment of the method of manufacturing the optical fiber,
the first shielding layer 103 is directly formed on the non-functional surface and the sidewall surface of the semiconductor chip through a dispensing process or a screen printing process; the second shielding layer 104 is formed by sputtering, a selective plating process, a dispensing process, or a screen printing process. The first shielding layer 103 is made of solder or conductive silver paste, and the second shielding layer 104 is made of copper, tungsten, aluminum, solder or conductive silver paste.
In one embodiment, the method further comprises: an intermediate material layer on the non-functional surface and the sidewall surface of the semiconductor chip 101, the intermediate material layer having an ellipsoidal surface; the first shielding layer is positioned on the surface of the intermediate material layer and also has an ellipsoidal surface.
In another embodiment, the first shielding layer 103 is a magnetic field shielding layer and the second shielding layer 104 is an electric field shielding layer; or the first shielding layer 103 is an electric field shielding layer, and the second shielding layer 104 is a magnetic field shielding layer. The electric field shielding layer is made of copper, tungsten and aluminum; the material of the magnetic field shielding layer is CoFeB alloy, coFeTa, niFe, co, coFe, coPt or Ni, co and Fe alloy.
In an embodiment, referring to fig. 18, a bottom shielding layer 114 is further disposed on the functional surface of the semiconductor chip 101, the bottom shielding layer 114 covers the entire functional surface of the semiconductor chip 101, a peripheral edge of the bottom shielding layer 114 is flush with peripheral sidewalls of the semiconductor chip 101, a plurality of pads 102 penetrate through the bottom shielding layer 114, and the pads 102 are isolated from the bottom shielding layer 114 by an isolation layer 111; the first shielding layer 103 is connected with the peripheral edge of the bottom shielding layer 114.
The external contact structure 124 is a solder ball, or the external contact structure includes a metal pillar and a solder ball on the metal pillar.
In one embodiment, the method further comprises: a conductive contact structure in the substrate 301, the conductive contact structure being electrically connected to the first shield layer.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (10)
1. A method for forming a package structure, comprising:
providing a plurality of semiconductor chips, wherein each semiconductor chip comprises a functional surface and a non-functional surface opposite to the functional surface, the functional surface is provided with a plurality of bonding pads, metal bumps are formed on the surfaces of the bonding pads, the functional surface of each semiconductor chip is also provided with a bottom shielding layer, the bottom shielding layer covers the whole functional surface of each semiconductor chip, the peripheral edge of the bottom shielding layer is flush with the peripheral side walls of the semiconductor chips, the bonding pads penetrate through the bottom shielding layer, and the bonding pads are isolated from the bottom shielding layer through isolating layers; the forming process of the semiconductor chip with the bottom shielding layer comprises the following steps: providing a wafer, wherein a plurality of semiconductor chips are formed on the wafer, and each semiconductor chip comprises a top dielectric layer and a top interconnection structure positioned in the top dielectric layer; forming an isolation layer on the top dielectric layer; etching the isolation layer, forming a plurality of first openings and second openings surrounding the first openings in the isolation layer, wherein the rest of the isolation layer is only positioned between the first openings and the second openings, and the first openings and the second openings are separated; filling metal materials into the first openings to form a plurality of bonding pads, and filling metal materials into the second openings to form a bottom shielding layer; forming a metal bump on the pad; after the metal bumps are formed, cutting the wafer to form a plurality of discrete semiconductor chips with bottom shielding layers;
providing a substrate, wherein the substrate is provided with a plurality of circuit structures, the front surface of the substrate is provided with a plurality of input ports, the back surface of the substrate is provided with a plurality of output ports, and the input ports and the output ports are respectively connected with the corresponding circuit structures;
the semiconductor chips are inversely arranged on the surface of the front surface of the substrate, so that the metal lug on each semiconductor chip is connected with the corresponding input port on the front surface of the substrate;
forming an underfill layer between the functional surface of the semiconductor chip and the front surface of the substrate;
forming a first shielding layer for coating the non-functional surface and the side wall surface of the semiconductor chip and the side surface of the bottom filling layer, wherein the surface of the first shielding layer is in an ellipsoid shape, and the first shielding layer is connected with the peripheral edge of the bottom shielding layer;
forming a second shielding layer on the first shielding layer;
forming a plastic packaging layer on the second shielding layer and the substrate between the semiconductor chips;
and forming an external contact structure connected with the output port on the back surface of the substrate.
2. The method for forming the package structure according to claim 1, wherein the first shielding layer is directly formed on the non-functional surface and the sidewall surface of the semiconductor chip by a dispensing process or a screen printing process; the second shielding layer is formed through sputtering, a selective electroplating process, a dispensing process or a screen printing process.
3. The method for forming the package structure according to claim 2, wherein the material of the first shielding layer is solder or conductive silver paste, and the material of the second shielding layer is copper, tungsten, aluminum, solder or conductive silver paste.
4. The method of forming the package structure of claim 1, further comprising: forming an intermediate material layer on the surface of the non-functional surface and the side wall of the semiconductor chip, wherein the intermediate material layer has an ellipsoidal surface; and forming a first shielding layer on the surface of the intermediate material layer, wherein the first shielding layer also has an ellipsoidal surface.
5. The method of forming the package structure according to claim 1 or 4, wherein the first shielding layer is a magnetic field shielding layer, and the second shielding layer is an electric field shielding layer; or the first shielding layer is an electric field shielding layer, and the second shielding layer is a magnetic field shielding layer.
6. The method for forming the package structure according to claim 5, wherein the material of the electric field shielding layer is copper, tungsten, or aluminum; the material of the magnetic field shielding layer is CoFeB alloy, coFeTa, niFe, co, coFe, coPt or Ni, co and Fe alloy.
7. The method of forming a package structure of claim 1, wherein the pads and the bottom shield layer are formed by a same process, comprising the steps of: forming a metal material layer in the first opening and the second opening and on the surface of the isolation layer; and removing the metal material layer higher than the surface of the isolation layer in a planarization manner, forming a bonding pad in the first opening, and forming a bottom shielding layer in the second opening.
8. The method for forming the package structure according to claim 1, wherein the external contact structure is a solder ball, or the external contact structure comprises a metal pillar and a solder ball on the metal pillar.
9. The method of forming the package structure of claim 1, further comprising: a conductive contact structure in the substrate, the conductive contact structure being electrically connected to the first shielding layer.
10. The method for forming the package structure according to claim 1, wherein after the forming the external contact structure, the method further comprises: and cutting the substrate to form a plurality of separated packaging structures.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910681470.1A CN110534442B (en) | 2019-07-26 | 2019-07-26 | Forming method of packaging structure |
| PCT/CN2020/102758 WO2021017896A1 (en) | 2019-07-26 | 2020-07-17 | Packaging structure and fabrication method thereof |
| US17/629,549 US12119308B2 (en) | 2019-07-26 | 2020-07-17 | Packaging structure of semiconductor chip and formation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910681470.1A CN110534442B (en) | 2019-07-26 | 2019-07-26 | Forming method of packaging structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110534442A CN110534442A (en) | 2019-12-03 |
| CN110534442B true CN110534442B (en) | 2023-03-14 |
Family
ID=68661857
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910681470.1A Active CN110534442B (en) | 2019-07-26 | 2019-07-26 | Forming method of packaging structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110534442B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US12119308B2 (en) | 2019-07-26 | 2024-10-15 | Tongfu Microelectronics Co., Ltd. | Packaging structure of semiconductor chip and formation method thereof |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6630736B1 (en) * | 2000-07-27 | 2003-10-07 | National Semiconductor Corporation | Light barrier for light sensitive semiconductor devices |
| WO2010058646A1 (en) * | 2008-11-21 | 2010-05-27 | インターナショナル・ビジネス・マシーンズ・コーポレーション | Semiconductor package and method for manufacturing same |
| CN102347313A (en) * | 2011-09-30 | 2012-02-08 | 常熟市广大电器有限公司 | Packaging structure for integrated circuit chip |
| CN103745967A (en) * | 2013-12-05 | 2014-04-23 | 南通富士通微电子股份有限公司 | Lead frame and packaging structure |
| CN103915355A (en) * | 2013-12-05 | 2014-07-09 | 南通富士通微电子股份有限公司 | Package structure forming method |
| CN107114005A (en) * | 2014-12-12 | 2017-08-29 | 名幸电子有限公司 | Molded case circuit module and its manufacture method |
| CN107305883A (en) * | 2016-04-22 | 2017-10-31 | 矽品精密工业股份有限公司 | Electronic package and manufacturing method thereof |
| CN109698188A (en) * | 2018-12-29 | 2019-04-30 | 江苏长电科技股份有限公司 | Chip assembly, encapsulating structure and its forming method |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102007020656B4 (en) * | 2007-04-30 | 2009-05-07 | Infineon Technologies Ag | Semiconductor chip workpiece, semiconductor device, and method of manufacturing a semiconductor chip workpiece |
| JP5357241B2 (en) * | 2011-08-10 | 2013-12-04 | 新光電気工業株式会社 | Semiconductor device and manufacturing method of semiconductor device |
-
2019
- 2019-07-26 CN CN201910681470.1A patent/CN110534442B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6630736B1 (en) * | 2000-07-27 | 2003-10-07 | National Semiconductor Corporation | Light barrier for light sensitive semiconductor devices |
| WO2010058646A1 (en) * | 2008-11-21 | 2010-05-27 | インターナショナル・ビジネス・マシーンズ・コーポレーション | Semiconductor package and method for manufacturing same |
| CN102347313A (en) * | 2011-09-30 | 2012-02-08 | 常熟市广大电器有限公司 | Packaging structure for integrated circuit chip |
| CN103745967A (en) * | 2013-12-05 | 2014-04-23 | 南通富士通微电子股份有限公司 | Lead frame and packaging structure |
| CN103915355A (en) * | 2013-12-05 | 2014-07-09 | 南通富士通微电子股份有限公司 | Package structure forming method |
| CN107114005A (en) * | 2014-12-12 | 2017-08-29 | 名幸电子有限公司 | Molded case circuit module and its manufacture method |
| CN107305883A (en) * | 2016-04-22 | 2017-10-31 | 矽品精密工业股份有限公司 | Electronic package and manufacturing method thereof |
| CN109698188A (en) * | 2018-12-29 | 2019-04-30 | 江苏长电科技股份有限公司 | Chip assembly, encapsulating structure and its forming method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110534442A (en) | 2019-12-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110718473B (en) | Forming method of packaging structure | |
| US9362234B2 (en) | Shielded device packages having antennas and related fabrication methods | |
| TW202011489A (en) | Method for forming chip package | |
| JP2005150717A (en) | Integrated circuit equipment and its manufacturing method | |
| CN110718535B (en) | Packaging structure | |
| CN110473859B (en) | Packaging structure | |
| KR20230104720A (en) | Package structures with built-in EMI shielding | |
| CN110534444B (en) | Forming method of packaging structure | |
| CN110534445B (en) | Forming method of packaging structure | |
| CN110534442B (en) | Forming method of packaging structure | |
| CN110544677B (en) | Packaging structure | |
| CN110518002B (en) | Forming method of packaging structure | |
| CN110473844B (en) | Packaging structure | |
| CN110534502B (en) | Packaging structure | |
| CN110534443B (en) | Forming method of packaging structure | |
| CN110718472B (en) | Forming method of packaging structure | |
| CN110459530B (en) | Packaging structure | |
| CN110504226B (en) | Packaging structure | |
| CN110707071B (en) | Packaging structure | |
| US12119308B2 (en) | Packaging structure of semiconductor chip and formation method thereof | |
| CN110718536B (en) | Packaging structure | |
| CN110783208B (en) | Forming method of packaging structure | |
| CN110504175B (en) | Forming method of packaging structure | |
| US20220246540A1 (en) | Packaging structure and formation method thereof | |
| WO2021017895A1 (en) | Packaging structure and fabrication method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |