CN110534442A - The forming method of encapsulating structure - Google Patents
The forming method of encapsulating structure Download PDFInfo
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- CN110534442A CN110534442A CN201910681470.1A CN201910681470A CN110534442A CN 110534442 A CN110534442 A CN 110534442A CN 201910681470 A CN201910681470 A CN 201910681470A CN 110534442 A CN110534442 A CN 110534442A
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- 238000000034 method Methods 0.000 title claims abstract description 77
- 239000004065 semiconductor Substances 0.000 claims abstract description 153
- 239000000758 substrate Substances 0.000 claims abstract description 80
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 24
- 238000004806 packaging method and process Methods 0.000 claims abstract description 11
- 229920003023 plastic Polymers 0.000 claims abstract description 9
- 239000004033 plastic Substances 0.000 claims abstract description 9
- 239000010410 layer Substances 0.000 claims description 529
- 239000000463 material Substances 0.000 claims description 67
- 238000000926 separation method Methods 0.000 claims description 49
- 229910052751 metal Inorganic materials 0.000 claims description 43
- 239000002184 metal Substances 0.000 claims description 43
- 230000008878 coupling Effects 0.000 claims description 28
- 238000010168 coupling process Methods 0.000 claims description 28
- 238000005859 coupling reaction Methods 0.000 claims description 28
- 230000005684 electric field Effects 0.000 claims description 26
- 230000008569 process Effects 0.000 claims description 26
- 229910000679 solder Inorganic materials 0.000 claims description 19
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 15
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 15
- 239000010949 copper Substances 0.000 claims description 15
- 229910052802 copper Inorganic materials 0.000 claims description 15
- 239000007769 metal material Substances 0.000 claims description 15
- 229910052709 silver Inorganic materials 0.000 claims description 15
- 239000004332 silver Substances 0.000 claims description 15
- 238000005530 etching Methods 0.000 claims description 14
- 239000003292 glue Substances 0.000 claims description 14
- 238000004026 adhesive bonding Methods 0.000 claims description 12
- 229910052782 aluminium Inorganic materials 0.000 claims description 12
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 12
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 12
- 229910052721 tungsten Inorganic materials 0.000 claims description 12
- 239000010937 tungsten Substances 0.000 claims description 12
- -1 CoFeTa Inorganic materials 0.000 claims description 11
- 239000004411 aluminium Substances 0.000 claims description 11
- 238000010276 construction Methods 0.000 claims description 11
- 238000007650 screen-printing Methods 0.000 claims description 11
- 238000004544 sputter deposition Methods 0.000 claims description 11
- 238000011049 filling Methods 0.000 claims description 10
- 229910045601 alloy Inorganic materials 0.000 claims description 7
- 239000000956 alloy Substances 0.000 claims description 7
- 238000009713 electroplating Methods 0.000 claims description 7
- 229910003321 CoFe Inorganic materials 0.000 claims description 5
- 229910019236 CoFeB Inorganic materials 0.000 claims description 5
- 229910018979 CoPt Inorganic materials 0.000 claims description 5
- 229910001030 Iron–nickel alloy Inorganic materials 0.000 claims description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 5
- 229910052737 gold Inorganic materials 0.000 claims description 5
- 239000010931 gold Substances 0.000 claims description 5
- 229910052759 nickel Inorganic materials 0.000 claims description 5
- 239000011248 coating agent Substances 0.000 claims description 4
- 238000000576 coating method Methods 0.000 claims description 4
- 238000009413 insulation Methods 0.000 claims description 3
- 239000002344 surface layer Substances 0.000 claims 1
- 230000000694 effects Effects 0.000 abstract description 14
- 238000005253 cladding Methods 0.000 abstract description 6
- 238000004519 manufacturing process Methods 0.000 description 13
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 10
- 229910052718 tin Inorganic materials 0.000 description 10
- 239000011135 tin Substances 0.000 description 10
- 238000010586 diagram Methods 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 8
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 8
- 238000005240 physical vapour deposition Methods 0.000 description 6
- 229920005989 resin Polymers 0.000 description 6
- 239000011347 resin Substances 0.000 description 6
- 239000004020 conductor Substances 0.000 description 4
- 230000010354 integration Effects 0.000 description 4
- 150000002739 metals Chemical class 0.000 description 4
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 4
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 3
- NTSDHVIXFWZYSM-UHFFFAOYSA-N [Ag].[Sb].[Sn] Chemical compound [Ag].[Sb].[Sn] NTSDHVIXFWZYSM-UHFFFAOYSA-N 0.000 description 3
- PQIJHIWFHSVPMH-UHFFFAOYSA-N [Cu].[Ag].[Sn] Chemical compound [Cu].[Ag].[Sn] PQIJHIWFHSVPMH-UHFFFAOYSA-N 0.000 description 3
- PSMFTUMUGZHOOU-UHFFFAOYSA-N [In].[Sn].[Bi] Chemical compound [In].[Sn].[Bi] PSMFTUMUGZHOOU-UHFFFAOYSA-N 0.000 description 3
- WGCXSIWGFOQDEG-UHFFFAOYSA-N [Zn].[Sn].[In] Chemical compound [Zn].[Sn].[In] WGCXSIWGFOQDEG-UHFFFAOYSA-N 0.000 description 3
- 238000005520 cutting process Methods 0.000 description 3
- 230000005611 electricity Effects 0.000 description 3
- 238000005538 encapsulation Methods 0.000 description 3
- RHZWSUVWRRXEJF-UHFFFAOYSA-N indium tin Chemical compound [In].[Sn] RHZWSUVWRRXEJF-UHFFFAOYSA-N 0.000 description 3
- LQBJWKCYZGMFEV-UHFFFAOYSA-N lead tin Chemical compound [Sn].[Pb] LQBJWKCYZGMFEV-UHFFFAOYSA-N 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 239000002356 single layer Substances 0.000 description 3
- GZCWPZJOEIAXRU-UHFFFAOYSA-N tin zinc Chemical compound [Zn].[Sn] GZCWPZJOEIAXRU-UHFFFAOYSA-N 0.000 description 3
- 229910000969 tin-silver-copper Inorganic materials 0.000 description 3
- 229910052725 zinc Inorganic materials 0.000 description 3
- 239000011701 zinc Substances 0.000 description 3
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- 229910000531 Co alloy Inorganic materials 0.000 description 2
- 229910000640 Fe alloy Inorganic materials 0.000 description 2
- 229910000990 Ni alloy Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 239000011651 chromium Substances 0.000 description 2
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical compound [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 229910052742 iron Inorganic materials 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 239000009719 polyimide resin Substances 0.000 description 2
- 229920002635 polyurethane Polymers 0.000 description 2
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- 238000010992 reflux Methods 0.000 description 2
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- 239000000243 solution Substances 0.000 description 2
- 230000001360 synchronised effect Effects 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 239000004215 Carbon black (E152) Substances 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- ZCQWOFVYLHDMMC-UHFFFAOYSA-N Oxazole Chemical compound C1=COC=N1 ZCQWOFVYLHDMMC-UHFFFAOYSA-N 0.000 description 1
- 239000004952 Polyamide Substances 0.000 description 1
- 239000004695 Polyether sulfone Substances 0.000 description 1
- 239000004698 Polyethylene Substances 0.000 description 1
- 239000004743 Polypropylene Substances 0.000 description 1
- 239000004372 Polyvinyl alcohol Substances 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 238000000277 atomic layer chemical vapour deposition Methods 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000005038 ethylene vinyl acetate Substances 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 229930195733 hydrocarbon Natural products 0.000 description 1
- 150000002430 hydrocarbons Chemical class 0.000 description 1
- 238000001746 injection moulding Methods 0.000 description 1
- JEIPFZHSYJVQDO-UHFFFAOYSA-N iron(III) oxide Inorganic materials O=[Fe]O[Fe]=O JEIPFZHSYJVQDO-UHFFFAOYSA-N 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229920001200 poly(ethylene-vinyl acetate) Polymers 0.000 description 1
- 229920002647 polyamide Polymers 0.000 description 1
- 229920002577 polybenzoxazole Polymers 0.000 description 1
- 229920001707 polybutylene terephthalate Polymers 0.000 description 1
- 229920000515 polycarbonate Polymers 0.000 description 1
- 239000004417 polycarbonate Substances 0.000 description 1
- 150000004291 polyenes Chemical class 0.000 description 1
- 229920006393 polyether sulfone Polymers 0.000 description 1
- 229920000573 polyethylene Polymers 0.000 description 1
- 229920000139 polyethylene terephthalate Polymers 0.000 description 1
- 239000005020 polyethylene terephthalate Substances 0.000 description 1
- 229920000098 polyolefin Polymers 0.000 description 1
- 229920006389 polyphenyl polymer Polymers 0.000 description 1
- 229920001155 polypropylene Polymers 0.000 description 1
- 229920002451 polyvinyl alcohol Polymers 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000001228 spectrum Methods 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
- 239000002023 wood Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Health & Medical Sciences (AREA)
- Electromagnetism (AREA)
- Toxicology (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
Abstract
A kind of forming method of encapsulating structure, will be after being inverted on substrate front side surface of several semiconductor chips；The non-functional surface of cladding semiconductor chip and the first screen layer of sidewall surfaces and bottom filled layer side surface are formed, and the surface of first screen layer is in ellipsoid；Secondary shielding layer is formed in the first screen layer；Plastic packaging layer is formed on substrate in the secondary shielding layer and between semiconductor chip；The external contact structure connecting with output port is formed at the back side of the substrate.The first screen layer with ellipsoid surface formed can the uniform non-functional surface and sidewall surfaces for completely covering the semiconductor chip, and when the ellipsoid surface of first screen layer forms secondary shielding layer, the problem that secondary shielding layer is not in uneven thickness and edges cover is bad, so that the bulk shield that both first screen layer and the secondary shielding layer of formation are constituted is completely, to improve the effect of shielding.
Description
Technical field
The present invention relates to field of semiconductor fabrication more particularly to a kind of formation sides of the encapsulating structure with electromagnetic shielding
Method.
Background technique
The rapid development of electronic product of new generation, push integrated antenna package also to high density, high-frequency, micromation,
Highly integrated direction is developed, and high frequency chip often generates stronger electromagnetic wave, causes not expecting to inside and outside and chip is encapsulated
Interference or noise；In addition electronic component density is higher and higher, the distance of transmission line is more and more closer, so that coming from integrated circuit
The inside and outside electromagnetic interference problem of encapsulation also gets worse, while can reduce the quality of integrated circuit, service life etc..
In electronic equipment and electronic product, electromagnetic interference (Electromagnetic Interference) energy passes through
Conductibility coupling and radiativity coupling are to be transmitted.It, need to be using filtering to conductibility coupling to meet EMC Requirements
Technology is inhibited using electromagnetic interface filter part；Radiativity coupling is then needed to be inhibited using shield technology.In current electricity
Magnetic frequency spectrum is increasingly intensively, electromagnetic power density sharply increases, low and high level device or equipment are largely used in mixed way in unit volume
Etc. factors and in the case where causing equipment and system electromagnetic environment worsening, importance just seems more prominent.
A magnetic field shielding is arranged in a kind of existing electromagnetic shielding solution mainly on semiconductor package
Layer, for shielding the electromagnetic interference of chip chamber, but the effect of existing electromagnetic shielding still have it is to be hoisted.
Summary of the invention
The technical problem to be solved by the present invention is to how improve the effectiveness of existing encapsulating structure.
The present invention provides a kind of forming methods of encapsulating structure, comprising: provides several semiconductor chips, each semiconductor
Chip includes functional surfaces and the non-functional surface opposite with functional surfaces, has several pads, the bond pad surface on the functional surfaces
On be formed with metal coupling；
Substrate is provided, there are several line constructions in the substrate, the front of substrate has several input ports, substrate
The back side has several output ports, and the input port and output port are connected with corresponding line construction respectively；
By being inverted on substrate front side surface for several semiconductor chips, so that each semiconductor core on piece
Metal coupling is connected with input port corresponding on the front of substrate；
Bottom filled layer is formed between the functional surfaces of the semiconductor chip and the front face surface of substrate；
Form the first of the non-functional surface and sidewall surfaces and bottom filled layer side surface that coat the semiconductor chip
Shielded layer, and the surface of the first screen layer is in ellipsoid；
Secondary shielding layer is formed in the first screen layer；
Plastic packaging layer is formed on substrate in the secondary shielding layer and between semiconductor chip；
The external contact structure connecting with output port is formed at the back side of the substrate.
Optionally, the first screen layer is formed directly into the semiconductor core by gluing process or screen printing technique
The non-functional surface and sidewall surfaces of piece；The secondary shielding layer passes through sputtering, selective electroplating technique, gluing process or web plate print
Dataller's skill is formed.
Optionally, the material of the first screen layer is solder or conductive silver glue, the material of the secondary shielding layer be copper,
Tungsten, aluminium, solder or conductive silver glue.
Optionally, further includes: intermediate layer of material is formed on the surface of the semiconductor chip non-functional surface and side wall, it is described
Intermediate layer of material has the surface of ellipsoid；First screen layer is formed in intermediate materials layer surface, the first screen layer also has
There is the surface of ellipsoid.
Optionally, the first screen layer is magnetic field shielding layer, and the secondary shielding layer is electric field shielding layer；Or institute
Stating first screen layer is electric field shielding layer, and the secondary shielding layer is magnetic field shielding layer.
Optionally, the material of the electric field shielding layer is copper, tungsten, aluminium；The material of the magnetic field shielding layer is CoFeB conjunction
Gold, CoFeTa, NiFe, Co, CoFe, CoPt or Ni, Co and Fe alloy.
Optionally, also there is bottom shield layer, the bottom shield layer covering half on the functional surfaces of the semiconductor chip
The entire functional surfaces of conductor chip, the edge of the bottom shield layer is flushed with the surrounding side wall of semiconductor chip, several
Pad runs through bottom shield layer, is isolated between pad and bottom shield layer by separation layer；When forming the first screen layer,
The first screen layer is connect with the edge of bottom shield layer.
Optionally, the forming process of the semiconductor chip with bottom shielded layer are as follows: wafer is provided, on the wafer
Several semiconductor chips are formed with, the semiconductor chip includes top layer dielectric layer and the top layer interconnection in top layer dielectric layer
Structure；Separation layer is formed in the top layer dielectric layer；The separation layer is etched, several first is formed in the separation layer and opens
Mouthful and surround it is described it is several first opening second opening, and remaining separation layer be only located at the first opening and the second opening it
Between, the first opening and the second opening are separated；Filling metal material forms several pads in several first openings,
Filling metal material forms bottom shield layer in second opening；Metal coupling is formed on the pad；Described in formation
After metal coupling, the wafer is cut, forms several discrete semiconductor chips with bottom shielded layer.
Optionally, several pads and bottom shield layer are formed by same technique, comprising steps of opening described first
Metal material layer is formed in mouth and the second opening and on the surface of separation layer；Planarization removal is higher than the insulation surface
Metal material layer forms pad in first opening, forms bottom shield layer in second opening.
Optionally, the external contact structure is that soldered ball or the outer contacting structure include metal column and be located at metal
Soldered ball on column.
Optionally, further includes: the conductive contact structure in the substrate, the conductive contact structure and the first shielding
Layer electrical connection.
Optionally, after the formation external contact structure, further includes: cut the substrate, form several isolated encapsulation
Structure.
Compared with prior art, technical solution of the present invention has the advantage that
Several semiconductor chips are being inverted in substrate front side surface by the forming method of encapsulating structure of the invention
On, bottom filled layer is formed between the functional surfaces of the semiconductor chip and the front face surface of substrate；Formation cladding is described partly to be led
The non-functional surface and sidewall surfaces of body chip and the first screen layer of bottom filled layer side surface, and the first screen layer
Surface is in ellipsoid；Secondary shielding layer is formed in the first screen layer；In the secondary shielding layer and semiconductor core
Plastic packaging layer is formed on substrate between piece；The external contact structure connecting with output port is formed at the back side of the substrate.Shape
At the first screen layer with ellipsoid surface not only first screen layer itself uniform can completely cover the semiconductor
The non-functional surface and sidewall surfaces of chip, and when the ellipsoid surface of first screen layer forms secondary shielding layer, the second screen
The problem that layer is not in uneven thickness and edges cover is bad is covered, so that the second screen of first screen layer and formation
The bulk shield for covering both layers composition is completely, to improve the effect of shielding.Also, it realizes substrate and there is the first screen
Cover the integration packaging production of the semiconductor chip of layer and secondary shielding layer.
Further, intermediate layer of material, the centre are formed on the surface of the non-functional surface of the semiconductor chip and side wall
Material layer has the surface of ellipsoid；First screen layer is formed in intermediate materials layer surface, the first screen layer also has ellipse
Spherical surface.There is the intermediate layer of material on ellipsoid surface by being formed, kinds of processes can be passed through in intermediate layer of material
The first screen layer with different materials is formed, and the first screen layer formed also has the surface of spheroid shape, and in centre
When forming first screen layer on the surface of the ellipsoid of material layer, first screen layer not will receive the shadow of wedge angle or steep sidewalls
It rings, so that being formed in first screen layer is not in uneven thickness and the bad problem of edges cover, to improve shielding
The integrality of layer.
Further, the first screen layer is magnetic field shielding layer, then the secondary shielding layer formed is electric field shielding layer；Or
The first screen layer is electric field shielding layer, then the secondary shielding layer formed is magnetic field shielding layer, by forming structure above-mentioned
First screen layer and secondary shielding layer so that first screen layer and secondary shielding layer are directed to electric field respectively or magnetic field is shielded
It covers, to improve the shield effectiveness of shielded layer, and the secondary shielding layer can cover in the first screen layer thickness not
Uniform and bad edges cover place, so that the bulk shield that both first screen layer and secondary shielding layer are constituted
It is completely, to further improve the effect of shielding.
Further, after the formation external contact structure, the preformed cover plate is cut, forms several isolated encapsulation knots
Structure, thus realize the batch making with the encapsulating structure of first screen layer and secondary shielding layer, improve the efficiency of production.
Further, also there is bottom shield layer, the bottom shield layer covering half on the functional surfaces of the semiconductor chip
The entire functional surfaces of conductor chip, the edge of the bottom shield layer is flushed with the surrounding side wall of semiconductor chip, several
Pad runs through bottom shield layer, is isolated between pad and bottom shield layer by separation layer；When forming the first screen layer,
The first screen layer is connect with the edge of bottom shield layer.I.e. in the present embodiment not only after forming first screen layer,
It also will form secondary shielding layer in first screen layer, thus the secondary shielding layer can cover thickness in the first screen layer
The place that degree is uneven and edges cover is bad, so that the whole screen that both first screen layer and secondary shielding layer are constituted
Covering layer is completely, to improve the effect of shielding, and due to also having bottom shield on the functional surfaces of the semiconductor chip
Layer, when forming the first screen layer, the first screen layer is connect with the edge of bottom shield layer, so that envelope
Semiconductor chip in the assembling structure cladding complete or comprehensive by bottom shielded layer and first screen layer, thus electric and magnetic fields
It cannot be entered in encapsulating structure by the bottom of encapsulating structure and bring electromagnetic interference to semiconductor chip, to realize to semiconductor
Chip carries out comprehensive electromagnetic shielding, further improves the effect of electromagnetic shielding.
Further, the forming process of the semiconductor chip with bottom shielded layer are as follows: wafer is provided, on the wafer
Several semiconductor chips are formed with, the semiconductor chip includes top layer dielectric layer and the top layer interconnection in top layer dielectric layer
Structure；Separation layer is formed in the top layer dielectric layer；The separation layer is etched, several first is formed in the separation layer and opens
Mouthful and surround it is described it is several first opening second opening, and remaining separation layer be only located at the first opening and the second opening it
Between, the first opening and the second opening are separated；Filling metal material forms several pads in several first openings,
Filling metal material forms bottom shield layer in second opening；Metal coupling is formed on the pad；Described in formation
After metal coupling, the wafer is cut, forms several discrete semiconductor chips with bottom shielded layer.Aforementioned process is not only
Be capable of forming bottom shielded layer, and formed bottom shield layer process and existing semiconductor chip fabrication technique it is integrated, bottom
The manufacturing process of shielded layer synchronous with the manufacturing process of pad can carry out, and simplify manufacture craft, reduce technology difficulty, mention
High efficiency.
Detailed description of the invention
Fig. 1-Figure 12 is the structural schematic diagram of the forming process of first embodiment of the invention encapsulating structure；
Figure 13-Figure 18 is the structural schematic diagram of the forming process of second embodiment of the invention encapsulating structure.
Specific embodiment
As described in the background art, the effect of existing electromagnetic shielding still has to be hoisted.
The study found that existing magnetic field shielding layer is formed generally by sputtering technology, due to semiconductor package thickness
Degree is general thicker, and semiconductor package is generally in rectangle so that semiconductor package there are multiple apex angles and side wall compared with
To be precipitous, when forming the magnetic field shielding layer of cladding semiconductor package by sputtering technology, the magnetic field shielding layer of formation
Thickness, which is easy uneven, semiconductor package edge, can have unlapped situation, so that the shielding of magnetic field shielding layer
Effect is difficult to ensure.
For this purpose, the present invention provides a kind of encapsulating structure and forming method thereof, the forming method is by described several half
Conductor chip is inverted on substrate front side surface, the shape between the functional surfaces of the semiconductor chip and the front face surface of substrate
At bottom filled layer；Form the of the non-functional surface for coating the semiconductor chip and sidewall surfaces and bottom filled layer side surface
One shielded layer, and the surface of the first screen layer is in ellipsoid；Secondary shielding layer is formed in the first screen layer；Institute
State formation plastic packaging layer on the substrate in secondary shielding layer and between semiconductor chip；It is formed and is exported at the back side of the substrate
The external contact structure of port connection.Not only first screen layer itself can be equal for the first screen layer with ellipsoid surface formed
The uniform non-functional surface and sidewall surfaces for completely covering the semiconductor chip, and on the ellipsoid surface of first screen layer
When forming secondary shielding layer, the problem that secondary shielding layer is not in uneven thickness and edges cover is bad, so that
The bulk shield that both first screen layer and the secondary shielding layer of formation are constituted is completely, to improve the effect of shielding.
In order to make the foregoing objectives, features and advantages of the present invention clearer and more comprehensible, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.When describing the embodiments of the present invention, for purposes of illustration only, schematic diagram can disobey general ratio
Example makees partial enlargement, and the schematic diagram is example, should not be limited the scope of the invention herein.In addition, in reality
It should include the three-dimensional space of length, width and depth in the production of border.
Fig. 1-Figure 12 is the structural schematic diagram of the forming process of first embodiment of the invention encapsulating structure.
It is Fig. 1 along the schematic diagram of the section structure in the direction cutting line AB with reference to Fig. 1-Fig. 4, Fig. 2, several semiconductor chips is provided
101, each semiconductor chip 101 includes functional surfaces and the non-functional surface opposite with functional surfaces, is had on the functional surfaces several
Pad 102 is formed with metal coupling 130 on the pad 102.
Integrated circuit (not shown), the semiconductor chip are formed in the functional surfaces of the semiconductor chip 101
There are several pads 102, the pad 102 is electrically connected with the integrated circuit in semiconductor chip 101, institute on 101 functional surfaces
State port of the pad 102 as integrated circuit and external electrical connections in semiconductor chip 101.
The functional surfaces of the semiconductor chip 101 are to be used to form the one side of integrated circuit, the non-functional surface be with
The opposite one side of functional surfaces, surrounded surface is the side wall of semiconductor chip 101 between functional surfaces and non-functional surface.
The semiconductor chip 101 is formed by semiconductor integration making technology, is specifically please referred to Fig. 1 and Fig. 2, is provided
Wafer 100, the chip area and the Cutting Road region between chip area that the wafer 100 includes several ranks arrangement；
Several semiconductor chips 101 are correspondingly formed in several chip areas of the wafer 100；In the function of the semiconductor chip 101
Several pads 102 can be formed on face；With reference to Fig. 3, metal coupling 130, the metal coupling are formed on 102 surface of pad
One or more of 130 materials of aluminum, nickel, tin, tungsten, platinum, copper, titanium, chromium, tantalum, gold, silver, the formation of the metal coupling 130
Technique can be plating, sputtering or physical gas-phase deposition, and the purpose for forming metal coupling 130 is that pad 102 is drawn height,
Convenient for subsequent wiring, and the metal coupling 130 also has the function of protecting pad and heat transfer；With reference to Fig. 4, along Cutting Road
Divide the wafer 100, forms several discrete semiconductor chips 101.
In one embodiment, the material of the wafer 100 can be monocrystalline silicon (Si), monocrystalline germanium (Ge) or SiGe
(GeSi), silicon carbide (SiC)；It is also possible to silicon-on-insulator (SOI), germanium on insulator (GOI)；It or can also be others
III-V compounds of group such as material, such as GaAs.
In one embodiment, the integrated circuit in the semiconductor chip 101 may include several semiconductor devices (such as
Transistor, memory, diode and/or triode etc.) and by interconnection structure (including the metal connecting line of semiconductor devices connection
And metal plug).
In the present embodiment, the semiconductor chip 101 is the semiconductor chip being electromagnetically shielded.
With reference to Fig. 5, substrate 301 is provided, there are several line constructions in the substrate 301, if the front of substrate 301 has
Dry input port, the back side of substrate have several output ports, the input port and output port respectively with corresponding route
Structure connection；By being inverted on substrate front side surface for several semiconductor chips 101, so that each semiconductor chip
Metal coupling 130 on 101 is connected with input port corresponding on the front of substrate.
The substrate 301 can be PCB substrate or line carrier plate.There are several line constructions in the substrate 301, if
Main line line structure can be in ranks part in basic, each line construction with to drink input port and output port connect.
It is subsequent in the present embodiment to realize substrate 301 and the integration packaging with first screen layer and the semiconductor chip of secondary shielding layer.
By several semiconductor chips 101 when being inverted on substrate front side surface, each semiconductor chip 101
On metal coupling 130 connected with input port corresponding on substrate 301 by a solder layer.
The material of the solder layer is tin, Xi Yin, tin-lead, tin silver copper, tin silver-colored zinc, tin zinc, tin bismuth indium, tin indium, Sillim, tin
One or more of metals such as copper, tin zinc indium or tin silver antimony.
In one embodiment, further includes: also there is conductive contact structure (not shown) in the substrate 301, it is described
Conductive contact structure is electrically connected with the first screen layer being subsequently formed, so that shielded layer can pass through partially wiring layer 123 again
The electrostatic interference in electric discharge or the barrier external world.
With reference to Fig. 6, bottom filling is formed between the functional surfaces of the semiconductor chip 101 and the front face surface of substrate 301
Layer 132.
The bottom filled layer 132 covers the side of the metal coupling 130.
The formation process of the bottom filled layer 132 is to be molded or turn modeling technique, and the material of the bottom filled layer 132 is tree
Rouge, the resin can be epoxy resin, polyimide resin, benzocyclobutane olefine resin or polybenzoxazoles resin.
With reference to Fig. 7, the non-functional surface for coating the semiconductor chip 101 and sidewall surfaces and bottom filled layer 132 are formed
The first screen layer 103 of side surface, and the surface of the first screen layer 103 is in ellipsoid.
In the present embodiment, the first screen layer 103 that formed can only coat the non-functional surface of the semiconductor chip 101
With sidewall surfaces (and 132 side surface of bottom filled layer).
The first screen layer 103 is formed directly into the semiconductor chip by gluing process or screen printing technique
103 non-functional surface and sidewall surfaces not will form first screen layer, the institute of formation on the support plate of 101 two sides of semiconductor chip
Stating first screen layer 103 can the uniform non-functional surface and sidewall surfaces for completely covering the semiconductor chip.Described first
The material of shielded layer 103 can with solder or conductive silver glue, by gluing process in the non-functional surface of the semiconductor chip 101 and
Sidewall surfaces spot printing solder or conductive silver glue form the first screen layer 103 with ellipsoid surface.Pass through screen printing technique
Solder layer is formed in the non-functional surface and sidewall surfaces of semiconductor chip 101, and carries out reflux technique, being formed has ellipsoid table
The first screen layer 103 in face.The solder be tin, Xi Yin, tin-lead, tin silver copper, tin silver-colored zinc, tin zinc, tin bismuth indium, tin indium, Sillim,
One or more of metals such as tin copper, tin zinc indium or tin silver antimony.
The surface of the first screen layer 103 refers to that the surface of first screen layer 103 does not have wedge angle, the first screen in ellipsoid
Cover the surface of layer 103 in arcuation, the first screen layer 103 with ellipsoid surface of formation not only first screen layer 103 itself
Can the uniform non-functional surface and sidewall surfaces for completely covering the semiconductor chip 101, and it is subsequent in first screen layer
When 103 ellipsoid surface forms secondary shielding layer, secondary shielding layer is not in uneven thickness and edges cover is bad
The problem of, so that the bulk shield that both first screen layer 103 and the secondary shielding layer being subsequently formed are constituted is complete
, improve the effect of shielding.
In other embodiments, intermediate materials are formed on the surface of the non-functional surface of the semiconductor chip 101 and side wall
Layer (not shown), the intermediate layer of material have the surface of ellipsoid；First screen layer is formed in intermediate materials layer surface,
The first screen layer also has the surface of ellipsoid.There is the intermediate layer of material on ellipsoid surface by being formed, in intermediate wood
On the bed of material can by kinds of processes formed have different materials first screen layer, and formed first screen layer also have it is ellipse
The surface of ball-type.
Specifically, the material of the intermediate layer of material can be non-conductive glue, conductive silver glue, liquid resin or weldering
Material, the material for forming the intermediate layer of material can be gluing process or screen printing technique.The shape in the intermediate layer of material
It can be using sputtering, selective electroplating technique, gluing process or screen printing work at the first screen layer with spheroid shape surface
The material of skill, the corresponding first screen layer can be copper, tungsten, aluminium, solder or conductive silver glue, or subsequent to mention
Magnetic field shielding layer and electric field shielding layer material.
When the first screen layer of formation also covers the substrate surface of semiconductor chip two sides, it is subsequently formed secondary shielding layer
The first screen layer on the substrate of semiconductor chip two sides can be removed by etching technics afterwards.In the present embodiment, the formation
First screen layer 103 is the shielded layer of electric and magnetic fields, and first screen layer 103 is used for the shielding of electric and magnetic fields, is subsequently formed
Secondary shielding layer be also electric and magnetic fields shielded layer, secondary shielding layer be used for electric and magnetic fields shielding.
The study found that existing shielded layer should shield electric field armoured magnetic field again, and the single layer screen of existing certain material
Covering layer or multi-layer phase only can have preferable shield effectiveness to electric field with the shielded layer of material or analog material, to the screen in magnetic field
It covers that effect is relatively weak, affects the shield effectiveness of shielded layer.Thus in other embodiments, the first screen layer 103 is
Magnetic field shielding layer, first screen layer is used for armoured magnetic field, and the secondary shielding layer being subsequently formed is electric field shielding layer, secondary shielding
Layer is for shielding electric field；Or the first screen layer is electric field shielding layer, and first screen layer is for shielding electric field, and described the
Two shielded layers are magnetic field shielding layer, and secondary shielding layer is used for armoured magnetic field, by formed structure above-mentioned first screen layer and
Secondary shielding layer, so that first screen layer and secondary shielding layer are directed to electric field respectively or magnetic field is shielded, to improve screen
Cover the shield effectiveness of layer.When the first screen layer 103 is electric field shielding layer, the first screen layer 103 (electric field shielding layer)
Material be copper, tungsten, aluminium；When the first screen layer 103 is magnetic field shielding layer, the 103 (magnetic field shielding of first screen layer
Layer) material be CoFeB alloy, CoFeTa, NiFe, Co, CoFe, CoPt or Ni, Co and Fe alloy.Form described first
Shielded layer 103 can use sputtering, physical vapour deposition (PVD), atomic layer deposition or chemical vapor deposition or other suitable works
Skill.
With reference to Fig. 8, secondary shielding layer 104 is formed in the first screen layer 103.
In the present embodiment, the secondary shielding layer 104 is formed by sputtering, the material of the secondary shielding layer 104 be copper,
The metals such as tungsten, aluminium, the secondary shielding layer 104 of the formation be not only located at coat the semiconductor chip 101 non-functional surface and
On 103 surface of first screen layer of sidewall surfaces, the secondary shielding layer 104 is also located at the support plate of 101 two sides of semiconductor chip
On 201 surfaces.
In other embodiments, the secondary shielding layer can be only located at the non-functional surface for coating the semiconductor chip and side
On 103 surface of first screen layer of wall surface, and the surface of the secondary shielding layer is in ellipsoid, and the secondary shielding layer passes through
Selective electroplating technique, gluing process or screen printing technique are formed, and the secondary shielding layer formed is enabled preferably to cover institute
First screen layer is stated, prevent from occurring uneven thickness in secondary shielding layer or covers bad place, is further ensured that the first screen
The integrality of the bulk shield of both layer 103 and secondary shielding layer composition is covered, and subsequent without additional exposure mask and etching
Technique removes semiconductor chip.
The material of the secondary shielding layer can be copper, solder or conductive silver glue.The material of the secondary shielding layer is copper
When, the secondary shielding layer is formed by selective electroplating technique, it is specific: mask layer (figure is first formed on the substrate 301
In be not shown), there is in the mask layer non-functional surface for exposing semiconductor chip 101 and the first screen in sidewall surfaces
Cover the opening of layer 103；Using the first screen layer 103 as conductive layer when plating, plating forms second in said opening
Shielded layer；Remove the mask layer.
The material of the secondary shielding layer is solder or conductive silver glue, can pass through gluing process or screen printing technique shape
At the secondary shielding layer.Specifically, solder or conductive silver glue point are coated in 101 side of semiconductor chip when carrying out gluing process
On 103 surface of first screen layer on wall and non-functional surface.Carry out screen printing when, will have first meshed web plate as
On substrate 301, in the corresponding mesh being located in web plate of each semiconductor chip 101；It is brushed in mesh into solder, solder
Cover 103 surface of first screen layer on 101 side wall of semiconductor chip and non-functional surface；Remove the web plate；To solder into
Row reflux, forms secondary shielding layer in first screen layer 103.
In one embodiment, the solder is tin, Xi Yin, tin-lead, tin silver copper, tin silver-colored zinc, tin zinc, tin bismuth indium, tin indium, tin
One or more of metals such as gold, tin copper, tin zinc indium or tin silver antimony.
In other embodiments, the first screen layer 103 is magnetic field shielding layer, then the secondary shielding layer 104 formed is
Electric field shielding layer；Or the first screen layer 103 is electric field shielding layer, then the secondary shielding layer 104 formed is magnetic field shielding
Layer, by forming the first screen layer and secondary shielding layer of structure above-mentioned, so that first screen layer and secondary shielding layer difference
It is shielded for electric field or magnetic field, to improve the shield effectiveness of shielded layer.When the secondary shielding layer 104 is electric field screen
Layer is covered, the material of the secondary shielding layer 104 (electric field shielding layer) is copper, tungsten, aluminium；When the secondary shielding layer 104 is magnetic field
Shielded layer, the material of the secondary shielding layer 104 (magnetic field shielding layer) be CoFeB alloy, CoFeTa, NiFe, Co, CoFe,
The alloy of CoPt or Ni, Co and Fe.Sputtering, physical vapour deposition (PVD), atomic layer can be used by forming the secondary shielding layer 104
Deposition or chemical vapor deposition or other suitable techniques.
In one embodiment, after forming the secondary shielding layer 104, described adjacent half can be removed by etching technics
The first screen layer on substrate between conductor chip 101.
With reference to Fig. 9, the secondary shielding material layer 104 on the substrate 301 of 101 two sides of semiconductor chip is removed.
The secondary shielding material layer 104 removed on the substrate 301 of 101 two sides of semiconductor chip can use dry etching work
Skill, such as plasma etching industrial.
With reference to Figure 10, modeling is formed on the substrate 301 in the secondary shielding layer 104 and between semiconductor chip 101
Sealing 105.
The plastic packaging layer 105 is for sealing and fixing the semiconductor chip 101, to be subsequently formed preformed cover plate.
The material of the plastic packaging layer 105 can be for epoxy resin, polyimide resin, benzocyclobutane olefine resin, polyphenyl simultaneously
Oxazole resin, polybutylene terephthalate, polycarbonate, polyethylene terephthalate, polyethylene, polypropylene, polyene
One of hydrocarbon, polyurethane, polyolefin, polyether sulfone, polyamide, polyurethane, ethylene-vinyl acetate copolymer or polyvinyl alcohol
Or it is several.
Forming the plastic packaging layer 105 can be using Shooting Technique (injection molding) or turn modeling technique
(transfer molding) or other suitable techniques.
With reference to Figure 11, the external contact structure 124 connecting with output port is formed on the back side of the substrate 301.
External contact structure described in the present embodiment 124 is soldered ball, and in other embodiments, the outer contacting structure includes
Metal column and the soldered ball on metal column.
With reference to Figure 11 and Figure 12, after the formation external contact structure 124, the preformed cover plate 10 is cut, is formed several
Isolated encapsulating structure 11.
With reference to Figure 12, each encapsulating structure 11 includes substrate 301, has line construction, substrate in the substrate 301
Front there are several input ports, the back side of substrate has several output ports, the input port and output port difference
It is connect with line construction；
The semiconductor chip 101 being inverted on the front of substrate 301, the semiconductor chip 101 include functional surfaces and with
Functional surfaces opposite non-functional surface has several pads 102 on the functional surfaces, has metal coupling on the pad 102
130, the metal coupling 130 on each semiconductor chip 101 is connected with input port corresponding on the front of substrate；
Bottom filled layer 132 between the functional surfaces of the semiconductor chip 101 and the front face surface of substrate 301；
Coat the of 132 side surface of non-functional surface and sidewall surfaces and bottom filled layer of the semiconductor chip 101
One shielded layer 103, and the surface of the first screen layer 103 is in ellipsoid；
Secondary shielding layer 104 in the first screen layer 103
The external contact structure 124 being connect with output port positioned at the back side of the substrate 301.
The external contact structure 124 is soldered ball or the outer contacting structure includes metal column and is located on metal column
Soldered ball.
The present invention realizes there is first screen layer 103 and secondary shielding layer 104 by aforesaid semiconductor integration making technology
Encapsulating structure 11 batch making, improve the efficiency of production.
Figure 13-Figure 18 is the structural schematic diagram of the forming process of second embodiment of the invention encapsulating structure.Second embodiment
Difference with first embodiment is: also having bottom shield layer, the bottom shield on the functional surfaces of the semiconductor chip
The entire functional surfaces of layer covering semiconductor chip, the edge of the bottom shield layer and the surrounding side wall of semiconductor chip are neat
Flat, several pads run through bottom shield layer, are isolated between pad and bottom shield layer by separation layer；Forming first screen
When covering layer, the first screen layer is connect with the edge of bottom shield layer.Not only the first screen is being formed i.e. in the present embodiment
After covering layer, secondary shielding layer also will form in first screen layer, thus the secondary shielding layer can cover first screen
Place in uneven thickness in layer and bad edges cover is covered, so that both first screen layer and secondary shielding layer are constituted
Bulk shield be it is complete, improve the effect of shielding, and due to also having on the functional surfaces of the semiconductor chip
Bottom shield layer, when forming the first screen layer, the first screen layer is connect with the edge of bottom shield layer, from
And the cladding for making the semiconductor chip in encapsulating structure complete or comprehensive by bottom shielded layer and first screen layer, thus electricity
Field and magnetic field cannot be entered in encapsulating structure by the bottom of encapsulating structure brings electromagnetic interference to semiconductor chip, to realize
Comprehensive electromagnetic shielding is carried out to semiconductor chip, further improves the effect of electromagnetic shielding.
The forming process of the semiconductor chip with bottom shielded layer are as follows: Figure 13 is referred to, wafer 100 is provided, it is described
Several semiconductor chips 101 are formed on wafer 100, the semiconductor chip 101 is including top layer dielectric layer 108 and is located at top layer
Top layer interconnection structure 109 in dielectric layer 108, the semiconductor chip further include being located at wafer (or semiconductor substrate) surface shape
At several semiconductor devices (such as transistor etc.), between 100 surface of top layer dielectric layer 108 and wafer it is several layer by layer
Between dielectric layer, there is corresponding interconnection structure, interconnection structure can be mutual with upper and lower level in interlayer dielectric layer in every layer of interlayer dielectric layer
It is electrically connected even or with semiconductor devices, the top layer interconnection structure 109 in the top layer dielectric layer 108 can be with the layer of adjacent layer
Between interconnection structure electrical connection in dielectric layer；Separation layer is formed in the top layer dielectric layer 108.
Separation layer described in the present embodiment be double stacked structure, including the first separation layer 110 and be located at the first separation layer
The material of the second separation layer 111 on 110, the first separation layer 110 and the second separation layer 111 is not identical, 110 He of the first separation layer
The material of second separation layer 111 can be one of silica, silicon nitride, silicon oxynitride, be accurately controlled shape convenient for subsequent
At second opening depth, prevent formation second be open when over etching separation layer so that second opening expose top layer Jie
The part of the surface of Portions of top layer interconnection structure 109 in matter layer 108, it is subsequent in the second opening formed bottom shielded layer when cause to push up
Short circuit between layer interconnection structure 109.In other embodiments, the separation layer can be single layer structure.
With reference to Figure 14, the separation layer is etched, if forming several first openings 112 in the separation layer and surrounding described
Second opening 113 of dry first opening 112, and remaining separation layer 111 be only located at the first opening 112 and the second opening 112 it
Between, first opening 112 and the second opening 111 are separated.
It is several first opening 112 be it is discrete, it is described first opening 112 run through the separation layer, each first opening
112 can expose 109 part of the surface of top layer interconnection structure accordingly, and subsequent filling metal is formed in first opening 112
Pad.
It is described second opening 113 surround it is described first opening 112, second opening 113 and first opening 112 between by every
Absciss layer 111 separates, and the depth of second opening 113 is less than the thickness of separation layer, first opening 112 and around first
The exterior domain of the separation layer 111 of opening 112 all corresponds to the region of the second opening 113, and third opening 113 is connection, after
When continuing the formation bottom shielded layer in third opening 113, the bottom shielded layer can be covered on the functional surfaces of semiconductor chip 101
All regions other than pad (being formed in the first opening 112) and around the separation layer of pad, when in semiconductor
When the non-functional surface of chip 101 and the surface of side wall form first screen layer, the four of the first screen layer and bottom shield layer
Circumferential edges connection, so that the semiconductor chip in encapsulating structure is complete or comprehensive by bottom shielded layer and first screen layer
Cladding, thus electric and magnetic fields cannot be entered in encapsulating structure by the bottom of encapsulating structure and bring electromagnetism to semiconductor chip
Interference carries out comprehensive electromagnetic shielding to semiconductor chip to realize, further improves the effect of electromagnetic shielding.
In the present embodiment, uses the first etching technics to etch second separation layer 111 and made with first separation layer 110
For stop-layer, the second opening is formed in second separation layer 111；Then, the second etching technics, etching described second are carried out
Separation layer 111 and the first separation layer 110 form the first opening, In in second separation layer 111 and the first separation layer 110
Before carrying out the first etching technics or the second etching technics, it can be formed on the surface of second separation layer 110 corresponding
Mask layer.It should be noted that second etching technics can also be carried out prior to the first etching technics.
In other embodiments, when the separation layer is single layer structure, twice etching technique can also be carried out and be respectively formed
The first opening and the second opening, by control etching technics time, thus control formation second opening depth (second opens
The depth of mouth is less than the thickness of separation layer).
With reference to Figure 15, filling metal material forms several pads 102 in several first openings, opens described second
Filling metal material forms bottom shield layer 114 in mouthful；Metal coupling 130 is formed on the pad 102；With reference to Figure 16, shape
After metal coupling 130, the wafer is cut, forms several discrete semiconductor chips 101 with bottom shielded layer 114.
In one embodiment, several pads 102 and bottom shield layer 114 are formed by same technique, comprising steps of
Metal material layer is formed in the first opening and the second opening and on the surface of separation layer, the metal material layer passes through
Physical vapour deposition (PVD), sputtering or electroplating technology are formed, the material of the metal material layer can for aluminium, nickel, tin, tungsten, platinum,
One or more of copper, titanium, chromium, tantalum, gold, silver；Planarization removal is higher than the metal material layer of the insulation surface, in institute
Formation pad 102 in the first opening is stated, forms bottom shield layer 114 in second opening.
With reference to Figure 17, Figure 17 is the overlooking structure diagram of pad 102 and bottom shield layer 114 in Figure 16, in conjunction with reference
Figure 16 and Figure 17, has bottom shield layer 114 on the functional surfaces of the semiconductor chip 101, and the bottom shield layer 114 covers
The entire functional surfaces of semiconductor chip 101, the edge of the bottom shield layer 114 and four sides of semiconductor chip 101
Wall flushes, several pads 102 run through bottom shield layer 114, between pad 102 and bottom shield layer 114 by separation layer 111 every
From.
Process and the existing semiconductor chip fabrication technique that bottom shield layer 114 is previously formed in the application are integrated, bottom
The manufacturing process of shielded layer 114 synchronous with the manufacturing process of pad 102 can carry out, and simplify manufacture craft, reduce technique
Difficulty improves efficiency.
With reference to Figure 18, the semiconductor chip 101 with bottom shield layer 114 is inverted on substrate 301, so that described every
Metal coupling 130 on a semiconductor chip 101 is connected with input port corresponding on the front of substrate 301；It is partly led described
Bottom filled layer 132 is formed between the functional surfaces of body chip 101 and the front face surface of substrate 301；It is formed and coats the semiconductor core
The non-functional surface and sidewall surfaces of piece 101 and the first screen layer 103 of 132 side surface of bottom filled layer, and first screen
The surface of layer 103 is covered in ellipsoid；Secondary shielding layer 104 is formed in the first screen layer 103；In the secondary shielding layer
Plastic packaging layer 105 is formed on substrate 301 on 104 and between semiconductor chip 101；The substrate 301 the back side formed with
The external contact structure 124 of output port connection.
It should be noted that in second embodiment with structure same or similar in first embodiment other limit or retouch
It states, is not repeating in a second embodiment, specifically please refer to the restriction or description of corresponding portion in first embodiment.
A kind of encapsulating structure is additionally provided in one embodiment of the invention, please refers to Figure 11 or Figure 18, comprising:
Substrate 301 has several line constructions in the substrate 301, and the front of substrate 301 has several input ports,
The back side of substrate has several output ports, and the input port and output port are connected with corresponding line construction respectively；
Several semiconductor chips 101 being inverted on the front of substrate 301, each semiconductor chip 101 include functional surfaces
The non-functional surface opposite with functional surfaces has several pads 102 on the functional surfaces, has metal convex on the pad 102
Block 130, the metal coupling 130 on each semiconductor chip 101 connect with input port corresponding on the front of substrate 301
It connects；
Bottom filled layer 132 between the functional surfaces of the semiconductor chip 101 and the front face surface of substrate 301；
Coat the of 132 side surface of non-functional surface and sidewall surfaces and bottom filled layer of the semiconductor chip 101
One shielded layer 103, and the surface of the first screen layer 103 is in ellipsoid；
Secondary shielding layer 104 in the first screen layer 103；
The external contact structure 124 being connect with output port positioned at the back side of the substrate 301.
In one embodiment,
The first screen layer 103 is formed directly into the semiconductor chip by gluing process or screen printing technique
Non-functional surface and sidewall surfaces；The secondary shielding layer 104 passes through sputtering, selective electroplating technique, gluing process or web plate print
Dataller's skill is formed.The material of the first screen layer 103 is solder or conductive silver glue, and the material of the secondary shielding layer 104 is
Copper, tungsten, aluminium, solder or conductive silver glue.
In one embodiment, further includes: positioned at the intermediate materials of semiconductor chip 101 non-functional surface and sidewall surfaces
Layer, the intermediate layer of material have the surface of ellipsoid；Positioned at the first screen layer of the intermediate materials layer surface, described first
Shielded layer also has the surface of ellipsoid.
In another embodiment, the first screen layer 103 is magnetic field shielding layer, and the secondary shielding layer 104 is electricity
Field shielded layer；Or the first screen layer 103 is electric field shielding layer, and the secondary shielding layer 104 is magnetic field shielding layer.Institute
The material for stating electric field shielding layer is copper, tungsten, aluminium；The material of the magnetic field shielding layer be CoFeB alloy, CoFeTa, NiFe, Co,
The alloy of CoFe, CoPt or Ni, Co and Fe.
In one embodiment, Figure 18 is please referred to, also there is bottom shield layer on the functional surfaces of the semiconductor chip 101
114, the bottom shield layer 114 covers the entire functional surfaces of semiconductor chip 101, the surrounding of the bottom shield layer 114
Edge is flushed with the surrounding side wall of semiconductor chip 101, and several pads 102 run through bottom shield layer 114, pad 102 and bottom screen
It covers and is isolated between layer 114 by separation layer 111；The first screen layer 103 and the edge of bottom shield layer 114 connect
It connects.
The external contact structure 124 is soldered ball or the outer contacting structure includes metal column and is located on metal column
Soldered ball.
In one embodiment, further includes: the conductive contact structure in the substrate 301, the conductive contact structure
It is electrically connected with first screen layer.
The above is only a preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
Member, various improvements and modifications may be made without departing from the principle of the present invention, these improvements and modifications also should be regarded as
Protection scope of the present invention.
Claims (12)
1. a kind of forming method of encapsulating structure characterized by comprising
There is provided several semiconductor chips, each semiconductor chip includes functional surfaces and the non-functional surface opposite with functional surfaces, described
There are several pads on functional surfaces, be formed with metal coupling in the bond pad surface；
Substrate is provided, there are several line constructions in the substrate, the front of substrate has several input ports, the back side of substrate
With several output ports, the input port and output port are connected with corresponding line construction respectively；
By being inverted on substrate front side surface for several semiconductor chips, so that the metal of each semiconductor core on piece
Convex block is connected with input port corresponding on the front of substrate；
Bottom filled layer is formed between the functional surfaces of the semiconductor chip and the front face surface of substrate；
Form the first shielding of the non-functional surface for coating the semiconductor chip and sidewall surfaces and bottom filled layer side surface
Layer, and the surface of the first screen layer is in ellipsoid；
Secondary shielding layer is formed in the first screen layer；
Plastic packaging layer is formed on substrate in the secondary shielding layer and between semiconductor chip；
The external contact structure connecting with output port is formed at the back side of the substrate.
2. the forming method of encapsulating structure as described in claim 1, which is characterized in that the first screen layer passes through dispensing work
Skill or screen printing technique are formed directly into the non-functional surface and sidewall surfaces of the semiconductor chip；The secondary shielding layer is logical
Sputtering, selective electroplating technique, gluing process or screen printing technique is crossed to be formed.
3. the forming method of encapsulating structure as claimed in claim 2, which is characterized in that the material of the first screen layer is weldering
Material or conductive silver glue, the material of the secondary shielding layer are copper, tungsten, aluminium, solder or conductive silver glue.
4. the forming method of encapsulating structure as described in claim 1, which is characterized in that further include: in the semiconductor chip
The surface of non-functional surface and side wall forms intermediate layer of material, and the intermediate layer of material has the surface of ellipsoid；In intermediate materials
Layer surface forms first screen layer, and the first screen layer also has the surface of ellipsoid.
5. the forming method of encapsulating structure as described in claim 1 or 4, which is characterized in that the first screen layer is magnetic field
Shielded layer, and the secondary shielding layer is electric field shielding layer；Or the first screen layer is electric field shielding layer, and described second
Shielded layer is magnetic field shielding layer.
6. the forming method of encapsulating structure as claimed in claim 5, which is characterized in that the material of the electric field shielding layer is
Copper, tungsten, aluminium；The material of the magnetic field shielding layer be CoFeB alloy, CoFeTa, NiFe, Co, CoFe, CoPt or Ni, Co and
The alloy of Fe.
7. the forming method of encapsulating structure as described in claim 1, which is characterized in that on the functional surfaces of the semiconductor chip
Also there is bottom shield layer, the entire functional surfaces of bottom shield layer covering semiconductor chip, the four of the bottom shield layer
Circumferential edges are flushed with the surrounding side wall of semiconductor chip, and several pads run through bottom shield layer, between pad and bottom shield layer
It is isolated by separation layer；When forming the first screen layer, the edge of the first screen layer and bottom shield layer connects
It connects.
8. the forming method of encapsulating structure as claimed in claim 7, which is characterized in that partly the leading with bottom shielded layer
The forming process of body chip are as follows: wafer is provided, is formed with several semiconductor chips on the wafer, the semiconductor chip includes
Top layer dielectric layer and the top layer interconnection structure in top layer dielectric layer；Separation layer is formed in the top layer dielectric layer；Etching
The separation layer forms several first openings in the separation layer and surrounds the second opening of several first openings, and
Remaining separation layer is only located between the first opening and the second opening, and the first opening and the second opening are separated；Described
Filling metal material forms several pads in several first openings, and filling metal material forms bottom screen in second opening
Cover layer；Metal coupling is formed on the pad；After forming the metal coupling, the wafer is cut, is formed several discrete
Semiconductor chip with bottom shielded layer.
9. the forming method of encapsulating structure as claimed in claim 8, which is characterized in that several pads and bottom shield layer
It is formed by same technique, comprising steps of forming gold in the first opening and the second opening and on the surface of separation layer
Belong to material layer；Planarization removal is higher than the metal material layer of the insulation surface, forms pad, In in first opening
Bottom shield layer is formed in second opening.
10. the forming method of encapsulating structure as described in claim 1, which is characterized in that the external contact structure is soldered ball,
Or the outer contacting structure includes metal column and the soldered ball on metal column.
11. the forming method of encapsulating structure as described in claim 1, which is characterized in that further include: in the substrate
Conductive contact structure, the conductive contact structure are electrically connected with first screen layer.
12. the forming method of encapsulating structure as described in claim 1, which is characterized in that after the formation external contact structure,
Further include: the substrate is cut, several isolated encapsulating structures are formed.
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|---|---|---|---|
| CN201910681470.1A CN110534442B (en) | 2019-07-26 | 2019-07-26 | Forming method of packaging structure |
| US17/629,549 US20220270982A1 (en) | 2019-07-26 | 2020-07-17 | Packaging structure and fabrication method thereof |
| PCT/CN2020/102758 WO2021017896A1 (en) | 2019-07-26 | 2020-07-17 | Packaging structure and fabrication method thereof |
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| WO2021017896A1 (en) * | 2019-07-26 | 2021-02-04 | Tongfu Microelectronics Co., Ltd. | Packaging structure and fabrication method thereof |
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