CN110491832A - The method and apparatus of through hole for rear production through-hole - Google Patents

The method and apparatus of through hole for rear production through-hole Download PDF

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Publication number
CN110491832A
CN110491832A CN201910725136.1A CN201910725136A CN110491832A CN 110491832 A CN110491832 A CN 110491832A CN 201910725136 A CN201910725136 A CN 201910725136A CN 110491832 A CN110491832 A CN 110491832A
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China
Prior art keywords
wafer
hole
oxide
carrier wafer
active device
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陈思莹
陈保同
杨敦年
刘人诚
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication of CN110491832A publication Critical patent/CN110491832A/en
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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Abstract

The present invention provides the methods for the through hole that through-hole is made after being used to form.A kind of method includes providing the active device wafer with front and the opposite back side, which includes the conductive interconnection material being arranged in the dielectric layer；The carrier wafer with the through-hole filled with oxide is provided, which extends to the second surface of carrier wafer from the first surface of carrier wafer；By the second surface of the positive engagement of active device wafer to carrier wafer；The oxide in the through hole of carrier wafer is etched to form oxide through hole；And conductive material is deposited in oxide through hole to form conductor, which extends to active device wafer and is in electrical contact with conductive interconnection material.A kind of device includes the carrier wafer with oxide through hole, which extends through carrier wafer and reach the active device wafer engaged with carrier wafer.The present invention also provides the devices of the through hole for rear production through-hole.

Description

The method and apparatus of through hole for rear production through-hole
The application be submitted on 03 28th, 2013 application No. is the entitled of 201310105417.X " to make after being used for The divisional application of the Chinese invention patent application of the method and apparatus of the through hole of through-hole ".
The cross reference of related application
This application involves and require to submit on April 18th, 2012 entitled " for BSI imaging sensor and most terminate Manufacturing method (the Fabrication Method of Via-last TOV for BSI Image of the rear production through-hole TOV of structure Sensor and Resulting Structures) " the 61/625th, No. 987 U.S. Provisional Patent Application priority, Full content is hereby expressly incorporated by reference.
Technical field
This invention relates generally to technical field of semiconductors, more specifically for, be related to semiconductor devices and its manufacturer Method.
Background technique
In the work for utilizing semiconductor crystal wafer to form traditional through hole (TV) (through-via) for three-dimensional (3D) arrangement In skill, low-temperature oxidation is used so that TSV to be isolated with wafer with thin oxide layer liner silicon through hole (TSV).Due to typical case The high aspect ratio of TSV, the stress of the trench corner at the bottom of the through-hole in wafer will lead to oxide fracture, and when with When forming metal afterwards, it is possible to create extruding metal (such as copper or Cu squeeze).These fracture and extrusion device to can reliability and Performance has an adverse effect.
In the specific application of TV, during manufacturing back-illuminated type (BSI) cmos image sensor (CIS) device, carry Tool wafer, which can be, engages the wafer engaged with active device wafer using wafer.For example, Silicon Wafer may be active device crystalline substance Justify and can have many integrated circuits formed therein, wherein integrated circuit is CIS device, each integrated circuit With photodiode array.Several gold can be formed in the dielectric materials layer for the upper front for being formed in active device wafer Categoryization layer.
On the opposite back side of active device wafer, for back-illuminated type (BSI) imaging sensor, light projection is allowed to arrive On the photodiode of BSI CIS device, and color filter array (CFA) material can be formed in the back side of active device wafer It top and is aligned with photodiode to form colour element.Lenticule (ML) material can be arranged in above CFA material with Further increase light-receiving.Glassy layer can be bonded to the back side of active device wafer to protect CIS device.For CFA, ML Material and bond material are especially sensitive to high-temperature technology.
In order to complete these BSI CIS devices, in wafer scale technique, such as the carrier wafer of silicon carrier wafer can be connect It closes in the top of active device wafer.In conventional methods where, TV can be etched into and pass through semiconductor carrier wafer, and creation is prolonged Extend through the via openings of carrier wafer.These TV may be extended to expose highest metalization layer and be formed in active device wafer A part of top.Copper conductive material or other conductors can be deposited in through hole, and the creation of these conductors extends through The power path of carrier wafer.
The relevant heat and mechanical stress of silicon etch process and generation that TSV is formed in carrier wafer may cause The fracture of the upper dielectric layer of source device wafers.Fracture can be formed in liner oxide layer in through-holes.In addition, in copper deposition In technical process, copper extruding will form in these fractures.These used techniques can during forming TSV in carrier wafer It can need high-temperature technology.High temperature used in these techniques can further create the device in active device wafer and use its The undesirable thermal stress of his material.
Summary of the invention
In order to solve the existing defects in the prior art, according to an aspect of the present invention, it provides a method, wraps It includes: forming at least one through-hole in carrier wafer；At least one described through-hole is filled with oxide；The carrier wafer is pacified It is filled to the second wafer；Across the oxide etching through hole for filling at least one through-hole, to form oxide perforation Hole；And with the conductor filled oxide through hole.
In this method, the oxide is high-density plasma (HDP) oxide.
This method further includes that the carrier wafer is thinned.
In this method, before reduction steps, at least one described through-hole extends from the first surface of the carrier wafer The second surface of the carrier wafer is not extended into the carrier wafer but.
In this method, second wafer includes imaging sensor.
In this method, second wafer includes conductive interconnection part, and the oxide through hole further extend with The exposure conductive interconnection part.
In this method, the conductor filled oxide through hole is simultaneously electrically connected with the conductive interconnection part.
In this method, the conductor includes copper.
This method further includes the external terminal to be formed above the carrier wafer and with conductor electrical contact.
In this method, the conductor includes copper.
According to another aspect of the present invention, it provides a method, comprising: providing has having for the positive and opposite back side Source device wafers, the front include the conductive interconnection material of setting in the dielectric layer；There is provided has passing through filled with oxide The carrier wafer of through-hole, the through hole extend to the second table of the carrier wafer from the first surface of the carrier wafer Face；The second surface of the carrier wafer is bonded to the front of the active device wafer；The carrier is thinned The first surface of wafer；The oxide in the through hole is etched to form the first surface from the carrier wafer The oxide through hole in the dielectric layer of the active device wafer is extended to, to lead described in the exposure dielectric layer A part of interconnection materials；And in the oxide through hole deposited conductor material to be formed and the conductive interconnection material Expect the conductor of electrical contact.
In this method, the active device wafer further includes cmos image sensor.
In this method, the cmos image sensor is back-illuminated cmos image sensors.
In this method, depositing the conductor material further comprises deposition copper.
This method further include: the conductor material is deposited on the second surface of the carrier wafer；Patterning institute The conductor material on the second surface of carrier wafer is stated to be formed and the conductor in the oxide through hole The conducting wire of material connection；And form the joint outer part connecting with the conducting wire.
In this method, forming the joint outer part includes: to be formed on the second surface of the carrier wafer Side and the passivating material for covering the conducting wire；Patterning opening is in the passivating material with conducting wire described in expose portion；And The joint outer part is formed in said opening.
In this method, forming the joint outer part includes being formed selected from substantially by soldered ball, cylinder, column, protrusion, weldering Expect the joint outer part in group composed by convex block, bonding wire.
According to another aspect of the invention, a kind of device is provided, comprising: active device wafer, having includes multiple electricity The wafer of device and the conductive interconnection part being arranged on front；And carrier wafer, it is arranged on the active device wafer The upper front and the wafer are bonded to the active device wafer, the carrier wafer further include: through hole extends through It crosses the carrier wafer and there is the oxide material formed in the through hole；Oxide through hole extends through institute The oxide material in through hole is stated, the oxide through hole extends to lead described in the exposure active device wafer A part of electrical interconnection；Conductive material is deposited in the oxide through hole, the conductive material and the active device The expose portion of the conductive interconnection part of wafer is in electrical contact；And joint outer part, it is formed in the top of the carrier wafer And it is electrically connected with the conductive material.
In the apparatus, the conductive material includes copper.
In the apparatus, the active device wafer includes back-illuminated cmos image sensors.
Detailed description of the invention
In order to which the present invention and its advantage is more fully understood, it is described below now by what is carried out in conjunction with attached drawing as ginseng It examines, in which:
Fig. 1 shown with sectional view be the BSI CIS exemplary means used by embodiment active device wafer；
Fig. 2 is with cross sectional view source in the embodiment of the carrier wafer in middle process stage；
Fig. 3 shows the carrier wafer of Fig. 2 after other techniques with sectional view.
Fig. 4 shows the carrier wafer of Fig. 3 after the cmp process with sectional view；
Fig. 5 shows the carrier wafer of Fig. 4 after further oxide deposition with sectional view；
Fig. 6 has provided carrier wafer with cross sectional view and has engaged with active device wafer to form exemplary bonded wafers structure (such as in Fig. 5) embodiment,；
Fig. 7 shows the structure of Fig. 6 for showing carrier wafer after wafer reduction process with sectional view；
Fig. 8 shows the bonded wafers structure of Fig. 7 after via process with sectional view；
Fig. 9 shows the bonded wafers structure of Fig. 8 after other techniques with sectional view；
Figure 10 shows the bonded wafers structure of the completion of embodiment with sectional view；
Figure 11 shows the bonded wafers structure of Fig. 8 after other techniques with sectional view to show alternative embodiment；With And
Figure 12 shows the bonded wafers structure of Figure 11 after other techniques of alternative embodiment with sectional view.
Unless otherwise stated, the corresponding label and symbol in different attached drawings are often referred to corresponding component.Draw attached drawing To be clearly shown the related fields of embodiment without drawn to scale.
Specific embodiment
In the following, the manufacture and use of exemplary embodiment of the present are discussed in detail.It should be appreciated, however, that the present invention provides Many applicable concepts that can be realized in various specific environments.The specific embodiment discussed only show manufacture and Use concrete mode of the invention, rather than the limitation present invention and scope of the appended claims.
As shown in the picture, exemplary embodiment is provided for improving such as interconnection piece of through hole (through vias) The technique of reliability, through hole include silicon through hole or substrate through hole, the through-hole for extending through intermediary layer etc., all these Through-hole is commonly referred to as TV herein.In being particularly suitable for the application that embodiment uses, BSI CIS device is formed in In active device wafer.However, the 3D packaging part using bonded wafers is increasing, and the TV of embodiment and method are suitable for Many applications have carrier wafer or the carrier substrate of through hole in such applications to extend to the side of another wafer or substrate Formula is formed.As provided further below, the embodiment of elaboration is including the use of high density plasma oxide (HDP Ox) Technique forms through-hole in carrier wafer.The bottom of grinding or polishing step exposure through hole and HDP Ox.Later in HDP Ox Middle formation via openings.Different from existing method silicon through hole (TSV), the through hole formed here is oxide through hole (TOV).It can use low temperature etching processes and form TOV, therefore generate lower thermal stress.Therefore, traditional TV method is eliminated The oxide fracture of middle discovery and extruding metal phenomenon, to provide the reliability of the raising of the device of completion.
Advantageous refinements using the embodiment of the elaboration may include: that through hole etching is simpler；To in active device wafer The thermal shock of the material used is smaller, for example, the heat in the example of BSI CIS application, on CFA/ML material and grafting material Impact becomes smaller；And using the embodiment but also through-hole side wall and the risk of the oxide of corner fracture reduce.
Fig. 1 shows active device wafer 11 with sectional view.Although will have for the example of illustrated embodiments used herein Source device wafers 11 are described as BSI CIS device wafers, but these embodiments provide advantageous through-hole and 3D sets of wafers The perforation of part, these through holes and 3D wafer assembly suitable for the wafer and substrate of wherein carrier wafer and other device stacks Hole, without these embodiments are defined in any specific application.
Referring now to Figure 1, showing BSI CIS device 11.Provide substrate 13, substrate 13 can be Silicon Wafer or other Semiconductor crystal wafer.The array of photodiode 23 is formed in a part of substrate 13.Peripheral circuit may include such as 21 Hes 19 MOS transistor, for example, such as 21 and 19 MOS transistor can be formed in 21 He of P-MOS transistor in dopant well N-MOS transistor 19.Show the top of the transistor being formed in doped well region 21 and 19 and photodiode 23 Grid conductor 29, the grid conductor 29 can be polysilicon, the polysilicon of doping or other grids comprising metal gate material Material and there is the side wall insulator (not shown) that is formed thereon.It is well known that the array of photodiode 23 can wrap It includes a certain access transistor (for simplicity, being not shown), charge transfer transistor, reading in such as 3T or 4T photodiode trap Selection transistor and reset transistor.Show can be the area of isolation 33 of shallow trench isolation part (STI) or LOCOS separator with Being isolated between photodiode 23 and transistor well 21 and 19 is provided, transistor well 21 and 19 is also electrically isolated from each other.
Dielectric structure 25 is located at the upper front of wafer 13, and dielectric structure 25 may include multiple interlayers and inter-metal dielectric Layer.These layers include so-called BEOL (later process) layer of active device wafer.BEOL layer includes conduction well known in the art Interconnection piece.
Material in dielectric structure 25 may include one or more dielectrics, such as silica, nitride, oxidation Object, nitrogen oxides and high-k dielectric and low-k dielectric.The conductor of such as top conductors 31 is formed in dielectric structure 25 In layer and it is divided into multiple metal layers of the metal layers such as metal -1, metal -2.These metal layers pass through dielectric structure 25 Interior dielectric layer is electrically isolated and can be formed for example, by technique below: forming ditch using the dielectric material being patterned Slot is filled groove with the conductive material of such as copper or aluminium copper using electrochemistry spraying plating (ECP), is then gone using CMP planarization Except the excess stock at each metal layer；The technique is repeated to form various metalization layers.Dual damascene can be used and singly inlay Technique forms conductor in the dielectric layer.
CFA material 35 is formed in the back side of wafer 13.By only allowing feux rouges, green light or blue light to pass through two pole of photoelectricity Corresponding photodiode in pipe 23, the CFA with photodiode are created in the photodiode array of BSI sensor 11 Colour picture element (pixel).Lenticule (ML) device 37 collects initial light and initial light is focused on two pole CFA and photoelectricity Guan Shang.For example, interim grafting material 15 is arranged above ML device.Glass substrate 17 is bonded on the upper back of wafer 13, with It protects imaging sensor photodiode and the glass substrate 17 completes the back portion of BSI CIS device 11.
Complete active device wafer 13 and formed CIS sensor 11 after, need further processing step formed with The electrical connection of the sensor.
Although should be noted that BSI CIS sensor 11 is used as the particular instance of illustrated embodiments, these embodiments are mentioned For the 3D wafer connected structure that can be used by any active device wafer type.For example, digital signal processor including easily The property lost and the memory device of nonvolatile memory, analog processor, RF circuit, resistor, inductor and capacitor can be used In active device wafer, it is assumed that be connected to active device wafer outside using wafer engagement and through hole in 3D package arrangement Portion's connector, any kind of device can form in active device wafer and utilize these embodiments.
Fig. 2 is with cross sectional view source in the embodiment of the carrier wafer 41 in the intermediate stage of technique.In embodiment, it is carrying Tool wafer 41 is bonded to before the active device wafer 11 of Fig. 1, and the carrier wafer 41 is prepared in a series of preceding working procedures.Scheming In 2, photoresist or hard mask layer 43 are deposited on the top of wafer 45.Layer 43 is patterned using photoetching and etching step, With through-hole (as described below) that is formed with to be formed in wafer 45 it is corresponding opening 47.Wafer 45 can be semiconductor Wafer, and can be Silicon Wafer, but germanium, indium, GaAs and the other materials for semiconductor crystal wafer also can be used.Make For alternative embodiment, other carrier materials (such as glass and ceramics) used in wafer engagement can be used for wafer 45.
Fig. 3 shows the carrier wafer 41 of Fig. 2 after some other processing steps with sectional view.In the section from Fig. 2 During the section for being transitioned into Fig. 3, by photoresist layer 43 (referring to fig. 2) be used as etching mask, using such as dry ecthing (including Plasma etching, RIE etch etc.) etch process extend to through-hole 40 in wafer 45.Then photoresist layer 43 is removed.Example Such as, high-density plasma (HDP) process deposits filling through-hole 40 can be used and cover the oxide on the surface of wafer 45 42.It can use with SiH4(silane) as precursor gases plasma reactant and using provide deposition and atomic oxygen come Form HDP oxide.When compared with other oxides deposition, HDP oxide is dense and in relatively low temperature Degree is lower to be formed.However, these embodiments are not limited to use in the HDP oxide of oxide skin(coating) 42；It as non-limiting examples, can be with The other materials used includes HARP (high aspect ratio technique for CVD), SACVD, BPSG oxide.
Fig. 4 shows the carrier wafer shown in Fig. 3 41 after some other processing steps with sectional view.In order to from Fig. 3 Intermediate stage be transitioned into the stage shown in Fig. 4, other oxide removals using chemically mechanical polishing (CMP) or such as etched Technique removes partial oxide 42 from the upper surface of wafer 45, if can also further planarize the upper of wafer 45 using CMP Surface.Then, through-hole 40 keeps the oxide 42 of filling.The thickness t1 of carrier wafer can be in about 400 to about 800 microns of model In enclosing.In unrestricted illustrative examples, carrier wafer 41 can have about 750 microns of thickness t1 at this stage.
Fig. 5 shows the carrier wafer shown in Fig. 4 41 after some other processing steps with sectional view.In order to from Fig. 4 Intermediate stage be transitioned into the stage shown in Fig. 5, use such as CVD, PECVD or PVD deposition oxide deposition or thermal oxide Object, which is grown in above the upper surface of wafer 45, forms oxide skin(coating) 44.For example, the thickness of layer 44 can be at 0.1 micron to 1 micron In the range of.As described below, when carrier wafer 41 can oxide skin(coating) molecular bond on the surface with active device wafer When (Fig. 5 is not shown), layer 44 is used in subsequent oxide and oxide wafer joint technology.Oxide skin(coating) 44 has exposure Surface, the surface relatively flat of the exposure and smooth and compatible with wafer bond techniques.
Fig. 6 is shown after above-mentioned preparation process completes with another sectional view and has been carried out oxide and oxide wafer The carrier wafer 41 of Fig. 5 after joint technology.Compared with Fig. 5, the load rotated downward by exposed surface is now illustrated Has wafer 41.For simplicity, showing the section of Fig. 6, still, such as carrier wafer can also be shown as and be located at active device wafer Lower section.Carrier wafer 41 is engaged with active device wafer 11 (referring to Fig. 1) at present.It is engaged using oxide with oxide wafer Technique is formed so that the oxide skin(coating) 44 of carrier wafer 41 is bonded to the upper front in the wafer 13 of active device wafer 11 Oxide skin(coating) 46.Oxide skin(coating) 46 is also possible to thermally grown oxide or can be in the upper front of active device wafer 11 By CVD, PECVD, the PVD deposition oxide skin(coating) 46, and the thickness of oxide skin(coating) 46 can be at 1 micron to about 2 microns In range.In order to form wafer engagement, the surface of oxide skin(coating) 44 and 46 can be activated for example, by plasma process, Or chemical cleaning is carried out, then placed in a manner of physical contact.Wafer can occur under room temperature or increased temperature to connect It closes, and wafer engagement can be implemented in a vacuum chamber.It in one embodiment, can be in wafer bonding process Use temperature in the range of about 150 DEG C to about 450 DEG C.
During by the installation of carrier wafer 41 to active device wafer 11, in through-hole 40 and active device wafer 11 The specific part of top metallization part 31 is aligned.Through-hole 40 can be used to form vertical in subsequent step (described below) Straight oxide through hole, the oxide through hole establish upper surface to the part of active device wafer 11 gold of carrier wafer 41 The electrical connection of categoryization layer.
Fig. 7 shows carrier wafer shown in fig. 6 41 and the active device wafer after other processing steps with sectional view 11.In order to be transitioned into operation stage shown in Fig. 7 from the intermediate stage of Fig. 6, the surface (being currently upper surface) of wafer 45 is held To expose through-hole 40, the grinding wafer or wafer thinning operation may include machinery wafer for row grinding wafer or wafer thinning operation Grinding, silicon etching, the combination of CMP or these techniques, to form the through hole 40 for extending through wafer 45.Through hole 40 is kept The HDP oxidation material 42 of filling.
Fig. 8 shows carrier wafer 41 and active device wafer 11 after other techniques.Photoresist or hard mask layer 53 It is formed in the top of the exposed surface of carrier wafer 41.It is formed in photoresist or hard mask layer 53 using photoetching and etch process Opening 55.It is used as etching mask using opening 55 and by photoresist layer 53, oxide through hole (TOV) 51 is formed in HDP In oxide 42 and oxide skin(coating) 44 and 46 is extended through to expose the metallization structure 31 in active device wafer 11 most A part of top layer.
The etch process for being used to form TOV 51 is oxide etching process and can implement the erosion by RIE etch Carving technology, the narrow through-hole which is particluarly suitable for being formed that extend into oxide skin(coating) 44,46 in HDP oxide 42 are opened The high aspect ratio and anisotropic properties of mouth.Since the etching is oxide etching, it is possible to active device wafer 11 In material (e.g., including CFA and ML material) there is relatively low heat affecting at a temperature of implement the etching.In addition, TOV 51 are etched through HDP oxide 42 and the opening extends into another oxide skin(coating) 44, subsequently into oxide skin(coating) 46, so that Entire etch process is oxide etching.In contrast, in the conventional method, comparable etching is entered across carrier wafer The silicon of following oxide skin(coating) etches, to generate additional thermal stress to oxide.
Due to forming through-hole 51 after wafer joint technology, which is considered " making through-hole afterwards " side Method.
By comparing embodiment described herein method and existing silicon through hole etching and thermal oxide lining formed, this The use of a little embodiments provides many advantages.In existing method due to caused by formation " turning " stress problem have in use There is no because in these embodiments, HDP oxide is used for conductor formed in through-hole when the embodiment of TOV It is isolated with carrier wafer, and in the conventional method, it is heavy to implement liner oxidation in high aspect ratio through-hole as low thermal oxidation object Product, so as to cause the region being broken.By utilizing these embodiments, HDP oxide forms separation layer, therefore no longer implements The liner oxidation step.Compared with the existing method the problem of, using these embodiments and TOV eliminate hot liner oxide and its Bring integrity problem.
Fig. 9 shows the carrier wafer 41 and active device wafer 11 of Fig. 8 after other processing steps with sectional view.In order to It is transitioned into Fig. 9 from Fig. 8, removes photoresist layer 53, and side wall and bottom using electrochemistry spraying plating (ECP) technique in through-hole 51 Interior formation copper (Cu) redistributing layer (RDL) 57, copper (Cu) redistributing layer (RDL) 57 extend on the exposed surface of wafer 45. For example, RDL 57 can be one of copper or copper alloy, and may include titanium nitride, tantalum nitride etc. barrier layer and Adhesion layer is to prevent copper ion from spreading.It would be recognized by those skilled in the art that can be in the copper or other conductors of filling through-hole 51 Before or after 57 form, lining, barrier layer, seed layer etc. are formed in through-holes.
RDL 57 is isolated by HDP oxide 42 with wafer 45 in through-hole 51, therefore it is heavy not need additional insulator Product is to keep this isolation.RDL 57 is extended in through-hole 51 and is extended to the sudden and violent of the metalization layer 31 in active device wafer 11 Reveal part, and formed from the upper surface of wafer 45, passes through oxide through hole 51 to the electrical connector of metalization layer 31.RDL 57 are again formed as on the surface of wafer 45, and as shown in figure 9, RDL 57 can be patterned to the upper table in wafer 45 A plurality of conducting wire is formed on face.Therefore, RDL 57 provides the outer of the metalization layer 31 for being established in active device wafer 11 The conductor part of portion's electrical connector.
Figure 10 shows the carrier wafer 41 and active device wafer of Fig. 9 after other processing steps with another sectional view 11.In fig. 10 it is shown that being deposited on RDL 57 in (such as silicon nitride) layer of passivating material 61 or another layer of passivation material TOV 51 after side.Passivating material 61 covers the RDL 57 in through-hole and is located above the upper surface of wafer 45.Such as 63 Opening be formed in passivating material 61, then in the opening formed terminal 65.Terminal 65 can be the end ball grid array (BGA) Son, and terminal 65 forms the external terminal with more partial electrical contacts of RD L57.Metallization of the BGA terminal 65 in through-hole 51 It is electrically connected by RDL 57 with active device wafer 11 at layer 31.BGA terminal 65 can be formed and be used as soldered ball or solder projection simultaneously And BGA terminal 65 can be deposited on RDL layer 57, be then subjected to such as thermal reflux to complete BGA terminal 65.
In the exemplary embodiment technique shown in Fig. 9 and 10, formed RDL57 and BGA ball 65 without CMP process and Mosaic technology, CMP process and mosaic technology are commonly used in the copper or other conductors on patterning through-hole.
Now, Figure 11 and 12 shows optional specific embodiment example.In Figure 11, shown with sectional view in other works The structure of Fig. 9 after skill step.The barrier layer of such as TaN (tantalum nitride) is formed in a manner of liner through-hole 51.It shows and fills out The through-hole 51 of conductor filled with such as copper or alloy, the conductor are formed by ECP technique, carry out CMP process then to remove More burden (overburden) and the surface for planarizing through-hole 51.Therefore, which is similar to known in through-hole Form the mosaic technology of copper.
Figure 12 shows the structure of Figure 11 after other processing steps.In fig. 12 it is shown that after the cmp process Through-hole 51 filled with copper.RDL layer 57 is formed to above substrate by conductor and forms conducting wire.For example, the layer can be and pass through light It carves and etch patterning is formed by Al/Cu alloy, to form the conducting wire connecting with through-hole.Passivation layer 61 is formed in RDL layer 57 Top, on conducting wire formed be open and formed BGA ball 65 with complete be used for active device wafer 11 joint outer part.
The BGA terminal 65 of Figure 10 and 12 can by based on lead solder or lead-free solder formed, and for example, BGA terminal 65 can be by forming comprising one of silver, tin, copper or a variety of solders.BGA terminal forms conductive terminal and can not be Spherical, such as column (pillars), cylinder (columns), column (studs), column can be used and stack (stacks of Studs other shapes) form alternative embodiment.BGA terminal 65 may include protective coating, for example, nickel, gold and palladium and The alloy of such as ENIG, ENEPIG.In an alternative embodiment, ball bar can be replaced with column, column, bonding wire, convex block Array terminal 65 and these refill-units can be copper, gold or other conductive materials comprising solder.Shape can be cylinder, column Shape object, wire bonding convex block or wirebond posts are provided for module or integrated circuit to be installed leading to another plate or substrate Any shape of electric terminal may be used as terminal.In some embodiments, for example, the stacking of wire bonding cylindricality convex block and copper or Golden conducting wire is used together the alternative embodiment as BGA ball 65.
It is described above to implement in wafer scale technique with Fig. 2 to technique shown in Fig. 10, that is to say, that carrier is brilliant Circle 41 can be engaged with active device wafer 11 as shown in Figure 7, and can implement to include forming TOV and formation with wafer scale The later step of conductive RDL layer, passivation layer and ball grid array terminals.Optionally, after wafer engagement step, pass through cutting Or device isolation can be standalone module to form integrated circuit modules by sawing operation, it is then possible to complete independent integrated Circuit module.Due to the economic consideration of scale and benefit, wafer scale technique is used more and more, however, the embodiments herein It is not limited to wafer scale process example.
As use embodiment described herein the advantages of, it should it is believed that, for heat budget and mechanical stress, active When device wafers are engaged with the carrier wafer, technique needed for passing through HDP oxide (or similar oxide) etching TOV Condition stress compared with heat condition needed for the etching in existing method is smaller, such as the silicon substrate etching of carrier wafer.In addition, , it is believed that can also be penetrated through by eliminating to be formed in the conventional method in the TOV of embodiment around the HDP oxide of conductor The oxide fracture of hole (through-vias) Shi Faxian and conductor squeeze phenomenon to improve reliability.
In the exemplary embodiment, a kind of method, which is included in carrier wafer, forms at least one through-hole；It is filled out with oxide Fill at least one through-hole；The carrier wafer is installed to the second wafer；Across the oxide erosion for filling at least one through-hole Through-hole is carved to form oxide through hole；And with the conductor filled oxide through hole.In yet another embodiment, above-mentioned side Oxide in method is high-density plasma (HDP) oxide.In another embodiment, this method further includes that carrier is thinned Wafer.In yet another embodiment, in the above-mentioned methods, before reduction steps, at least one through-hole is from carrier wafer First surface extends to the second surface in carrier wafer but not extending to carrier wafer.In another embodiment, upper It states in method, the second wafer includes imaging sensor.In yet another embodiment, in the above-mentioned methods, the second wafer includes leading Electrical interconnection and oxide through hole further extend to expose conductive interconnection part.In yet another embodiment, in above-mentioned side In method, conductor filled oxide through hole and it is electrically connected with conductive interconnection part.Conductor is copper in yet other embodiments,.In In another embodiment, implement the above method and the above method further include to be formed it is positioned at carrier wafer above and electric with conductor The external terminal of contact.In yet another embodiment, in the above-mentioned methods, conductor is copper.
In further embodiments, a kind of method includes providing the active device wafer with front and the opposite back side, The front includes the conductive interconnection material of setting in the dielectric layer；The carrier wafer for having the through-hole filled with oxide is provided, The through-hole extends to the second surface of carrier wafer from the first surface of carrier wafer；It engages the second surface of carrier wafer and has The front of source device wafers；For oxide in etching vias to form oxide through hole, the oxide through hole is brilliant from carrier Round first surface extends in the dielectric layer of active device wafer to one of the conductive interconnection material in exposed dielectric layer Point；And conductive material being deposited in oxide through hole to form conductor, the conductor and conductive interconnection material are in electrical contact.
In yet another embodiment, in the above-mentioned methods, active device wafer further includes cmos image sensor.Another In a embodiment, the above method is back side illumination image sensor including wherein cmos image sensor.In yet another embodiment, In the above-mentioned methods, this method includes depositing conductive material on the second surface of carrier wafer；Pattern the of carrier wafer Conductive material on two surfaces is to form the conducting wire connecting with the conductive material in oxide through hole；And it is formed and is connected with conducting wire The joint outer part connect.
In yet another embodiment, forming joint outer part in the above-mentioned methods includes forming second positioned at carrier wafer Surface and the passivating material for covering conducting wire；Patterning opening is in passivating material to expose portion conducting wire；And it is opening Joint outer part is formed in mouthful.In yet another embodiment, the above method further includes deposition copper including wherein deposition conductive material. In yet another embodiment, in the above-mentioned methods, this method includes forming joint outer part, and forming joint outer part includes being formed Joint outer part selected from the substantially group as composed by soldered ball, cylinder, column, column, solder projection, bonding wire.
In another embodiment, a kind of device includes active device wafer, and it includes multiple which, which has, The wafer of electrical part and the conductive interconnection part being arranged on front；And carrier wafer, the carrier wafer are arranged in active device The upper front of the wafer and wafer is engaged with active device wafer, the carrier wafer further include: extend through carrier wafer And the through-hole with the oxide material formed in through-hole；Extend through the oxide perforation of the oxide material in through-hole Hole, the oxide through hole extend to expose a part of the conductive interconnection part of active device wafer；It is deposited on oxide perforation The expose portion of the conductive interconnection part of conductive material in hole, the conductive material and active device wafer is in electrical contact；And it is formed Top in carrier wafer and the joint outer part that is electrically connected with conductive material.
In yet another embodiment, in above-mentioned apparatus, conductive material is copper.In another embodiment, in above-mentioned dress In setting, active device wafer includes back-illuminated cmos image sensors.
Although describing the present invention about exemplary embodiment, this explanation should not be construed in a limiting sense Book.On the basis of with reference to this specification, the various change of these exemplary embodiments and combination and of the invention other Embodiment is obvious for those skilled in the art.

Claims (20)

1. a kind of method for manufacturing semiconductor device, comprising:
At least one through-hole is formed in carrier wafer, wherein the carrier wafer includes the first side and second relative to each other Side, and the through-hole includes the first end and second end for being located at first side and described second side；
At least one described through-hole is filled with oxide；
The carrier wafer is installed to the second wafer, so that second side of the carrier wafer engages second wafer；
Across the oxide etching through hole for filling at least one through-hole, to form oxide through hole, wherein institute Stating oxide through hole includes the third end being overlapped with the first end and the 4th end in second wafer, and described The width of one end is of same size with the third end, and the width of the second end is greater than the first end, the third The width at end and the 4th end；And
With the conductor filled oxide through hole.
2. according to the method described in claim 1, wherein, the oxide is high-density plasma (HDP) oxide.
3. according to the method described in claim 1, further including that the carrier wafer is thinned.
4. according to the method described in claim 3, before reduction steps, at least one described through-hole is from the carrier wafer First surface extends to the second surface for not extending in the carrier wafer but the carrier wafer.
5. according to the method described in claim 1, wherein, second wafer includes imaging sensor.
6. according to the method described in claim 1, wherein, second wafer includes conductive interconnection part, and the wherein oxygen Compound through hole further extends with the exposure conductive interconnection part.
7. according to the method described in claim 6, wherein, the conductor filled oxide through hole is simultaneously mutual with the conduction Even part electrical connection.
8. according to the method described in claim 7, wherein, the conductor includes copper.
9. according to the method described in claim 7, further including being formed above the carrier wafer and being connect with the conductor electricity The external terminal of touching.
10. according to the method described in claim 1, wherein, the conductor includes copper.
11. a kind of method for manufacturing semiconductor device, comprising:
The active device wafer with the positive and opposite back side is provided, the front includes that the conduction of setting in the dielectric layer is mutual Even material；
The carrier wafer for having the through hole filled with oxide, first surface of the through hole from the carrier wafer are provided The second surface of the carrier wafer is extended to, the through hole includes being located at the first surface and the second surface First end and second end；
The second surface of the carrier wafer is bonded to the front of the active device wafer；
The first surface of the carrier wafer is thinned；
It etches the oxide in the through hole and is extended to the first surface for being formed from the carrier wafer and is described active Oxide through hole in the dielectric layer of device wafers, with one of the conductive interconnection material in the exposure dielectric layer Part, wherein the oxide through hole include the third end being overlapped with the first end and be located at the active device wafer In the 4th end, the width of the first end is of same size with the third end, and the width of the second end be greater than institute State the width of first end, the third end and the 4th end；And
Deposited conductor material is in the oxide through hole to form the conductor with conductive interconnection material electrical contact.
12. according to the method for claim 11, wherein the active device wafer further includes cmos image sensor.
13. according to the method for claim 12, wherein the cmos image sensor is back-illuminated type cmos image sensing Device.
14. according to the method for claim 11, wherein depositing the conductor material further comprises deposition copper.
15. according to the method for claim 11, further includes:
The conductor material is deposited on the second surface of the carrier wafer；
The conductor material on the second surface of the carrier wafer is patterned to be formed and the oxide through hole In the conductor material connection conducting wire；And
Form the joint outer part connecting with the conducting wire.
16. according to the method for claim 15, wherein forming the joint outer part includes:
Form above the second surface for being located at the carrier wafer and cover the passivating material of the conducting wire；
Patterning opening is in the passivating material with conducting wire described in expose portion；And
The joint outer part is formed in said opening.
17. according to the method for claim 16, wherein forming the joint outer part includes being formed selected from substantially by welding Ball, cylinder, column, protrusion, solder projection, the joint outer part in group composed by bonding wire.
18. a kind of semiconductor device, comprising:
Active device wafer, the conductive interconnection part that there is the wafer including multiple electrical parts and be arranged on front；And
Carrier wafer, is arranged on the upper front of the active device wafer and the wafer is bonded to the active device Part wafer, wherein the carrier wafer includes the first side and second side relative to each other, and described second side and the front Engagement, the carrier wafer further include:
Through hole extends through the carrier wafer and has the oxide material formed in the through hole, described to pass through Through-hole includes the first end and second end for being located at first side and described second side；
Oxide through hole, extends through the oxide material in the through hole, the oxide through hole extend with A part of the conductive interconnection part of the exposure active device wafer, wherein the oxide through hole include with it is described The third end and the 4th end in the active device wafer that first end is overlapped, the width of the first end and the third That holds is of same size, and the width of the second end is greater than the width of the first end, the third end and the 4th end；
Conductive material is deposited in the oxide through hole, and the conductive material is led with the described of the active device wafer The expose portion of electrical interconnection is in electrical contact；And
Joint outer part is formed in the top of the carrier wafer and is electrically connected with the conductive material.
19. semiconductor device according to claim 18, wherein the conductive material includes copper.
20. semiconductor device according to claim 18, wherein the active device wafer includes back-illuminated type cmos image Sensor.
CN201910725136.1A 2012-04-18 2013-03-28 The method and apparatus of through hole for rear production through-hole Pending CN110491832A (en)

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