CN110460253B - Rectifier and front-end circuit constituting RFID electronic tag - Google Patents

Rectifier and front-end circuit constituting RFID electronic tag Download PDF

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CN110460253B
CN110460253B CN201910720140.9A CN201910720140A CN110460253B CN 110460253 B CN110460253 B CN 110460253B CN 201910720140 A CN201910720140 A CN 201910720140A CN 110460253 B CN110460253 B CN 110460253B
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tube
nmos
pmos
nmos tube
electrode
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CN110460253A (en
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郭东辉
刘鹏志
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Xiamen University
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Xiamen University
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
    • H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
    • H02M7/12—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/21—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/217—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M7/25—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only arranged for operation in series, e.g. for multiplication of voltage

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  • Power Engineering (AREA)
  • Rectifiers (AREA)
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Abstract

The invention relates to the technical field of circuits, and provides a rectifier and a front-end circuit for forming an RFID electronic tag. The power-on reset circuit comprises a rectifier, a voltage clamping circuit, an LDO circuit and a power-on reset circuit; the rectifier is connected with the voltage clamping circuit, the voltage clamping circuit is connected with the LDO circuit and the energy storage capacitor CL, the LDO circuit is connected with the power-on reset circuit, the rectifier receives signals from the RF antenna and converts the signals into direct current signals, the direct current signals are regulated by the voltage clamping circuit and then store energy into the energy storage capacitor CL, the energy storage capacitor CL provides power for the LDO circuit, and the LDO circuit provides power for the power-on reset circuit; the rectifying circuit of the invention utilizes the self-bias of the circuit to offset the influence of the threshold voltage, reduces the conduction voltage drop, reduces the loss and achieves the purposes of reducing the power consumption and increasing the RFID identification distance.

Description

Rectifier and front-end circuit constituting RFID electronic tag
Technical Field
The invention relates to the technical field of circuits, in particular to a rectifier and a front-end circuit for forming an RFID electronic tag.
Background
In the RFID wireless transmission system, since the energy received from the antenna by the passive chip is an RF signal and cannot be used for the tag power source, the RF signal must be rectified into a DC voltage for the subsequent circuit. The intensity of the energy emitted by the reader varies with distance. For the same reader, the short-distance chip receives more energy, the long-distance chip receives less energy, and the weak input energy cannot reach the working power supply of the chip and cannot start the chip. In far-field communication, if a chip circuit is required to work under the condition of long distance and small input energy, voltage doubling rectification is required to be carried out on a radio-frequency signal to increase the amplitude, and conversion from alternating current to direct current is realized. And the RFID front-end circuit provides power for the whole chip, a complete front-end circuit should include a high-efficiency rectifier, a stable power supply, and a power-on reset circuit that provides a reset signal to the digital baseband.
The rectifier in the RFID is responsible for exchanging energy and signals with the reader antenna, and the rectifying capability of the rectifier directly determines the working distance of the RFID. The topology of the voltage-doubling rectifier mainly has two types: dickson rectifying structures and bridge differential rectifying structures. Since in 1976, since John f, Dickson proposed a voltage doubler rectifier circuit structure (see fig. 1), and many applied the Dickson structure to RF wireless front ends, corresponding Dickson structure based circuits have developed a number of topologies including charge transfer stage charge pump structures, NCP-1/2 structures, self-biased threshold compensation structures, intrinsic tube structures, and so forth. The bridge rectifier structure has the characteristics of low input voltage, relatively high direct current output voltage, power conversion efficiency and the like, but the circuit area and leakage current are large, so that the power loss voltage of the circuit is large, and the bridge rectifier structure is not suitable for an RFID label chip. Generally, the voltage-doubling rectification utilizes a half-wave rectification principle to realize charge transfer on a capacitor by using a plurality of diodes and capacitors, and voltage multiplication is carried out to achieve an RF-DC conversion function.
At present, the main limitations on the rectification efficiency of the rectifier are: forward conduction voltage drop loss and reverse leakage current loss. In the case of a rectifier using a MOSFET-connected diode, the threshold voltage is a factor that restricts the rectification efficiency, and the primary direction of research based on the Dickson voltage-doubler rectifier circuit is to cancel or compensate the MOS diode threshold voltage. A rectification circuit of a low threshold voltage MOS tube or a low conduction voltage drop diode can effectively improve the receiving sensitivity and output direct current level.
In order to solve the problem of MOS transistor threshold voltage compensation and provide a stable power supply for an RFID chip, the scheme improves and designs a front-end circuit and an energy collecting circuit.
Disclosure of Invention
In order to solve the above problems, an object of the present invention is to provide a rectifier and a front-end circuit constituting an RFID tag.
The rectifier and the front-end circuit form the RFID electronic tag and comprise a rectifier, a voltage clamping circuit, an LDO circuit and a power-on reset circuit, wherein the rectifier is connected with the voltage clamping circuit, the voltage clamping circuit is connected with the LDO circuit and an energy storage capacitor CL, the LDO circuit is connected with the power-on reset circuit, the rectifier receives signals from an RF antenna and converts the signals into direct current signals, the direct current signals are regulated by the voltage clamping circuit and then store energy into the energy storage capacitor CL, the energy storage capacitor CL provides power for the LDO circuit, and the LDO circuit provides power for the power-on reset circuit.
The rectifier comprises front 5 stages of NMOS tubes (MN1, MN2, MN3, MN4 and MN5) and rear 5 stages of PMOS tubes (MP1, MP2, MP3, MP4 and MP5), wherein drains and sources between the NMOS tubes (MN1, MN2, MN3, MN4 and MN5) are sequentially connected and are connected with one ends of capacitors (C10, C10, C10 and C10), sources and drains between the PMOS tubes (MP 10, MP 10, MP 10, MP 10, MP 10 and MP 10) are sequentially connected and are connected with one ends of the capacitors (C10, C10 and C10), the source of the NMOS tube (MN 10) is grounded, a gate of the NMOS tube (MN 10) is connected with the drain of the NMOS tube (MN 10), the gate of the NMOS tube (MP 10) and the gate of the PMOS tube (MP 10) are connected with the drain of the NMOS tube (MN 10) and the gate of the PMOS tube (NMOS tube (MN 10) are connected with the drain of the NMOS tube (MN 10) and the drain of the NMOS tube (MN 10) and the PMOS tube (MN 10) of the PMOS tube (MN 10) and the gate of the drain of the NMOS tube (MN 10) of the gate of the PMOS tube (MN 10) of the drain of the PMOS tube (MN 10) are connected with the drain of the gate of the NMOS tube (MN 10) and the drain of the PMOS tube (MN 10) of the gate of the NMOS tube (MN 10) of the PMOS tube (MN 10) and the gate of the PMOS tube (MN 10) of the PMOS tube (NMOS tube (MN 10) of the gate of the drain of the PMOS tube (MN 10) are connected with the gate of the NMOS tube (MN 10) and the PMOS tube (NMOS tube (MN 10) of the gate of the NMOS tube of the PMOS tube (MN 10) of the NMOS tube (MN 10) are connected with the gate of the NMOS tube of the PMOS tube of the NMOS tube (MN 10) and the NMOS tube of the gate of the PMOS tube of the NMOS tube of the PMOS tube of the NMOS tube of the PMOS tube (MN 10, the PMOS tube of the NMOS tube of the PMOS tube of the gate of the PMOS tube (MN 10, the drain electrode of the PMOS tube (MP1) is connected with the drain electrode of the PMOS tube (MP4), the grid electrode of the PMOS tube (MP4) is connected with the drain electrode of the PMOS tube (MP3), the grid electrode of the PMOS tube (MP5) is connected with the drain electrode of the PMOS tube (MP4), and the source electrode of the PMOS tube (MP5) is an output end; the other end of the capacitor (C10, C12, C14, C16, C18) is connected to one end of the RF antenna, and the other end of the capacitor (C11, C13, C15, C17) is connected to the other end of the RF antenna.
The voltage clamping circuit consists of NMOS tubes (MN21, MN22, MN23, MN24, MN25 and MN26) and resistors (R1 and R2), the drains of the NMOS tubes (MN21, MN25 and MN26) are connected with the gates of the NMOS tubes (MN21) and serve as input ends to be connected with the output end of the rectifier and one end of the energy storage capacitor CL, and the other end of the energy storage capacitor CL is grounded; the source electrode of the NMOS tube (MN21) is connected with the drain electrode and the grid electrode of the NMOS tube (MN22), the source electrode of the NMOS tube (MN22) is connected with the drain electrode and the grid electrode of the NMOS tube (MN23), the source electrode of the NMOS tube (MN23) is connected with the drain electrode and the grid electrode of the NMOS tube (MN24), the source electrode of the NMOS tube (MN24) is connected with one end of a resistor R1 and the grid electrode of the NMOS tube (MN25), the source electrode of the NMOS tube (MN25) is connected with one end of a resistor R2 and the grid electrode of the NMOS tube (MN26), and the source electrode of the NMOS tube (MN26) is connected with the other end of the resistors (R1 and R2) and grounded.
The LDO circuit consists of PMOS tubes (MP30, MP31, MP32, MP33, MP34, MP35, MP36, MP37, MP38 and MP39), capacitors (C31 and C32), a resistor R3 and NMOS tubes (MN31, MN32, MN33, MN34, MN35, MN36, MN37, MN38 and MN 39); the source of the PMOS tube (MP34, MP31, MP32, MP33, MP35, MP36 and MP39) is connected with the drain of the PMOS tube (MP37 and MP38) and is connected with the gate of the PMOS tube (MP30) and one end of the energy storage capacitor CL, the source of the PMOS tube (MP30) is connected with the drain of the PMOS tube (MP32), the gate of the PMOS tube and one end of the capacitor C31 and the gate of the PMOS tube (MP31), the other end of the capacitor C31 is connected with the drain of the PMOS tube (MP30), the source of the NMOS tube (MN39, MN38, MN37, MN36, MN35, MN34 and MN33), and the source connection point of the source of the NMOS tube (MN34) is grounded; the grid electrode of the NMOS tube (MN31) is connected with the source electrode of the NMOS tube (MN33), one end of the capacitor C32 and the drain electrode of the PMOS tube (MP39) through a resistor, the connection point of the drain electrode of the PMOS tube (MP39) is used as an output end, the source electrode is connected with the source electrode of the NMOS tube (MN32) and the drain electrode of the NMOS tube (MN33), and the drain electrode is connected with the source electrode of the PMOS tube (MP37), the grid electrode of the PMOS tube (MP 38); the grid electrode of the NMOS transistor (MN32) is connected with one end of the resistor R3 and the drain electrode of the PMOS transistor (MP35), and the drain electrode is connected with the other end of the capacitor C32, the source electrode of the PMOS transistor (MP38) and the grid electrode of the PMOS transistor (MP 39); the grid electrode of the NMOS tube (MN33) is connected with the grid electrode and the drain electrode of the NMOS tube (MN34) and the drain electrode of the PMOS tube (MP 36); the drain and the gate of the NMOS tube (MN35) are connected with the other end of the resistor R3; the drain electrode of the NMOS tube (MN36) is connected with the drain electrode of the NMOS tube (MN38), the drain electrode of the PMOS tube (MP34) is connected with the grid electrode, the grid electrode of the NMOS tube (MN37) is connected with the drain electrode of the NMOS tube (MP33), and the drain electrode of the PMOS tube (MP33) is connected with the grid electrode of the NMOS tube (MN 3578); the gates of the PMOS tubes (MP33, MP34, MP35 and MP36) are connected; the grid electrode of the NMOS tube (MN38) is connected with the drain electrode of the NMOS tube (MN39) and the drain electrode of the PMOS tube (MP 31); the gate of the NMOS transistor (MN39) is connected with the drain of the NMOS transistor (MN 35).
The power-on reset circuit consists of PMOS tubes (MP41, MP42, MP43, MP44, MP45 and MP46), NMOS tubes (MN41, MN42, MN43, MN44 and MN45), a delay circuit, an exclusive-OR gate, a NOT gate and a capacitor C41; the source electrode of the PMOS tube (MP41) is connected with the drain electrode of the NMOS tube (MN45) and is used as an input end to be connected with the drain electrode of the PMOS tube (MP39), the grid electrode is an external port, and the drain electrode is connected with the source electrode of the PMOS tubes (MP42, MP43 and MP 44); the grid electrode of the PMOS tube (MP42) is connected with the drain electrode and the grid electrode of the NMOS tube (MN41) and the grid electrode of the NMOS tube (MN 42); the grid electrode of the PMOS tube (MP43) is connected with one end of the capacitor C41 and the source electrode of the NMOS tube (MN42) and is grounded at the connection point, and the drain electrode is connected with the drain electrode of the NMOS tube (MN42), the grid electrodes of the PMOS tube (MP44, MP45) and the NMOS tube (MN43, MN 44); the drain electrode of the PMOS tube (MP44) is connected with the drain electrode of the PMOS tube (MP46) and the source electrode of the PMOS tube (MP 45); the drain electrode of the PMOS tube (MP45) is connected with the drain electrode of the NMOS tube (MN43), the grid electrodes of the PMOS tube (MP46) and the NMOS tube (MN45), and is connected with the input end of the delay circuit and one input end of the exclusive-OR gate; the source electrode of the PMOS tube (MP46) is grounded, and the other end of the capacitor C41 is connected with the source electrode of the NMOS tube (MN 41); the source electrode of the NMOS tube (MN43) is connected with the drain electrode of the NMOS tube (MN44) and the source electrode of the NMOS tube (MN 45); the source electrode of the NMOS tube (MN44) is connected with the source electrode of the NMOS tube (MN 42); the drain electrode of the NMOS tube (MN45) is connected with the source electrode of the PMOS tube (MP 41); the other input end of the exclusive-OR gate is connected with the output port and the output end of the delay circuit, and the output end of the exclusive-OR gate is connected with the input end of the NOT gate; at least two NOT gates are arranged in series, and the output end of each NOT gate is an output end of the power-on reset circuit.
The delay circuit is composed of PMOS tubes (MP401, MP402, MP403, MP404 and MP405), NMOS tubes (MN401, MN402 and MN403) and a capacitor C401; the grid electrode of the PMOS tube (MP401) is connected with the grid electrode of the NMOS tube (MN401) and serves as an input end, the drain electrode is connected with the drain electrode of the NMOS tube (MN401) and the grid electrode of the PMOS tube (MP403), and the source electrode is connected with the source electrodes of the PMOS tubes (MP402, MP404 and MP405) and is connected with a power supply VDDL; the grid electrode of the PMOS tube (MP402) is an external input interface, and the drain electrode of the PMOS tube (MP403) is connected with the source electrode of the PMOS tube; the drain electrode of the PMOS tube (MP403) is connected with one end of the capacitor C401 and the grid electrodes of the PMOS tube (MP404) and the NMOS tube (MN 402); the drain electrode of the PMOS tube (MP404) is connected with the drain electrode of the NMOS tube (MN402), and the grid electrodes of the PMOS tube (MP405) and the NMOS tube (MN 403); the drain electrode of the PMOS tube (MP405) is connected with the drain electrode of the NMOS tube (MN403) and serves as an output end; the source of the NMOS tube (MN401) is connected with the other end of the capacitor C401 and the sources of the NMOS tubes (MN402, MN403), and is connected with GND and grounded.
The invention has the beneficial effects that: the rectifying circuit utilizes the self-bias of the circuit to offset the influence of the threshold voltage, reduces the conduction voltage drop, reduces the loss and achieves the purposes of reducing the power consumption and increasing the RFID identification distance. By adopting a low-power-consumption design method, some MOS tubes work in a sub-threshold region, and the overall power consumption of the front-end circuit is reduced.
Drawings
Fig. 1 is a schematic diagram of a Dickson voltage-multiplying rectification structure.
FIG. 2 is a block diagram of a front-end circuit according to the present invention.
Fig. 3 is a schematic diagram of the rectifier circuit of the present invention.
FIG. 4 is a schematic diagram of a voltage clamping circuit and the operating principle of the present invention.
FIG. 5 is a schematic diagram of an LDO circuit according to the present invention.
FIG. 6 is a schematic diagram of a power-on reset circuit of the present invention.
FIG. 7 is a schematic diagram of a delay circuit of the power-on-reset circuit of the present invention.
FIG. 8 is a diagram illustrating simulation results of the integrated front-end circuit according to the present invention.
Detailed Description
The invention is further illustrated by the following examples in conjunction with the accompanying drawings:
referring to fig. 2 to 8, the rectifier and front-end circuit forming the RFID tag includes a rectifier 1, a voltage clamp circuit 2, an LDO circuit 3, and a power-on reset circuit 4, where the rectifier 1 is connected to the voltage clamp circuit 2, the voltage clamp circuit 2 is connected to the LDO circuit 3 and an energy storage capacitor CL, the LDO circuit 3 is connected to the power-on reset circuit 4, the rectifier 1 receives a signal from an RF antenna and converts the signal into a dc signal, the dc signal is regulated by the voltage clamp circuit 2 and then stores energy in the energy storage capacitor CL, the energy storage capacitor CL provides power for the LDO circuit 3, and the LDO circuit 3 provides power for the power-on reset circuit 4.
The rectifier 1 comprises front 5 stages of NMOS tubes (MN1, MN2, MN3, MN4, MN5) and rear 5 stages of PMOS tubes (MP1, MP2, MP3, MP4, MP5), drains and sources between the NMOS tubes (MN1, MN2, MN3, MN4, MN5) are sequentially connected and are connected with one ends of capacitors (C10, C10, C10, C10), sources and drains between the PMOS tubes (MP 10, MP 10, MP 10, MP 10, and MP 10) are sequentially connected and are connected with one ends of the capacitors (C10, C10, C10), the source of the NMOS tube (MN 10) is grounded, the gate of the NMOS tube (MN 10) is connected with the drain of the NMOS tube (MN 10), and the gate of the NMOS tube (MP 72) is connected with the drain of the NMOS tube (MN 10), and one end of the gate of the PMOS tube (NMOS tube (MN 10) is connected with the drain of the NMOS tube (MN 10) and the gate of the drain of the PMOS tube (NMOS tube (MN 10) and the gate of the PMOS tube (MN 10) of the NMOS tube (MN 10) and the gate of the NMOS tube (MN 10) of the gate of the PMOS tube (MN 10) of the drain of the NMOS tube (MN 10) is connected with the drain of the NMOS tube (MN 10) and the gate of the drain of the PMOS tube (MN 10) of the gate of the NMOS tube (MN 10) is connected with the drain of the PMOS tube (MN 10), and the drain of the NMOS tube (MN 10) of the PMOS tube (NMOS tube (MN 10) and the gate of the PMOS tube (MN 10) of the NMOS tube (MN 10) of the gate of the NMOS tube (MN 10) are connected with the NMOS tube (MN 10) and the PMOS tube (MN 10) and the gate of the drain of the gate of the drain of the gate of the PMOS tube (MN 10) of the NMOS tube (MN 10) and the NMOS tube (MN 10) of the NMOS tube (MN 10) and the gate of the NMOS tube (MN 10) are connected with the gate of the NMOS tube (MN 10) of the PMOS tube (NMOS tube (MN 10) of the gate of the PMOS tube (MN 10), The drain electrode of the PMOS tube (MP1) is connected with the drain electrode of the PMOS tube (MP4), the grid electrode of the PMOS tube (MP4) is connected with the drain electrode of the PMOS tube (MP3), the grid electrode of the PMOS tube (MP5) is connected with the drain electrode of the PMOS tube (MP4), and the source electrode is connected with the input end of the connection voltage clamping circuit 2 as the output end; the other end of the capacitor (C10, C12, C14, C16, C18) is connected to one end of the RF antenna, and the other end of the capacitor (C11, C13, C15, C17) is connected to the other end of the RF antenna.
The voltage clamp circuit 2 comprises NMOS tubes (MN21, MN22, MN23, MN24, MN25 and MN26) and resistors (R1 and R2), the drains of the NMOS tubes (MN21, MN25 and MN26) are connected with the gates of the NMOS tubes (MN21) and serve as input ends to be connected with the output end of the rectifier 1 and one end of the energy storage capacitor CL, and the other end of the energy storage capacitor CL is grounded; the source electrode of the NMOS tube (MN21) is connected with the drain electrode and the grid electrode of the NMOS tube (MN22), the source electrode of the NMOS tube (MN22) is connected with the drain electrode and the grid electrode of the NMOS tube (MN23), the source electrode of the NMOS tube (MN23) is connected with the drain electrode and the grid electrode of the NMOS tube (MN24), the source electrode of the NMOS tube (MN24) is connected with one end of a resistor R1 and the grid electrode of the NMOS tube (MN25), the source electrode of the NMOS tube (MN25) is connected with one end of a resistor R2 and the grid electrode of the NMOS tube (MN26), and the source electrode of the NMOS tube (MN26) is connected with the other ends of the resistor R1 and the resistor R2 and is grounded.
The LDO circuit 3 consists of PMOS tubes (MP30, MP31, MP32, MP33, MP34, MP35, MP36, MP37, MP38 and MP39), capacitors (C31 and C32), a resistor R3 and NMOS tubes (MN31, MN32, MN33, MN34, MN35, MN36, MN37, MN38 and MN 39); the source of the PMOS transistor (MP34, MP31, MP32, MP33, MP35, MP36, MP39) is connected to the drain of the PMOS transistor (MP37, MP38), and is connected to the gate of the PMOS transistor (MP30) and one end of the energy storage capacitor CL, the source of the PMOS transistor (MP30) is connected to the drain of the PMOS transistor (MP32), one end of the gate and capacitor C31, and the gate of the PMOS transistor (MP31), the other end of the capacitor C31 is connected to the drain of the PMOS transistor (MP30), the source of the NMOS transistor (MN39, MN38, MN37, MN36, MN35, MN34, MN33), and is grounded at the source connection point of the NMOS transistor (MN34), wherein the source of the NMOS transistor MN36 is connected to a resistor (not shown); the grid electrode of the NMOS tube (MN31) is connected with the source electrode of the NMOS tube (MN33), one end of the capacitor C32 and the drain electrode of the PMOS tube (MP39) through a resistor (not shown), the grid electrode is connected with the power-on reset circuit 4 by taking the drain electrode connection point of the PMOS tube (MP39) as the output end, the source electrode is connected with the source electrode of the NMOS tube (MN32) and the drain electrode of the NMOS tube (MN33), and the drain electrode is connected with the source electrode of the PMOS tube (MP37), the grid electrode and the grid electrode of the PMOS tube (MP 38); the grid electrode of the NMOS transistor (MN32) is connected with one end of the resistor R3 and the drain electrode of the PMOS transistor (MP35), and the drain electrode is connected with the other end of the capacitor C32, the source electrode of the PMOS transistor (MP38) and the grid electrode of the PMOS transistor (MP 39); the grid electrode of the NMOS tube (MN33) is connected with the grid electrode and the drain electrode of the NMOS tube (MN34) and the drain electrode of the PMOS tube (MP 36); the drain and the gate of the NMOS tube (MN35) are connected with the other end of the resistor R3; the drain electrode of the NMOS tube (MN36) is connected with the drain electrode of the NMOS tube (MN38), the drain electrode of the PMOS tube (MP34) is connected with the grid electrode, the grid electrode of the NMOS tube (MN37) is connected with the drain electrode of the NMOS tube (MP33), and the drain electrode of the PMOS tube (MP33) is connected with the grid electrode of the NMOS tube (MN 3578); the gates of the PMOS tubes (MP33, MP34, MP35 and MP36) are connected; the grid electrode of the NMOS tube (MN38) is connected with the drain electrode of the NMOS tube (MN39) and the drain electrode of the PMOS tube (MP 31); the gate of the NMOS transistor (MN39) is connected with the drain (not shown) of the NMOS transistor (MN 35).
The power-on reset circuit 4 comprises PMOS transistors (MP41, MP42, MP43, MP44, MP45, MP46), NMOS transistors (MN41, MN42, MN43, MN44, MN45), a delay circuit 40, an exclusive or gate 41, a not gate 42 and a capacitor C41; the source electrode of the PMOS tube (MP41) is connected with the drain electrode of the NMOS tube (MN45) and is connected with the drain electrode of the PMOS tube (MP39) as an input end (LDO circuit 3), the grid electrode is an external port (EN _ POR), and the drain electrode is connected with the source electrode of the PMOS tubes (MP42, MP43 and MP 44); the grid electrode of the PMOS tube (MP42) is connected with the drain electrode and the grid electrode of the NMOS tube (MN41) and the grid electrode of the NMOS tube (MN 42); the grid electrode of the PMOS tube (MP43) is connected with one end of the capacitor C41 and the source electrode of the NMOS tube (MN42) and is grounded at the connection point, and the drain electrode is connected with the drain electrode of the NMOS tube (MN42), the grid electrodes of the PMOS tube (MP44, MP45) and the NMOS tube (MN43, MN 44); the drain electrode of the PMOS tube (MP44) is connected with the drain electrode of the PMOS tube (MP46) and the source electrode of the PMOS tube (MP 45); the drain of the PMOS transistor (MP45) is connected with the drain of the NMOS transistor (MN43), the grid of the PMOS transistor (MP46) and the grid of the NMOS transistor (MN45), and is connected with the input end of the delay circuit 40 and one input end of the exclusive-OR gate 41; the source electrode of the PMOS tube (MP46) is grounded, and the other end of the capacitor C41 is connected with the source electrode of the NMOS tube (MN 41); the source electrode of the NMOS tube (MN43) is connected with the drain electrode of the NMOS tube (MN44) and the source electrode of the NMOS tube (MN 45); the source electrode of the NMOS tube (MN44) is connected with the source electrode of the NMOS tube (MN 42); the drain electrode of the NMOS tube (MN45) is connected with the source electrode of the PMOS tube (MP 41); the other input end of the exclusive-or gate 41 is connected with the output port (EN) and the output end of the delay circuit 40, and the output end is connected with the input end of the not gate 42 (inverter); at least two not gates 42 (inverters) are arranged in series, and the output end is the output end of the power-on reset circuit 4.
The delay circuit 40 is composed of PMOS transistors (MP401, MP402, MP403, MP404, MP405), NMOS transistors (MN401, MN402, MN403) and a capacitor C401; the grid electrode of the PMOS tube (MP401) is connected with the grid electrode of the NMOS tube (MN401) and serves as an input end, the drain electrode is connected with the drain electrode of the NMOS tube (MN401) and the grid electrode of the PMOS tube (MP403), and the source electrode is connected with the source electrodes of the PMOS tubes (MP402, MP404 and MP405) and is connected with a power supply VDDL (not shown); the grid electrode of the PMOS tube (MP402) is an external input interface, and the drain electrode of the PMOS tube (MP403) is connected with the source electrode of the PMOS tube; the drain electrode of the PMOS tube (MP403) is connected with one end of the capacitor C401 and the grid electrodes of the PMOS tube (MP404) and the NMOS tube (MN 402); the drain electrode of the PMOS tube (MP404) is connected with the drain electrode of the NMOS tube (MN402), and the grid electrodes of the PMOS tube (MP405) and the NMOS tube (MN 403); the drain electrode of the PMOS tube (MP405) is connected with the drain electrode of the NMOS tube (MN403) and serves as an output end; the source of the NMOS transistor (MN401) is connected to the other end of the capacitor C401 and the sources of the NMOS transistors (MN402, MN403), and is connected to GND and ground (not shown).
The working process of the invention is as follows: when the amplitude of the RF signal can enable the rectifier to work, the voltage-multiplying rectifier receives an ultrahigh frequency band signal from the RF antenna and converts the ultrahigh frequency band signal into a direct current signal, the conversion from RF to DC is achieved, energy is stored on the energy storage capacitor CL, and the voltage clamping circuit is used for starting the clamping circuit to discharge to the energy storage capacitor to reduce voltage when the VDD direct current voltage is too large. When the direct-current voltage VDD output by the rectifying circuit is larger than 1.84V, the high voltage of 1.8V is output by the LDO _ H, the low voltage of 1V is output by the LDO _ L, and the whole RFID circuit starts to work. V generated by band-gap reference circuitrefThe reference voltage is used as the comparison voltage of the LDO.
As shown in fig. 3, the rectifier circuit 1 adopts a 2-step 10-stage CMOS threshold self-compensation circuit, the sources and drains of 10 MOS transistors are connected in sequence, the first 5 stages are NMOS transistors, the gates of which are connected across the drain potentials of the next MOS transistor behind, because the higher potential can cancel the NMOS threshold voltage, and the fifth stages are PMOS transistors, the gates of which are connected across the drain potential of the previous MOS transistor behind, because the lower potential can cancel the influence of the PMOS threshold voltage. Meanwhile, a mixed PMOS and NMOS circuit is adopted, so that an additional Dummy tube is not required to be added, and the circuit area is reduced. L of tubes in an electric circuitminThe minimum size is taken to reduce the influence of parasitic capacitance. And the source and the drain of the PMOS tube are connected to reduce the influence of the body effect.
As shown in fig. 4, a is a voltage clamp circuit diagram, and b is a voltage clamp circuit operation principle diagram; for RFID tags, when the tag is close to the reader, the energy obtained is high, which can be up to tens of volts, because the input regulation rate of the low-dropout voltage regulator circuit is limited. If a bleeder circuit or a protection circuit is not used, the RFID tag circuit is damaged by a large current and then cannot work. Therefore, it is not only easy to useThe voltage clamping circuit is adopted to carry out primary voltage limiting, and when the rectified voltage of the RFID label exceeds MN21～MN24After the sum of the on-voltages of MN25、MN26And subsequently turned on, the voltage clamp begins to bleed current.
As shown in fig. 5, the LDO circuit 3 mainly includes an error amplifier, a power amplifier stage, a resistor feedback network, and a BG module. The left part is a starting circuit which has the function of ensuring that the band-gap reference circuit can work in the power-on process, after the power-on, the capacitor C31 can be continuously charged and copied to the grid of the MN38 through the current mirror, when the voltage is greater than the threshold voltage of the current mirror, the current mirror formed by the circuits MP33, MP34, MN36 and MN37 can be conducted to output a disturbance, so that the current mirror can get rid of the degeneracy point of the 'all 0' state, and current is generated. After circuit starting VrefThe bias voltage is generated to control the gate of MN39 to turn on, at this time, the gate of MN38 is pulled low, the start-up circuit is turned off, and the charge of capacitor C31 is discharged through MP 30. The middle part is a reference voltage generating circuit which adopts a band-gap reference voltage source to generate VrefThe principle is to sum the voltages of opposite temperature coefficients to generate a reference voltage, and the MOS transistor in the dashed line box works in the sub-threshold region. The right part is a two-stage operational amplifier, and a Miller capacitance compensation method is adopted for keeping stability. Wherein M isN36、MN37Two MOS tubes working in subthreshold region generate delta VGSForming a current IPTATAfter the voltage is amplified by m times in proportion by a current mirror, positive temperature coefficient voltage mI is obtained in a resistor R3PTATR, then a subthreshold V with a negative temperature coefficientGSAdding to obtain a reference voltage V with zero temperature coefficientref. The error amplifier is essentially a two-stage operational amplifier structure, so the phase compensation of the feedback loop is a design difficulty of the LDO. Meanwhile, the power adjusting tube of the output stage adjusts the V of the power adjusting tubeGSAnd VDSTo ensure the output voltage to be stable, and to provide certain drive for the load.
The power-on reset circuit 4, as shown in fig. 6, controls the enabling of POR by an external port EN signal, and reduces static power consumption by shutting down the POR module when EN is at a high level. When the output voltage of the voltage stabilizing circuit reaches a certain value, a positive pulse signal with a certain time is generated, the time is related to the time delay, and the positive pulse signal is a power-on reset signal after shaping. As shown in fig. 7, in the DELAY circuit 40(DELAY block), the VBP signal is used to control the DELAY amount, i.e., the pulse width of the power-on reset signal. The Schmitt trigger is used for preventing the influence of power supply ripples or noises on a circuit and generating a hysteresis effect.
Fig. 8 is a simulation result of the whole front-end circuit of the present invention, and it can be seen from the simulation result that when the amplitude of the RF signal input to the rectifier circuit is about 230mV, the rectifier circuit outputs a DC voltage of 1.84V, the low dropout voltage regulator circuit outputs DC voltages of 1.8V and 1V, and about 20us of the circuit after power-on reaches a steady state. Meanwhile, the POR circuit can generate a high-level reset signal of about 7us when the power-on process of the circuit is carried out, and the digital circuit is reset.
The rectifying circuit of the invention utilizes the self-bias of the circuit to offset the influence of the threshold voltage, reduces the conduction voltage drop, reduces the loss and achieves the purposes of reducing the power consumption and increasing the RFID identification distance. By adopting a low-power-consumption design method, some MOS tubes work in a sub-threshold region, and the overall power consumption of the front-end circuit is reduced.
The above description is only for the specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto, and any changes or substitutions that are not thought of through the inventive work should be covered within the protection scope of the present invention.

Claims (2)

1. Constitute RFID electronic tags's rectifier and front end circuit, including rectifier, voltage clamp circuit, LDO circuit and power-on reset circuit, its characterized in that: the rectifier is connected with the voltage clamping circuit, the voltage clamping circuit is connected with the LDO circuit and the energy storage capacitor CL, the LDO circuit is connected with the power-on reset circuit, the rectifier receives signals from the RF antenna and converts the signals into direct current signals, the direct current signals are regulated by the voltage clamping circuit and then store energy into the energy storage capacitor CL, the energy storage capacitor CL provides power for the LDO circuit, and the LDO circuit provides power for the power-on reset circuit;
the voltage clamping circuit consists of an NMOS tube MN21, an NMOS tube MN22, an NMOS tube MN23, an NMOS tube MN24, an NMOS tube MN25, an NMOS tube MN26, a resistor R1 and a resistor R2, wherein the drain electrode of the NMOS tube MN21, the drain electrode of the NMOS tube MN25 and the drain electrode of the NMOS tube MN26 are connected with the grid electrode of the NMOS tube MN21 and used as the input end to be connected with the output end of the rectifier and one end of the energy storage capacitor CL, and the other end of the energy storage capacitor CL is grounded; the source electrode of the NMOS tube MN21 is connected with the drain electrode and the grid electrode of the NMOS tube MN22, the source electrode of the NMOS tube MN22 is connected with the drain electrode and the grid electrode of the NMOS tube MN23, the source electrode of the NMOS tube MN23 is connected with the drain electrode and the grid electrode of the NMOS tube MN24, the source electrode of the NMOS tube MN24 is connected with one end of a resistor R1 and the grid electrode of the NMOS tube MN25, the source electrode of the NMOS tube MN25 is connected with one end of the resistor R2 and the grid electrode of the NMOS tube MN26, the source electrode of the NMOS tube MN26 is connected with the resistor R1, and the other end of the resistor R2 is connected and grounded;
the LDO circuit consists of a PMOS tube MP30, a PMOS tube MP31, a PMOS tube MP32, a PMOS tube MP33, a PMOS tube MP34, a PMOS tube MP35, a PMOS tube MP36, a PMOS tube MP37, a PMOS tube MP38, a PMOS tube MP39, a capacitor C31, a capacitor C32, a resistor R3, an NMOS tube MN31, an NMOS tube MN32, an NMOS tube MN33, an NMOS tube MN34, an NMOS tube MN35, an NMOS tube MN36, an NMOS tube MN37, an NMOS tube MN38 and an NMOS tube MN 39; a PMOS tube MP34, a PMOS tube MP31, a PMOS tube MP32, a PMOS tube MP33, a PMOS tube MP35, a PMOS tube MP36, a source electrode of a PMOS tube MP39, a PMOS tube MP37, a drain electrode of the PMOS tube MP38 is connected with a grid electrode of a PMOS tube MP30 and one end of an energy storage capacitor CL, a source electrode of the PMOS tube MP30 is connected with a drain electrode of the PMOS tube MP32, one end of the grid electrode and a capacitor C31, and the grid electrode of the PMOS tube MP31, the other end of the capacitor C31 is connected with a drain electrode of the PMOS tube MP30, an NMOS tube MN39, an NMOS tube MN38, an NMOS tube MN37, an NMOS tube MN36, an NMOS tube MN35, an NMOS tube MN34, and a source electrode of the NMOS tube MN33, and the source electrode connection point of the NMOS tube MN34 is grounded; the grid electrode of the NMOS tube MN31 is connected with the source electrode of the NMOS tube MN33, one end of the capacitor C32 and the drain electrode of the PMOS tube MP39 through a resistor, the connection point of the drain electrode of the PMOS tube MP39 is used as an output end, the source electrode is connected with the source electrode of the NMOS tube MN32 and the drain electrode of the NMOS tube MN33, and the drain electrode is connected with the source electrode and the grid electrode of the PMOS tube MP37 and the grid electrode of the PMOS tube MP 38; the grid electrode of the NMOS transistor MN32 is connected with one end of the resistor R3 and the drain electrode of the PMOS transistor MP35, and the drain electrode is connected with the other end of the capacitor C32, the source electrode of the PMOS transistor MP38 and the grid electrode of the PMOS transistor MP 39; the grid electrode of the NMOS tube MN33 is connected with the grid electrode and the drain electrode of the NMOS tube MN34 and the drain electrode of the PMOS tube MP 36; the drain and the gate of the NMOS transistor MN35 are connected with the other end of the resistor R3; the drain electrode of the NMOS tube MN36 is connected with the drain electrode of the NMOS tube MN38, the drain electrode of the PMOS tube MP34 and the grid electrode thereof, and the grid electrode thereof is connected with the grid electrode and the drain electrode of the NMOS tube MN37 and the drain electrode of the PMOS tube MP 33; the gates of the PMOS tube MP33, the PMOS tube MP34, the PMOS tube MP35 and the PMOS tube MP36 are connected; the grid electrode of the NMOS transistor MN38 is connected with the drain electrode of the NMOS transistor MN39 and the drain electrode of the PMOS transistor MP 31; the grid electrode of the NMOS tube MN39 is connected with the drain electrode of the NMOS tube MN 35;
the power-on reset circuit consists of a PMOS tube MP41, a PMOS tube MP42, a PMOS tube MP43, a PMOS tube MP44, a PMOS tube MP45, a PMOS tube MP46, an NMOS tube MN41, an NMOS tube MN42, an NMOS tube MN43, an NMOS tube MN44, an NMOS tube MN45, a delay circuit, an exclusive-OR gate, a NOT gate and a capacitor C41; the source electrode of the PMOS tube MP41 is connected with the drain electrode of the NMOS tube MN45 and is used as the input end to be connected with the drain electrode of the PMOS tube MP39, the grid electrode is an external port, and the drain electrode is connected with the source electrodes of the PMOS tube MP42, the PMOS tube MP43 and the PMOS tube MP 44; the grid electrode of the PMOS tube MP42 is connected with the drain electrode and the grid electrode of the NMOS tube MN41 and the grid electrode of the NMOS tube MN 42; the grid electrode of the PMOS tube MP43 is connected with one end of the capacitor C41 and the source electrode of the NMOS tube MN42, and is grounded at the connection point, the drain electrode is connected with the drain electrode of the NMOS tube MN42, the PMOS tube MP44, the PMOS tube MP45, the NMOS tube MN43 and the grid electrode of the NMOS tube MN 44; the drain electrode of the PMOS tube MP44 is connected with the drain electrode of the PMOS tube MP46 and the source electrode of the PMOS tube MP 45; the drain electrode of the PMOS tube MP45 is connected with the drain electrode of the NMOS tube MN43, the grid electrodes of the PMOS tube MP46 and the NMOS tube MN45, and is connected with the input end of the delay circuit and one input end of the exclusive-OR gate; the source electrode of the PMOS tube MP46 is grounded, and the other end of the capacitor C41 is connected with the source electrode of the NMOS tube MN 41; the source electrode of the NMOS transistor MN43 is connected with the drain electrode of the NMOS transistor MN44 and the source electrode of the NMOS transistor MN 45; the source electrode of the NMOS transistor MN44 is connected with the source electrode of the NMOS transistor MN 42; the drain electrode of the NMOS transistor MN45 is connected with the source electrode of the PMOS transistor MP 41; the other input end of the exclusive-OR gate is connected with the output port and the output end of the delay circuit, and the output end of the exclusive-OR gate is connected with the input end of the NOT gate; at least two NOT gates are arranged in series, and the output end of each NOT gate is an output end of the power-on reset circuit;
when the amplitude of the RF signal can enable the rectifier to work, the voltage-multiplying rectifier receives the ultrahigh frequency band signal from the RF antenna and converts the ultrahigh frequency band signal into a direct current signal to achieve conversion from RF to DC, energy is stored on the energy storage capacitor CL, and the voltage clamping circuit is used for storing the direct current signal when VDD is zeroWhen the current voltage is overlarge, the clamping circuit is started to discharge the energy storage capacitor to reduce the voltage; when the direct-current voltage VDD output by the rectifying circuit is larger than 1.84V, the LDO _ H outputs 1.8V high voltage, the LDO _ L outputs 1V low voltage, the RFID whole circuit starts to work, and V generated by the band-gap reference circuitrefThe reference voltage is used as the comparison voltage of the LDO.
2. The rectifier and front-end circuit for RFID tags according to claim 1, wherein: the delay circuit is composed of a PMOS tube MP401, a PMOS tube MP402, a PMOS tube MP403, a PMOS tube MP404, a PMOS tube MP405, an NMOS tube MN401, an NMOS tube MN402, an NMOS tube MN403 and a capacitor C401; the grid electrode of the PMOS tube MP401 is connected with the grid electrode of the NMOS tube MN401 and serves as an input end, the drain electrode is connected with the drain electrode of the NMOS tube MN401 and the grid electrode of the PMOS tube MP403, and the source electrode is connected with the PMOS tube MP402, the PMOS tube MP404 and the source electrode of the PMOS tube MP405 and is connected with a power supply VDDL; the grid electrode of the PMOS tube MP402 is an external input interface, and the drain electrode is connected with the source electrode of the PMOS tube MP 403; the drain electrode of the PMOS tube MP403 is connected with one end of the capacitor C401, the gate electrodes of the PMOS tube MP404 and the NMOS tube MN 402; the drain electrode of the PMOS tube MP404 is connected with the drain electrode of the NMOS tube MN402, and the grid electrodes of the PMOS tube MP405 and the NMOS tube MN 403; the drain electrode of the PMOS tube MP405 is connected with the drain electrode of the NMOS tube MN403 and serves as an output end; the source electrode of the NMOS transistor MN401 is connected with the other end of the capacitor C401, the NMOS transistor MN402 and the source electrode of the NMOS transistor MN403, and is connected with GND and grounded.
CN201910720140.9A 2019-08-06 2019-08-06 Rectifier and front-end circuit constituting RFID electronic tag Active CN110460253B (en)

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