JPS59193056A - Substrate bias voltage generating circuit - Google Patents

Abstract

PURPOSE:To obtain the titled circuit of less consumed power by a method wherein the voltage generating circuit is composed of an oscillating circuit, a circuit forming the substrate bias voltage by rectifying the oscillation signal pulse thereof, and a voltage controlling circuit which compares this voltage with the reference voltage and then stops the oscillating action of the oscillating circuit when the voltage becomes over a fixed value in absolute value manner. CONSTITUTION:For example, four inverters 1V1-1V4 are connected in cascade form, and the output of the inverter 1V4 at the final stage is inputted to a rectifying circuit composed of capacitors C1, C2 and MOSFET elements Q1, Q2. Besides, a ring oscillator OSC is composed by connecting a NOR gate G, consisting of a C-MOS circuit impressed by a positive power source voltage Vcc, to the inverter 1V1 at the initial stage, and the output terminal of the gate G is connected to the output side of the inverter 1V4 at the final stage. The gate of the element Q2 is coupled to the voltage Vcc via resistors R2 and R1. The action of the oscillator is controlled in such a manner, thus generating a bias voltage of a fixed value -Vbb in the rectifying circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a substrate bias voltage generation circuit, and relates to a technique that is effective for, for example, a circuit built in a CMO5 integrated circuit.

[Background technology]

2. Description of the Related Art Conventionally, it has been known that a semiconductor integrated circuit device configured with a MOSFET (insulated gate field effect transistor) has a built-in substrate bias voltage generation circuit in order to reduce parasitic capacitance with the substrate. A known substrate bias generation circuit includes an oscillation circuit and a circuit that rectifies its output pulse, and supplies a negative voltage to, for example, an N-type substrate (or well region).

In such a substrate bias voltage generation circuit, the substrate bias voltage fluctuates due to the operation of the logic circuit or fluctuations in the power supply voltage Vcc, etc., resulting in problems such as fluctuations in the threshold voltage of the MOSFET, for example. especially,
Supplying substrate bias voltage only to specific well regions 0
In MO3 (complementary MO3) circuits, etc., the relative relationship between the threshold voltage of a MOSFET to which no substrate bias voltage is applied and the threshold voltage of a MOSFET to which the above substrate bias voltage is applied is very different. This poses a problem when transmitting and receiving signals between MO3FET circuits.

[Purpose of the invention]

An object of the present invention is to provide a substrate bias voltage generation circuit that can generate a controlled substrate bias voltage.

Another object of the present invention is to provide a substrate bias voltage generation circuit with reduced power consumption.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

In other words, the substrate bias voltage is compared with a predetermined reference voltage, and the absolute value of the substrate bias voltage is greater than a certain voltage (
By stopping the oscillation operation of the oscillation circuit when this occurs, a substrate bias voltage controlled to a constant voltage is formed.

[Embodiment 1] FIG. 1 shows a circuit diagram of an embodiment of a substrate bias voltage generation circuit built in a semiconductor integrated circuit device composed of MOSFETs. The circuit elements constituting each circuit in the figure are formed using known semiconductor integrated circuit manufacturing techniques.

The substrate bias voltage generation circuit of this embodiment is composed of the following circuits.

Although not particularly limited, four inverters rV1 to I
V4 are connected in cascade configuration. Final stage inverter IV4
The output signal is applied to one input of the NOR gate circuit G, and the output signal is applied to the input of the first stage inverter IVI, thereby forming a ring oscillator osc.

Although not particularly limited, these inverters IVI to IV4 and the gate circuit G are configured by CMOS circuits. In addition, although not particularly limited, inverter IV4
The output signal of is rectified by the next rectifier circuit to form a substrate bias voltage -vbb.

The rectifier circuit is composed of capacitors CI and C2 and diode-type MO5FETs QI and Q2. That is, the output pulse of the inverter IV4 is supplied to one end of the capacitor C1, and the MO5FET QI is provided between the other end of the capacitor CI and the ground potential of the circuit.

The MO3FETQ2 is provided between the connection point between the capacitor Cl and the MO3FETQI and the substrate or well region to which a bias voltage is applied. The capacitor C2 is a stray capacitance between the substrate or well region to which the bias voltage is applied and the ground potential of the circuit.

For example, when forming a negative substrate bias voltage -vbb from a positive power supply voltage Vcc, the diode-type MO3F
The gate electrodes of ETQI and Q2 are connected as shown. The output pulse of the inverter IV4 is the power supply voltage Vc
When the voltage is at a high level such as c, MO3FET QI is turned on, so that the capacitor C1 is charge-amplified to the Vcc-Vth level.

Next, when the output pulse of the inverter IV4 is at a low level such as the ground potential of the circuit, MO3FETQ1 is turned off and MO3FETQ2 is turned on, so that the negative voltage at the other end of the capacitor c1 is
2, the substrate or well region is biased to a negative voltage. By repeating the above operation, the bias voltage = vbb applied to the substrate or well region has a maximum voltage of −Vcc+2 in absolute value.
It becomes vth.

In this embodiment, the following voltage control circuit is provided in order to control the substrate bias voltage -vbb to a predetermined constant voltage below the maximum voltage.

Although not particularly limited, the substrate bias voltage -vbb is supplied to one end of a voltage dividing resistor circuit made up of high-resistance polysilicon resistors R1 and R2, and the other end is supplied with the power supply voltage Vcc.
is supplied, thereby creating a substantial partial pressure. Although not particularly limited, this divided voltage is applied to the gate of MO3FETQ3 that constitutes the inverter circuit. This M
A high-resistance polysilicon resistor R3 is provided between the dot L/in of the O3FET Q3 and the power supply voltage Vcc. Then, the threshold voltage of MO3FETQ3 of this inverter circuit is set as a reference voltage, and the output signal is supplied to the other input of the gate circuit G.

The operation of this embodiment circuit will be explained with reference to the operational waveform diagram in FIG.

Now, the substrate bias voltage -vbb has become large in absolute value, and the voltage divided by the voltage dividing circuit is the voltage
When the threshold voltage vth of the 3FETQ3 becomes lower than that, the MO3FETQ3 is turned off. This MO3FET
Due to the OFF state of Q3, its output level VC becomes high level (logic "1°") and controls the gate circuit G to close (its output is fixed at low level), so the oscillation operation of ring oscillator O3C stops. This also stops the rectification operation described above, so the substrate bias voltage -
vbb no longer increases in absolute value (increases toward the negative voltage side).

Furthermore, when the substrate bias voltage -vbb becomes small in absolute value due to the stoppage of the rectifying operation or leakage current from the substrate or well region, the divided voltage increases to the high level side and the MOS F Since ETQ3 is turned on, its output level becomes a low level (logic "0"), and data 1 to circuit G are controlled to be open, so that a positive feedback loop of ring oscillator O3C is formed, thereby inhibiting its oscillation. The operation is started.The rectification operation of the output pulse formed by this oscillation operation is performed again in the rectifier circuit, so that the substrate bias voltage ＼/bb is kept in absolute value until it reaches the above-mentioned constant voltage. By the above operation, the substrate bias voltage -v
bb can be controlled to be -' a predetermined constant voltage.

Although not particularly limited, the substrate bias voltage -vbb can be applied to a static RAM (
It is used to supply a P-type well region in which a memory array (random access memory) is formed.

〔effect〕

(]) Since the substrate bias voltage can be controlled to a desired constant voltage, it is possible to obtain the effect that the threshold voltage of the MOSFET formed in the substrate or well region to which the substrate bias voltage is applied can be made constant.

(2) MO3FET formed in the substrate or well region to which the substrate bias voltage is applied according to (1) above.
The effect is that the parasitic capacitance flowing into the circuit can be kept constant.

(3) According to (1) and (2) above, since the MOSFET and parasitic capacitance can be kept constant, it is possible to prevent deterioration of the operating margin of the circuit due to fluctuations in these.

(4) When the ring oscillator is configured with a CMO3 circuit, the oscillation operation of the ring oscillator is stopped when the substrate bias voltage becomes larger than necessary.
Theoretically, the current consumption can be reduced to zero, so the current consumption in the substrate bias voltage generation circuit can be suppressed to the necessary minimum.

(5) If the substrate bias voltage generated by the substrate bias voltage generation circuit as in the above embodiment is supplied to the well region where the memory array of the CMOS static RAM is formed, In a data retention state such as during a first hack-up, no leakage current flows into the well region, so the time it takes for the oscillation circuit to operate is shortened (this reduces power consumption). ＼・An effect can be obtained in that a static type RAM that can be subjected to a pull-up operation can be obtained.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, the above MO3F
The specific circuit configurations of the oscillation circuit and voltage control circuit may adopt various embodiments, such as omitting the inverter circuit consisting of ETQ3 and polysilicon resistor R3 and using the logic threshold voltage of the gate circuit G as the reference voltage. It is something that can be done. Furthermore, a PN junction diode or the like may be used as the unidirectional element constituting the rectifier circuit.

[Application field]

The present invention can be widely applied as a substrate bias voltage generation circuit built into a semiconductor integrated circuit device.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is an operation waveform diagram for explaining its operation. IVI~IV4...Inverter, G...Nor gate circuit

Claims (1)

[Claims] 1. An oscillation circuit and a rectifier circuit that rectifies this oscillation signal pulse to form a substrate bias voltage, compare the substrate bias voltage with a predetermined reference voltage, and determine whether the substrate bias voltage is an absolute value. and a voltage control circuit that stops the oscillation operation of the oscillation circuit when the voltage exceeds a certain value. 2. The oscillation circuit has a plurality of CMOS inverter circuits and one gate circuit connected in series in a ring shape, and the output signal of the voltage detection circuit is applied to the other input terminal of the gate circuit. The substrate bias voltage generating circuit according to claim 1, characterized in that: 3. The voltage control circuit includes a voltage dividing circuit that divides the substrate bias voltage, and an inverter circuit that receives the divided voltage, and uses a logic threshold voltage of the inverter circuit as the reference voltage. A substrate bias voltage generation circuit according to claim 1 or 2. 4. The substrate bias voltage generation circuit according to claim 1, 2 or 3, wherein the substrate bias voltage generation circuit is built in a CMOS integrated circuit device.