JPH0468784B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a substrate bias voltage generation circuit, and relates to a technique that is effective for, for example, a circuit built in a CMOS integrated circuit.

[Background technology]

2. Description of the Related Art Conventionally, it has been known that a semiconductor integrated circuit device configured with MOSFETs (insulated gate field effect transistors) has a built-in substrate bias voltage generation circuit in order to reduce parasitic capacitance with the substrate. A known substrate bias generation circuit includes an oscillation circuit and a circuit that rectifies its output pulse, and supplies a negative voltage to, for example, an N-type substrate (or well region).

In such a substrate bias voltage generation circuit, the substrate bias voltage fluctuates due to the operation of the logic circuit or fluctuations in the power supply voltage Vcc, etc.
Problems such as fluctuations in the threshold voltage of the MOSFET arise. In particular, CMOS (complementary type)
In MOS) circuits, the relative relationship between the threshold voltage of a MOSFET to which no substrate bias voltage is applied and the threshold voltage of a MOSFET to which the above substrate bias voltage is applied is very different. This is a problem when transmitting and receiving signals.

[Object of the Invention] An object of the present invention is to provide a substrate bias voltage generation circuit that can generate a controlled substrate bias voltage.

Another object of the present invention is to provide a substrate bias voltage generation circuit that achieves low power consumption.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows. In other words, the substrate bias voltage is controlled to a constant voltage by comparing the substrate bias voltage with a predetermined reference voltage and stopping the oscillation operation of the oscillation circuit when the substrate bias voltage becomes larger than a certain voltage in absolute value. It forms a bias voltage.

Embodiment 1 FIG. 1 shows a circuit diagram of an embodiment of a substrate bias voltage generation circuit built into a semiconductor integrated circuit device configured with MOSFETs. The circuit elements constituting each circuit in the figure are formed using known semiconductor integrated circuit manufacturing techniques.

The substrate bias voltage generation circuit of this embodiment is constituted by the following circuits.

Although not particularly limited, four inverters IV1
4 to IV4 are connected in cascade. The output signal of the final stage inverter IV4 is the NOR gate circuit G.
The ring oscillator OSC is configured by applying the output signal to the input of the first-stage inverter IV1.
Although not particularly limited, these inverters IV1
IV4 to IV4 and the gate circuit G are constructed by CMOS circuits. Also, although not particularly limited,
The output signal of inverter IV4 is rectified by the next rectifier circuit to form substrate bias voltage -Vbb.

The rectifier circuit is composed of capacitors C1 and C2 and diode-type MOSFETs Q1 and Q2. That is, the output pulse of the inverter IV4 is supplied to one end of the capacitor C1, and the above-mentioned pulse is supplied between the other end of the capacitor C1 and the ground potential of the circuit.
MOSFETQ1 is provided. Then, between the connection point of this capacitor C1 and MOSFET Q1 and the substrate or well region that applies the bias voltage,
MOSFETQ2 is provided. The capacitor C2 is a stray capacitance between the substrate or well region to which the bias voltage is applied and the ground potential of the circuit.

For example, when forming a negative substrate bias voltage -Vbb from a positive power supply voltage Vcc, the gate electrodes of the diode-type MOSFETs Q1 and Q2 are connected as shown. When the output pulse of the inverter IV4 is at a high level such as the power supply voltage Vcc,
Since MOSFET Q1 is turned on, the capacitor C1 is charged up to the Vcc-Vth level.

Next, when the output pulse of the inverter IV4 is at a low level like the ground potential of the circuit,
MOSFETQ1 turns off and MOSFETQ2
is turned on, the negative voltage at the other end of the capacitor C1 is transmitted to the capacitor C2, and the substrate or well region is biased to a negative voltage. By repeating the above operation, the bias voltage -Vbb applied to the substrate or well region has a maximum voltage of -Vcc+ in absolute value.
It becomes 2Vth.

In this embodiment, the following voltage control circuit is provided to control the substrate bias voltage -Vbb to a predetermined constant voltage below the maximum voltage.

Although the substrate bias voltage -Vbb is not particularly limited, the high resistance value polysilicon resistors R1 and R2
The power supply voltage Vcc is supplied to one end of a voltage dividing resistor circuit constructed of the following, and the power supply voltage Vcc is supplied to the other end, whereby the voltage is substantially divided. Although this divided voltage is not particularly limited, it can be used to configure the inverter circuit.
Applied to the gate of MOSFETQ3. this
A high-resistance polysilicon resistor R3 is provided between the drain of MOSFET Q3 and the power supply voltage Vcc. And MOSFETQ of this inverter circuit
The threshold voltage of 3 is used as a reference voltage, and the output signal is supplied to the other input of the gate circuit G.

The operation of this embodiment circuit will be explained with reference to the operation waveform diagram in FIG.

Now, when the substrate bias voltage -Vbb increases in absolute value and the voltage V divided by the voltage dividing circuit becomes equal to or lower than the threshold voltage Vth of the MOSFET Q3, the MOSFET Q3 turns off.
Due to the off state of MOSFET Q3, its output level VC becomes high level (logic "1") and controls the gate circuit G to close (its output is fixed at low level), so that the ring oscillator
OSC oscillation operation stops. This also stops the above rectification operation, so the substrate bias voltage -
Vbb does not become larger in absolute value (larger on the negative voltage side) than this.

Furthermore, when the substrate bias voltage -Vbb becomes small in absolute value due to the stoppage of the rectifying operation or leakage current from the substrate or well region, the divided voltage increases to the high level side and MOSFETQ3
is turned on, its output level becomes low level (logic "0"), and gate circuit G is controlled to open, so a positive feedback loop of the linda oscillator OSC is formed, thereby inhibiting its oscillation operation. It will be started. By rectifying the output pulse formed by this oscillation operation again in the rectifying circuit, the substrate bias voltage -Vbb increases in absolute value until it reaches the constant voltage. By the above operation, the substrate bias voltage -Vbb can be controlled to be substantially a predetermined constant voltage.

Although not particularly limited, the above substrate bias voltage -
Vbb is a static type configured with a CMOS circuit.
It is used to supply a P-type well region where a RAM (random access memory) memory array is formed.

〔effect〕

(1) The substrate bias voltage can be maintained constant through a type of negative feedback operation. Furthermore, if the power supply voltage supplied to the semiconductor integrated circuit device to which the substrate bias voltage generation circuit according to the present invention is applied fluctuates due to noise or the like, the power supply wiring inside the semiconductor integrated circuit device and the substrate bias voltage supply The substrate bias voltage fluctuates due to undesired capacitive coupling due to non-ignorable parasitic capacitance that exists between the semiconductor substrate or the well region, and when the power supply voltage suddenly increases, the substrate bias voltage decreases to its absolute value. is made small, and conversely, when the power supply voltage drops rapidly, the absolute value of the substrate bias voltage is made large. At this time,
The substrate bias voltage generation circuit according to the present invention adopts a configuration in which the operation of the oscillation circuit is controlled by a divided voltage of the voltage between the power supply voltage and the substrate bias voltage. Therefore, when the power supply voltage rises rapidly, the oscillation circuit is activated at an earlier timing according to the voltage division between the power supply voltage whose level has suddenly increased and the substrate bias voltage whose absolute value has been reduced. In addition, when the power supply voltage suddenly falls, the oscillation circuit is activated at a timing according to the divided voltage between the power supply voltage whose level has suddenly fallen and the substrate bias voltage which has been increased in absolute value. Operation can be stopped.
These allow the substrate bias voltage to be stably controlled to a desired constant value. Therefore, an effect can be obtained in that the threshold voltage of the MOSFET formed in the substrate or well region to which the substrate bias voltage is applied can be made constant.

(2) Due to (1) above, the
The effect is that the parasitic capacitance in the MOSFET circuit can be kept constant.

(3) According to (1) and (2) above, since the MOSFET and the parasitic capacitance can be kept constant, it is possible to prevent deterioration of the operating margin of the circuit due to fluctuations thereof.

(4) When the above ring oscillator is configured with a CMOS circuit, the oscillation operation of the ring oscillator is stopped when the substrate bias voltage becomes larger than necessary, so the current consumption can theoretically be reduced to zero. Therefore, it is possible to suppress the current consumption in the substrate bias voltage generation circuit to the necessary minimum.

(5) The substrate bias voltage generated by the substrate bias voltage generation circuit as in the above embodiment is
When supplying to the well region where the memory array of CMOS static RAM is formed, the above oscillation circuit The static type is suitable for battery backup operation because it reduces power consumption by shortening the time the device is in the operating state.
The effect of obtaining RAM can be obtained.

Although the invention made by the present inventor has been specifically explained based on Examples above, this invention is not limited to the above Examples, and it is understood that various changes can be made without departing from the gist of the invention. Needless to say. For example, by omitting the inverter circuit consisting of MOSFET Q3 and polysilicon resistor R3,
The specific circuit configurations of the oscillation circuit and voltage control circuit can take various embodiments, such as one that utilizes the logic threshold voltage of the gate circuit G as the reference voltage. Furthermore, a PN junction diode or the like may be used as the unidirectional element constituting the rectifier circuit.

[Application field]

The present invention can be widely applied as a substrate bias voltage generation circuit built into a semiconductor integrated circuit device.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention;
FIG. 2 is an operation waveform diagram for explaining the operation. IV1 to IV4...Inverter, G...Nor gate circuit.

Claims (1)

[Claims] 1. A substrate bias voltage generation circuit formed in a predetermined area of a semiconductor integrated circuit device including a large number of MOSFETs on one semiconductor substrate, comprising: a plurality of CMOS inverter circuits; An oscillation circuit consisting of gate circuits having at least two inputs connected in series in a ring shape, a rectifier circuit that rectifies the oscillation signal pulse to form a substrate bias voltage, and between the power supply voltage of the circuit and the substrate bias voltage. A voltage dividing means consisting of a high resistance element that divides the voltage of a voltage control circuit that supplies a signal to another input terminal of the gate circuit to stop the oscillation operation of the oscillation circuit when the voltage exceeds a certain value; generation circuit. 2 The substrate bias voltage generation circuit described above is a CMOS
A substrate bias voltage generation circuit according to claim 1, which is built in an integrated circuit.