CN110416372A - A kind of preparation method of the lossless micro-nano structure towards micro-LED application - Google Patents
A kind of preparation method of the lossless micro-nano structure towards micro-LED application Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title claims abstract description 44
- 239000002086 nanomaterial Substances 0.000 title claims abstract description 39
- 238000005530 etching Methods 0.000 claims abstract description 89
- 239000004065 semiconductor Substances 0.000 claims abstract description 59
- 238000000034 method Methods 0.000 claims abstract description 57
- 239000000463 material Substances 0.000 claims abstract description 40
- 230000006378 damage Effects 0.000 claims abstract description 37
- 208000027418 Wounds and injury Diseases 0.000 claims abstract description 34
- 208000014674 injury Diseases 0.000 claims abstract description 34
- 230000008569 process Effects 0.000 claims abstract description 22
- 238000001020 plasma etching Methods 0.000 claims abstract description 14
- 238000012546 transfer Methods 0.000 claims abstract description 14
- 238000000354 decomposition reaction Methods 0.000 claims description 59
- 229910002601 GaN Inorganic materials 0.000 claims description 55
- 150000004767 nitrides Chemical class 0.000 claims description 51
- 239000013078 crystal Substances 0.000 claims description 43
- 239000000758 substrate Substances 0.000 claims description 39
- 229920002120 photoresistant polymer Polymers 0.000 claims description 30
- 229910052751 metal Inorganic materials 0.000 claims description 28
- 239000002184 metal Substances 0.000 claims description 28
- 238000001451 molecular beam epitaxy Methods 0.000 claims description 27
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 16
- 229910052594 sapphire Inorganic materials 0.000 claims description 15
- 239000010980 sapphire Substances 0.000 claims description 15
- 238000000151 deposition Methods 0.000 claims description 14
- 239000002070 nanowire Substances 0.000 claims description 13
- 238000013461 design Methods 0.000 claims description 11
- 239000010703 silicon Substances 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- 238000004528 spin coating Methods 0.000 claims description 9
- 238000003486 chemical etching Methods 0.000 claims description 8
- 238000005516 engineering process Methods 0.000 claims description 8
- 230000008021 deposition Effects 0.000 claims description 7
- 238000010894 electron beam technology Methods 0.000 claims description 7
- 238000001312 dry etching Methods 0.000 claims description 6
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 claims description 6
- 230000037361 pathway Effects 0.000 claims description 6
- 238000001259 photo etching Methods 0.000 claims description 6
- 238000011161 development Methods 0.000 claims description 4
- 238000002128 reflection high energy electron diffraction Methods 0.000 claims description 4
- 238000000137 annealing Methods 0.000 claims description 3
- 238000011065 in-situ storage Methods 0.000 claims description 3
- 238000012544 monitoring process Methods 0.000 claims description 3
- 239000012298 atmosphere Substances 0.000 claims description 2
- 230000008878 coupling Effects 0.000 claims description 2
- 238000010168 coupling process Methods 0.000 claims description 2
- 238000005859 coupling reaction Methods 0.000 claims description 2
- 238000004151 rapid thermal annealing Methods 0.000 claims description 2
- 238000000233 ultraviolet lithography Methods 0.000 claims description 2
- 238000000609 electron-beam lithography Methods 0.000 abstract description 4
- 238000010923 batch production Methods 0.000 abstract description 2
- 230000005855 radiation Effects 0.000 abstract description 2
- 230000006798 recombination Effects 0.000 abstract description 2
- 238000005215 recombination Methods 0.000 abstract description 2
- 230000009467 reduction Effects 0.000 abstract description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 22
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 22
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 13
- 238000010586 diagram Methods 0.000 description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 238000000407 epitaxy Methods 0.000 description 9
- 229910002704 AlGaN Inorganic materials 0.000 description 8
- 238000005566 electron beam evaporation Methods 0.000 description 7
- 229910052757 nitrogen Inorganic materials 0.000 description 7
- 238000001755 magnetron sputter deposition Methods 0.000 description 6
- 239000000377 silicon dioxide Substances 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 230000003628 erosive effect Effects 0.000 description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 238000004140 cleaning Methods 0.000 description 4
- 230000007246 mechanism Effects 0.000 description 4
- 229910017083 AlN Inorganic materials 0.000 description 3
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- 238000005979 thermal decomposition reaction Methods 0.000 description 3
- 238000010792 warming Methods 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 2
- 239000007864 aqueous solution Substances 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 239000007853 buffer solution Substances 0.000 description 2
- 238000000605 extraction Methods 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 230000001936 parietal effect Effects 0.000 description 2
- 230000001105 regulatory effect Effects 0.000 description 2
- 238000007788 roughening Methods 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 description 1
- 244000283207 Indigofera tinctoria Species 0.000 description 1
- 240000007594 Oryza sativa Species 0.000 description 1
- 235000007164 Oryza sativa Nutrition 0.000 description 1
- XSTXAVWGXDQKEL-UHFFFAOYSA-N Trichloroethylene Chemical group ClC=C(Cl)Cl XSTXAVWGXDQKEL-UHFFFAOYSA-N 0.000 description 1
- NWAIGJYBQQYSPW-UHFFFAOYSA-N azanylidyneindigane Chemical compound [In]#N NWAIGJYBQQYSPW-UHFFFAOYSA-N 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910000238 buergerite Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000010494 dissociation reaction Methods 0.000 description 1
- 230000005593 dissociations Effects 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000004868 gas analysis Methods 0.000 description 1
- 239000010437 gem Substances 0.000 description 1
- 229910001751 gemstone Inorganic materials 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 150000002576 ketones Chemical class 0.000 description 1
- 238000004020 luminiscence type Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000002114 nanocomposite Substances 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 229910017464 nitrogen compound Inorganic materials 0.000 description 1
- 150000002830 nitrogen compounds Chemical class 0.000 description 1
- 235000012149 noodles Nutrition 0.000 description 1
- 239000005416 organic matter Substances 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 238000007781 pre-processing Methods 0.000 description 1
- 239000002096 quantum dot Substances 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 235000009566 rice Nutrition 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910002058 ternary alloy Inorganic materials 0.000 description 1
- 238000012876 topography Methods 0.000 description 1
- 229960002415 trichloroethylene Drugs 0.000 description 1
- UBOXGVDOUJQMTN-UHFFFAOYSA-N trichloroethylene Natural products ClCC(Cl)Cl UBOXGVDOUJQMTN-UHFFFAOYSA-N 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
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Abstract
The invention discloses a kind of preparation methods of lossless micro-nano structure towards micro-LED application.The present invention realizes the transfer and preparation of micron or nano-scale pattern, strong flexibility, suitable for a variety of micro-, nanodevice structural preparations by electron beam lithography；The introducing for having evaded plasma etching damage acts on the reduction of material radiation recombination efficiency, is conducive to further increase the performance in photoelectric device；Lattice selective thermal chemistry, which is carved, compares traditional semiconductor etching process, and the controllable micron in the site of acquisition or nanostructure side wall have height steepness and slickness, are not limited by etching technics, can obtain the controllable nanostructure in the site in opposed polarity face；Micro-LED is prepared using heat chemistry etching technics, no etching injury introduces, and improves device performance, while having prior art concurrently, can be realized batch production.
Description
Technical field
The present invention relates to field of semiconductor photoelectron technique, and in particular to a kind of towards the lossless micro- of micro-LED application
The preparation method of micro-nano structure.
Background technique
Low dimensional semiconductor material has very including zero-dimensional quantum dots and one-dimensional nano line and associated nanostructure
High crystal quality, excellent electrical and optical properties, are widely applied, such as high efficiency light-emitting device, MEMS
MEMS sensor, single-electron memory and single photon emission device.With the exploitation and application of semiconductor material with wide forbidden band, newly
Generation environmental type solid-state lighting light source GaN base white light LEDs have been subjected to science and technology and industrial circle is more and more paid close attention to.With
The development of semiconductor manufacturing industry, micron light emitting diode (micro-LED) is widely used, compared with traditional lighting source,
Micro-LED illumination has many advantages, such as service life length, high reliablity, small in size, low in energy consumption and be easily integrated.Plasma dry is carved
Erosion technology is a highly important technique during preparing micro-LED, for it is micro-, nanometer table top prepare it is indispensable,
It is common to have reactive ion etching RIE or coupled plasma reactive ion etching ICP-RIE.Compared to other dry etchings and chemistry
Wet etching, plasma etching have good etch rate, selection ratio, etching surface pattern and anisotropic.But
During making LED, plasma constant bombardment can cause ion dam age to the material that is etched, and directly affect micro-LED
I-V characteristic and luminescent properties.
Summary of the invention
For the above problems of the prior art, the invention proposes a kind of towards the lossless of micro-LED application
The preparation method of micro-nano structure；It is etched compared to traditional ICP, avoids the introducing of etching injury, greatly improve micro-nano knot
The intrinsic crystal quality of structure, and it is prepared for the micro-LED for having lossless table top in conjunction with conventional semiconductor devices manufacturing process, from
And improve the luminous efficiency of such micro-LED device.
An object of the present invention is to provide a kind of preparation methods of no etching injury controllable micro-nano structure.
Preparation method without etching injury controllable micro-nano structure of the invention, comprising the following steps:
1) nitride semiconductor epitaxial piece is chosen, lattice, which has, decomposes anisotropy, exist with hexagoinal lattice stable configuration,
Its oikocryst face is polar surface, and other crystal faces are semi-polarity face or non-polar plane, is located in advance to nitride semiconductor epitaxial piece
Reason, so that clean surface；
2) in nitride semiconductor epitaxial on piece deposition mask layer, mask layer uses heat-resisting material, the material of mask layer
Decomposition temperature be higher than nitride semiconductor epitaxial piece decomposition temperature；
3) according to the requirement of the controllable micro-nano structure in prepared site, design exposure domain；
4) designed exposure domain is transferred to photoresist using pattern transfer method by the spin coating photoresist on mask layer
On；
5) plasmon coupling reactive ion etching ICP technology is utilized, dry etching is carried out to mask layer, etching obtains figure
Shape exposure mask；
6) according to the lattice polarity of the size of prepared micro-nano structure, position and material, the temperature of heat chemistry etching is determined
Degree and pressure carry out lattice selective thermal chemical etching in the ultrahigh vacuum equipment of molecular beam epitaxy MBE；
7) under pattern mask protection, group III-nitride below will not be thermally decomposed, and surrounding is then divided rapidly
Solution, pattern from two dimension to it is one-dimensional excessively, and the polar crystal face of different crystalline lattice have different decomposition temperatures, have it is each to different
Property, lattice polarity determines that each crystal plane surface can be different, and under heat chemistry etching temperature and pressure, decomposition temperature is lower than heat chemistry
The crystal face of etching temperature takes the lead in decomposing, and crystal face of the decomposition temperature near heat chemistry etching temperature decomposes slowly, decomposition temperature
Crystal face greater than heat chemistry etching temperature hardly decomposes, and decomposition rate is different, and the atom of microcosmic upper decomposition is from difference
Crystal face escape, is finally taken away by the vacuum pump of MBE, and macroscopically its decomposition path-ways is by the polar regulation of lattice, control temperature and
Time finally obtains the controllable micro-nano structure in desired site, due to there is no using plasma and semiconductor material reactive ion etching,
The introducing of etching injury is evaded, and each crystal face has the nanowire structure obtained steep in strict accordance with respective path decomposing
Straight and smooth side wall；
8) it is etched away pattern mask.
Wherein, in step 1), nitride semiconductor epitaxial piece is meteorological using molecular beam epitaxy MBE or metallorganic
Prepared by the method for extension MOCVD, the substrate of nitride semiconductor epitaxial piece uses sapphire, silicon or its self-supported substrate.Nitrogen
Compound semiconductor epitaxial wafer is III group, II-VI group or III-V nitride semiconductor epitaxial wafer；Such as gallium nitride GaN, indium nitride
InN, aluminium nitride AlN or their ternary alloy three-partalloy.
In step 2), the material of mask layer uses silica or silicon nitride, and deposition method using plasma increases
Extensive chemical vapour deposition process PECVD or Chemical Vapor-Phase Epitaxy method.
In step 4), using electron beam exposure EBL method or Ultraviolet lithography, by the pattern transfer for exposing domain to covering
In film layer, if you need to retain the photoresist of non-exposed areas after exposure, development, fixing, then positive photoresist is selected, and if to retain exposure
The photoresist in light region should then select negtive photoresist, based on this principle design exposure domain.
In step 5), the figure that the micro-nano structure controllable with prepared site is etched using ICP is consistent graphical
Exposure mask, the photoresist left after exposure technology in step 4) at this time are used as the etch-resistant layer of ICP technique, and sink in step 2)
For long-pending mask layer as the material that is etched, the etching gas selected at this time will not be to the nitride semiconductor epitaxial described in step 1)
Piece causes to etch；The Patterned masking layer of formation forms protection to the surface dangling bonds of semiconductor material below, makes it in height
It is not easily decomposed under temperature, and pattern mask sheet is as heat-resisting material, and it is not patterned the semiconductor material of exposure mask overlay area
Material can gradually decompose dissociation at high temperature.
In step 6), using the MBE cavity with ultrahigh vacuum atmosphere, avoids introducing other impurities, guarantee that gained is received
Rice noodles quality have high-purity, selective thermal chemical etching refer to specific vacuum degree (pressure) and at a temperature of, mask layer
The decomposition temperature of material and nitride semiconductor epitaxial piece has larger difference；Decomposition temperature is at 750~1150 DEG C, and pressure is 1
×10-6Torr was decomposed hereinafter, micro-nano structure is the first in micron and nano-wire array and micron and nanocomposite optical microcavity
Journey can using residual gas analyzer (Residual Gas Analysis) or reflection high energy electron diffraction (RHEED) into
Row in-situ monitoring is to adjust decomposition rate.
The lossless preparation method towards micro-LED that it is another object of the present invention to provide a kind of.
Lossless preparation method towards micro-LED of the invention, comprising the following steps:
1) nitride semiconductor LED epitaxial wafer is chosen, nitride semiconductor LED epitaxial wafer sequentially consists of substrate, N
Type doped layer, luminescent active region and p-type doped layer, the lattice of nitride semiconductor LED epitaxial wafer, which has, decomposes anisotropy, main
Crystal face is polar surface, and other crystal faces are semi-polarity face or non-polar plane, is located in advance to nitride semiconductor LED epitaxial wafer
Reason, so that clean surface；
2) in nitride semiconductor epitaxial on piece elder generation deposited metal, redeposited mask layer, mask layer uses heat-resisting material,
The decomposition temperature of the material of mask layer is higher than the decomposition temperature of nitride semiconductor epitaxial piece；
3) according to the requirement of prepared micro-LED mesa array, design exposure domain；
4) designed exposure domain is transferred to photoresist using pattern transfer method by the spin coating photoresist on mask layer
On；
5) it according to the positions and dimensions of institute's micro-LED mesa array, determines etching condition, dry method quarter is carried out to mask layer
Erosion obtains pattern mask；
6) according to the lattice polarity of the size of prepared micro-LED mesa array, position and material, annealing temperature is determined
Degree carries out lattice selective thermal chemical etching in MBE ultrahigh vacuum equipment；
7) under the protection of pattern mask, the nitride semiconductor LED epitaxial wafer under pattern mask will not occur
Thermal decomposition, around then rapidly decompose, pattern from two dimension to it is one-dimensional excessively, by control heat chemistry etching temperature and time,
Desired micro-LED mesa array is obtained, and has evaded introducing etching injury, in heat chemistry etching process, by temperature tune
To the temperature for forming Ohmic contact and the time is controlled, so that the metal of deposition and p-type doped layer are formed simultaneously p-type Ohmic contact；
8) it is etched away pattern mask；
9) depositing insulating layer；
10) photoetching windowing at N-type electrode, deposited metal are being needed to form, rapid thermal annealing forms N-type electrode and is formed simultaneously
N-type Ohmic contact；
11) photoetching windowing at P-type electrode is being needed to form, deposited metal forms P-type electrode, and in P-type electrode and N-type
Deposited metal forms interconnecting electrode between electrode；
12) roughing in surface is carried out to the back side of nitride semiconductor LED epitaxial wafer.
Wherein, in step 1), nitride semiconductor LED epitaxial wafer uses gallium nitride based nitride semiconductor epitaxial wafer；
Select the emission wavelength of nitride semiconductor LED epitaxial wafer adjustable for 300nm~500nm according to application demand.
In step 2), deposited metal, redeposition in p-type doped layer using electron beam evaporation method or magnetron sputtering method
Mask material resistant to high temperature, mask material resistant to high temperature use SiN or SiO2。
In step 3), the figure of design is PIN type micro-LED table top.
In step 4), graphical transfer method selects negative photo using ultraviolet photolithographic either electron beam exposure EBL
Glue, mesa region still retains photoresist after developing fixing, other regions are then the heat-resisting material deposited in step 2).
In step 5), using the photoresist left after developing fixing in step 4) as etch-resistant layer, carried out using ICP
Etching removes metal and mask layer outside mesa region, realizes the primary transfer of figure, this process etching gas is not to nitride
Semiconductor LED epitaxial wafer causes to etch.
In step 6), the plane of crystal energy anisotropy using the polarity driven of lattice regulates and controls heat chemistry etching process,
Basic law are as follows: under heat chemistry etching temperature and pressure, slower, semi-polarity face or non-polar plane decomposition rate are decomposed in oikocryst face
Comparatively fast.
In step 8), during obtaining micro-LED mesa array using selective thermal chemical etching, formed
At a temperature of Ohmic contact, the metal and p-type doped layer of deposition form p-type Ohmic contact, this process and utilization quick anneal oven shape
It is consistent at the principle of Ohmic contact.
In step 9), insulating layer is silica, silicon nitride or aluminium nitride material, and deposition method is electron beam evaporation
Or magnetron sputtering.
In step 10), the metal of deposited n-type electrode uses electron beam evaporation method or magnetron sputtering method.
In step 11), the metal and interconnecting electrode for depositing P-type electrode are using electron beam evaporation method or magnetron sputtering
Method,.
In step 10) and step 11), photoetching windowing, which refers to, selects opening area using photoetching, and dry method is recycled to carve
The method of erosion or chemical attack exposes window.
In step 12), the back of the method for dry etching or wet etching roughening nitride semiconductor LED epitaxial wafer is utilized
Face, to improve the light extraction efficiency of micro-LED.
Advantages of the present invention:
The present invention realizes the transfer and preparation of micron or nano grade figure by electron beam lithography, and strong flexibility is fitted
For a variety of micro-, nanodevice structural preparations；The introducing of plasma etching damage is evaded to material radiation recombination efficiency
Reduction effect, be conducive to further increase the performance in photoelectric device；Lattice selective thermal chemistry is carved partly leads compared to traditional
Body etching technics, the controllable micron in the site of acquisition or nanostructure side wall have height steepness and slickness, are not etched
Technique limitation, can obtain the controllable nanostructure in the site in opposed polarity face；Micro- is prepared using heat chemistry etching technics
LED, no etching injury introduce, and improve device performance, while having prior art concurrently, can be realized batch production.
Detailed description of the invention
Fig. 1 be no etching injury controllable nano structure according to the present invention preparation method embodiment one obtain
(0001) structural schematic diagram of the nitride semiconductor epitaxial piece obtained after epitaxial nitride silicon on the GaN of face；
Fig. 2 is that electronics is utilized in the embodiment one of the preparation method of no etching injury controllable nano structure according to the present invention
Partial schematic diagram after beam exposure, wherein (a) is top view, (b) is side view；
Fig. 3 is that ICP is utilized in the embodiment one of the preparation method of no etching injury controllable nano structure according to the present invention
Partial schematic diagram after etch silicon nitride mask layer, wherein (a) is top view, (b) is side view；
Fig. 4 is that heat chemistry is carved in the embodiment one of the preparation method of no etching injury controllable nano structure according to the present invention
The schematic diagram of erosion process, C are the decomposition direction of nonpolar face GaN atom, and B is the decomposition direction of polar surface GaN atom；
Fig. 5 is that heat chemistry is carved in the embodiment one of the preparation method of no etching injury controllable nano structure according to the present invention
The partial schematic diagram of the nano-wire array obtained after erosion, (a) are top view, (b) are side view；
Fig. 6 is cvd nitride in the embodiment two of the preparation method of no etching injury controllable nano structure according to the present invention
Schematic diagram after silicon mask layer；
Fig. 7 is had in the embodiment two for the preparation method of no etching injury controllable nano structure according to the present invention
The partial schematic diagram of AlGaN annulus Echo Wall micro-cavity structure, (a) are top view, are (b) section along figure (a) along A-A ' line
Figure；
Fig. 8 is had in the embodiment three for the preparation method of no etching injury controllable nano structure according to the present invention
The schematic diagram of nitride semiconductor LED epitaxial wafer and metal and mask layer,；
Fig. 9 is had in the embodiment three for the preparation method of no etching injury controllable nano structure according to the present invention
The partial schematic diagram of pattern mask；
Figure 10 is heat chemistry in the embodiment three of the preparation method of no etching injury controllable nano structure according to the present invention
The structural schematic diagram of the micro-LED mesa array obtained after etching；
Figure 11 prepares N-type in the embodiment three for the preparation method of no etching injury controllable nano structure according to the present invention
Schematic diagram after electrode；
Figure 12 prepares p-type in the embodiment three for the preparation method of no etching injury controllable nano structure according to the present invention
Schematic diagram after electrode and interconnecting electrode；Figure 13 is the preparation method of no etching injury controllable nano structure according to the present invention
Embodiment three in overall structure diagram after roughing in surface.
Specific embodiment
With reference to the accompanying drawing, by specific embodiment, the present invention is further explained.
Embodiment one
In the present embodiment, nitride semiconductor epitaxial piece uses GaN epitaxy piece；The material of mask layer is silicon nitride；Nanometer
The figure of structure uses periodic column two-dimensional lattice, and graph transfer method uses electron beam exposure；Heat chemistry etching process
It is carried out in ultrahigh vacuum chamber, hot etching process carries out in-situ monitoring using reflection high energy electron diffraction RHEED.
The preparation method of the nanostructure controllable without the site etching injury GaN of the present embodiment, comprising the following steps:
1) it chooses using sapphire as the gallium nitride epitaxial slice of substrate:
Buergerite GaN is greater than edge along [0001] Directional Decomposition rateWithThe decomposition rate in direction, selection
(0001) face GaN is as substrate, so thatWithDirection is conducive to be decomposed thermally to form metal-polar in substrate surface
The controllable nanostructure in site.Gallium nitride epitaxial slice is pre-processed, keeps substrate surface clean.
2) deposited silicon nitride mask layer:
Mechanism is etched according to heat chemistry, selects silicon nitride as mask material, utilizes electron beam evaporation technique cvd nitride
Silicon epitaxy 1-3.Since the decomposition temperature of silicon nitride in a vacuum is much higher than epitaxial layer of gallium nitride 1-2, nitridation can use
Silicon is the epitaxial layer of gallium nitride 1-2 of exposure mask protection below and will not thermally decompose, and the epitaxial layer of gallium nitride 1-2 of surrounding is according to lattice
Selective thermal is decomposed regulating effect and is gradually decomposed, and achievees the effect that heat chemistry etches.
3) according to the requirement of the controllable nanostructure in the site no etching injury GaN, design exposure domain.
4) spin coating negativity electron beam resist is schemed using electron beam lithography by pattern transfer to silicon nitride mask
Shape be the cylindric two-dimensional lattice equidistantly arranged, the distance between adjacent two o'clock be T=3 um, diameter D=500 nm, show
Effect after shadow fixing is as shown in Fig. 2, wherein 1-1 is sapphire substrates, and 1-2 is epitaxial layer of gallium nitride, and 1-3 is nitridation silicon epitaxy,
1-4 is electron beam resist.
5) etching mask layer obtains pattern mask:
Silicon nitride is performed etching using photoresist as exposure mask, obtains silicon nitride patterned cathode, as shown in figure 3, its
Middle 1-1 is sapphire substrates, and 1-2 is epitaxial layer of gallium nitride, and 1-3 is nitridation silicon epitaxy.And pattern mask substrate is carried out pre-
Processing, makes the clean surface of pattern mask substrate:
Firstly, chemically cleaning patterned substrate, remaining electron beam resist is removed, trichloro ethylene, third are used
Ketone, alcohol are slightly ultrasonic, so that the surface cleaning of pattern mask substrate；Then, pattern mask substrate is sent to MBE system
System is warming up to about 500 DEG C, toasts 10~30min, removes surface residual organic matter and vapor；
6) according to the diameter of aligned nanowires and length, the temperature range of heat chemistry etching is determined:
Rule and ultrahigh vacuum chamber pressure-temperature are thermally decomposed to nitride material decomposition temperature according to lattice polarity driven
Influencing mechanism, determine suitable resolver temperature-pressure section, the decomposition temperature of gallium-nitride metal polar surface in MBE equipment
Spending section is 650~720 DEG C, and N polar surface is then 750 DEG C~850 DEG C.Polar surface decomposition rate is about in temperature range
Vpolarity=12nm/min, non-polar plane decomposition rate are about Vnon-polarity=2nm/min, decomposable process such as Fig. 4
Shown, wherein 1-1 is sapphire substrates, and 1-2 is epitaxial layer of gallium nitride, and 1-3 is nitridation silicon epitaxy, and A is GaN polarity face
Decomposition path-ways, B are the decomposition path-ways in GaN polarity face.
7) under pattern mask protection, group III-nitride below will not be thermally decomposed, and surrounding is then divided rapidly
Solution, pattern from two dimension to it is one-dimensional excessively, and the polar crystal face of different crystalline lattice have different decomposition temperatures, have it is each to different
Property, lattice polarity determines that each crystal plane surface can be different, and under heat chemistry etching temperature and pressure, decomposition temperature is lower than heat chemistry
The crystal face of etching temperature takes the lead in decomposing, and crystal face of the decomposition temperature near heat chemistry etching temperature decomposes slowly, decomposition temperature
Crystal face greater than heat chemistry etching temperature hardly decomposes, and decomposition rate is different, and the atom of microcosmic upper decomposition is from difference
Crystal face escape, is finally taken away by the vacuum pump of MBE, and macroscopically its decomposition path-ways is by the polar regulation of lattice, control temperature and
Time finally obtains the controllable nanostructure in desired site, due to there is no using plasma and semiconductor material reactive ion etching,
The introducing of etching injury is evaded, and each crystal face has the nanowire structure obtained steep in strict accordance with respective path decomposing
Straight and smooth side wall.
8) exposure mask is removed:
After selective thermal chemical etching process, sample is taken out from MBE cavity, in the controllable nano junction in site
Also there are mask layers at the top of structure, and 3min is impregnated in HF aqueous solution or HF buffer solution BOE and is removed it, while making gained sample
Product clean surface, gained gallium nitride nano-wire is metal-polar, therefore the pointed pattern of the symmetrical pyramid of six sides is presented, such as Fig. 5 institute
Show, wherein 1-1 is sapphire substrates, and 1-5 is the gallium nitride nano-wire array without etching injury that preparation is completed.This method preparation
The controllable aligned nanowires of gallium nitride have excellent surface topography and crystal quality, scanning electron microscope SEM test shows
Nanowire sidewalls are steep, smooth, and decomposition rate of the nano wire along [0001] direction is apparently higher thanDirection, transmitted electron are aobvious
Micro mirror shows to decompose side wall without etching injury, and crystal quality is excellent.
Embodiment two
Without etching injury Echo Wall microcavity LED in the present embodiment, as shown in fig. 6, first using MOCVD or MBE in indigo plant
In (Ga)/GaN multiple quantum wells LED structure 2-2, then N layers of the extension 3umAl (Ga) again in LED structure are grown on jewel substrate 1-1
2-3, then deposition is for thermally decomposing the silicon nitride mask 2-4, last spin coating negativity ultraviolet photoresist 2-5 of etching.
The present embodiment without etching injury Echo Wall microcavity LED preparation method, comprising the following steps:
1) LED structure sample is prepared:
Using MOCVD MBE method, successively extension GaN, InGaN/GaN multiple quantum wells, GaN are covered on a sapphire substrate
Layer, according to emission wavelength adjustment multiple quantum well layer InGaN well layer In component and its thickness with GaN barrier layer.
2) extension echo parietal layer and silicon nitride mask layer:
According to the luminescence band of the LED of above-mentioned design and model selection, Al (Ga) N for designing Al component 0~0.3 makees
For echo wall material, while this layer of AlGaN can also further increase the luminous efficiency of multiple quantum wells as electronic barrier layer.Technique
Process is as follows, uses MBE MOCVD method AlGaN first；Then, according to heat chemistry etch mechanism, select silicon nitride as
Mask material.Due to the far high AlGaN of the decomposition temperature of silicon nitride in a vacuum, doing exposure mask using silicon nitride be can protect below
Al (Ga) N echo parietal layer will not thermally decompose, and nitrogen Al (Ga) the N material of surrounding along lattice selective thermal decompose regulating effect by
It gradually decomposes, achievees the effect that heat chemistry etches.To deposited silicon nitride and Al (Ga) N LED sample pre-processes, make substrate
Clean surface.
3) according to the requirement of Echo Wall micro-cavity structure, design configuration is extremely nitrogenized pattern transfer using ultraviolet photolithographic technology
On silicon exposure mask, figure is Echo Wall concentric annular, Echo Wall cavity internal diameter d=1um, outer diameter D=1.1um, wall thickness W=D-d=
100nm, Echo Wall cavity cycle T=1um.
4) spin coating negativity ultraviolet photoresist, etching mask layer obtain pattern mask:
After developing fixing, ICP etching is carried out to silicon nitride as exposure mask using residual photoresist, is obtained and Echo Wall knot
The consistent nitrogen pattern mask of structure exposure figure.Pattern mask substrate is pre-processed, the table of pattern mask substrate is made
Face is clean:
Firstly, patterned substrate is chemically cleaned, so that the surface cleaning of pattern mask substrate；Then, will scheme
Shape mask substrate is warming up to about 500 DEG C, toasts 10~30min.
5) according to the structural parameters of Echo Wall micro-cavity structure, the temperature range of heat chemistry etching is determined:
Rule and ultrahigh vacuum chamber pressure-temperature are thermally decomposed to nitride material decomposition temperature according to lattice polarity driven
Influencing mechanism, determine suitable resolver temperature-pressure section, in MBE equipment, temperature is decomposed in the metal-polar face of AlGaN
Spending section is 850~920 DEG C, and N polar surface is then 950 DEG C~1000 DEG C.Polar surface decomposition rate is about in temperature range
Vpolarity=10nm/min, non-polar plane decomposition rate are about Vnon-polarity=3nm/min.
6) after selective thermal chemical etching process, sample is taken out from MBE cavity, using HF aqueous solution or
HF buffer solution BOE removes remaining silicon nitride mask, as shown in fig. 7, wherein 1-1 is sapphire substrates, 2-2 is final structure
In (Ga)/GaN multiple quantum wells LED structure, 2-6 are AlGaN Echo Wall microcavity, and D is the outer diameter of AlGaN Echo Wall microcavity, and d is
The internal diameter of AlGaN Echo Wall microcavity.
7) under pattern mask protection, group III-nitride below will not be thermally decomposed, and surrounding is then divided rapidly
Solution, pattern from two dimension to it is one-dimensional excessively, and the polar crystal face of different crystalline lattice have different decomposition temperatures, have it is each to different
Property, lattice polarity determines that each crystal plane surface can be different, and under heat chemistry etching temperature and pressure, decomposition temperature is lower than heat chemistry
The crystal face of etching temperature takes the lead in decomposing, and crystal face of the decomposition temperature near heat chemistry etching temperature decomposes slowly, decomposition temperature
Crystal face greater than heat chemistry etching temperature hardly decomposes, and decomposition rate is different, and the atom of microcosmic upper decomposition is from difference
Crystal face escape, is finally taken away by the vacuum pump of MBE, and macroscopically its decomposition path-ways is by the polar regulation of lattice, control temperature and
Time finally obtains the controllable nanostructure in desired site, due to there is no using plasma and semiconductor material reactive ion etching,
The introducing of etching injury is evaded, and each crystal face has the nanowire structure obtained steep in strict accordance with respective path decomposing
Straight and smooth side wall.
8) it is etched away pattern mask.
This method obtain Echo Wall micro-cavity structure have steep, smooth side wall, do not introduce etching injury, have compared with
High crystal quality, scanning electron microscope SEM test show that nanowire sidewalls are steep, smooth, and transmission electron microscope shows
Side wall is decomposed without etching injury, crystal quality is excellent.
Embodiment three
In the present embodiment, a kind of lossless preparation method towards GaN base micro-LED is provided, comprising the following steps:
1) high-quality gallium nitride base LED epitaxial wafer is prepared:
As shown in figure 8, firstly, successively being grown outside N-type GaN on sapphire substrates 1-1 using MOCVD MBE method
Prolong 3-2, InGaN/GaN multiple quantum well layer 3-3, p-type GaN layer 3-4.
2) then, using electron beam evaporation technique deposited metal layer 3-5 and silicon nitride mask layer 3-6, last spin coating negativity
Ultraviolet photoresist 3-7.
3): being required according to micro-LED mesa array, design exposure domain.
4) designed domain is transferred to using ultraviolet photolithographic technology and has been deposited on SiN mask layer, spin coating negativity is ultraviolet
Photoresist, using residual photoresist as exposure mask after developing fixing.
5) using plasma dry etching technology obtains the sample with exposure mask table top, obtains patterned substrate.Figure
For with equidistant cylindrical array, rotary table diameter D=2um, cycle T=5um uses acetone removal photoresist to obtain exposure mask
Table top, as shown in figure 9, wherein 1-1 is sapphire substrates, 3-2 is N-type GaN epitaxy, and 3-3 is InGaN/GaN multiple quantum well layer,
3-4 is p-type GaN layer, and 3-5 is metal layer, and 3-8 is the silicon nitride mask table top that etching obtains.To the sample with exposure mask table top
It is pre-processed, keeps clean sample surfaces clean:
Firstly, patterned substrate is chemically cleaned, so that the surface cleaning of pattern mask substrate；Then, will scheme
Shape mask substrate is warming up to about 300 DEG C, toasts 10~30min.
6) according to the diameter and length of micro-LED table top, the temperature range of heat chemistry etching is determined:
Thermal decomposition etching is carried out in MBE cavity, selects temperature range at 680~800 DEG C.
7) under the protection of pattern mask, the nitride semiconductor LED epitaxial wafer under pattern mask will not occur
Thermal decomposition, around then rapidly decompose, pattern from two dimension to it is one-dimensional excessively, by control heat chemistry etching temperature and time,
Desired micro-LED mesa array is obtained, and has evaded introducing etching injury, in heat chemistry etching process, by temperature tune
To the temperature for forming Ohmic contact and the time is controlled, so that the metal of deposition and p-type doped layer are formed simultaneously p-type Ohmic contact.
8) after taking out sample in MBE, remaining silicon nitride mask is removed using ICP Etch selectivity quarter, this process is to non-
For silicon nitride material without influence, final effect is as shown in Figure 10, and wherein 1-1 is sapphire substrates, and 3-2 is N-type GaN epitaxy, and 3-3 is
InGaN/GaN multiple quantum well layer, 3-4 are p-type GaN layer, and 3-5 is metal layer；
9) depositing insulating layer；
10) firstly, using ultraviolet photolithographic in the non-mesa region aperture of N-type GaN.Then, magnetron sputtering deposited metal is utilized.
Then, using photoresist solvent stripping photoresist, metal is only left at window.It is carried out in the annealing furnace of nitrogen atmosphere again fast
Speed heat anneals to form Ohmic contact, obtains N-type electrode, and as shown in figure 11, wherein 1-1 is sapphire substrates, and 3-2 is outside N-type GaN
Prolong, 3-3 is InGaN/GaN multiple quantum well layer, and 3-4 is p-type GaN layer, and 3-5 is metal layer, and 3-9 is N-type electrode；
11) cvd silicon oxide insulating layer, production P, N interconnecting electrode:
Using electron beam evaporation technique on acquired table top sample depositing insulating layer silica, at P-type electrode
Using plasma etching or wet etching aperture, then using magnetron sputtering evaporation metal connection p-type and N-type electrode, such as scheme
Shown in 12, wherein 1-1 is sapphire substrates, and 3-2 is N-type GaN epitaxy, and 3-3 is InGaN/GaN multiple quantum well layer, and 3-4 is p-type
GaN layer, 3-5 are metal layer, and 3-9 is N-type electrode, and 3-11 is silicon dioxide insulating layer, 3-12 P, N interconnecting electrode.
12) roughing in surface:
It being thinned at the back side N-type GaN, is roughened, further increase light extraction efficiency, final structure is as shown in figure 13, wherein
1-1 is sapphire substrates, and 3-2 is N-type GaN epitaxy, and 3-3 is InGaN/GaN multiple quantum well layer, and 3-4 is p-type GaN layer, and 3-5 is
Metal layer, 3-9 are N-type electrode, and 3-11 is silicon dioxide insulating layer, and 3-12 P, N interconnecting electrode, 3-13 is the substrate after roughening
Back.
It is finally noted that the purpose for publicizing and implementing example is to help to further understand the present invention, but this field
Technical staff be understood that without departing from the spirit and scope of the invention and the appended claims, it is various replacement and repair
It is all possible for changing.Therefore, the present invention should not be limited to embodiment disclosure of that, and the scope of protection of present invention is to weigh
Subject to the range that sharp claim defines.
Claims (10)
1. a kind of preparation method of no etching injury controllable micro-nano structure, which is characterized in that the preparation method includes following step
It is rapid:
1) nitride semiconductor epitaxial piece is chosen, lattice, which has, decomposes anisotropy, with the presence of hexagoinal lattice stable configuration, master
Crystal face is polar surface, and other crystal faces are semi-polarity face or non-polar plane, pre-processes, makes to nitride semiconductor epitaxial piece
Obtain clean surface；
2) in nitride semiconductor epitaxial on piece deposition mask layer, mask layer uses heat-resisting material, point of the material of mask layer
Solve the decomposition temperature that temperature is higher than nitride semiconductor epitaxial piece；
3) according to the requirement of the controllable micro-nano structure in prepared site, design exposure domain；
4) designed exposure domain is transferred on photoresist by the spin coating photoresist on mask layer using pattern transfer method；
5) plasmon coupling reactive ion etching ICP technology is utilized, dry etching is carried out to mask layer, etching obtains graphical
Exposure mask；
6) according to the lattice polarity of the size of prepared micro-nano structure, position and material, determine heat chemistry etching temperature and
Pressure carries out lattice selective thermal chemical etching in the ultrahigh vacuum equipment of molecular beam epitaxy MBE；
7) under pattern mask protection, group III-nitride below will not be thermally decomposed, and surrounding is then decomposed rapidly,
From two dimension to one-dimensional, excessively and the polar crystal face of different crystalline lattice has different decomposition temperatures to pattern, has anisotropy, brilliant
Lattice polarity determines that each crystal plane surface can be different, and under heat chemistry etching temperature and pressure, decomposition temperature is etched lower than heat chemistry
The crystal face of temperature takes the lead in decomposing, and crystal face of the decomposition temperature near heat chemistry etching temperature decomposes slowly, and decomposition temperature is greater than
The crystal face of heat chemistry etching temperature hardly decomposes, and decomposition rate is different, the never same crystal face of the atom of microcosmic upper decomposition
Escape, is finally taken away by the vacuum pump of MBE, and macroscopically its decomposition path-ways is controlled temperature and time by the polar regulation of lattice,
The controllable micro-nano structure in desired site is finally obtained, due to not having using plasma and semiconductor material reactive ion etching, is evaded
The introducing of etching injury, and each crystal face is in strict accordance with respective path decomposing, make the nanowire structure obtained have it is steep and
Smooth side wall；
8) it is etched away pattern mask.
2. preparation method as described in claim 1, which is characterized in that in step 1), nitride semiconductor epitaxial piece is used
The preparation of the method for molecular beam epitaxy MBE or metallorganic meteorology extension MOCVD, the substrate of nitride semiconductor epitaxial piece are adopted
With sapphire, silicon or its self-supported substrate；Nitride semiconductor epitaxial piece is III group, II-VI group or III-V nitride
Semiconductor epitaxial wafer.
3. preparation method as described in claim 1, which is characterized in that in step 4), using electron beam exposure EBL method or
Ultraviolet lithography, by the pattern transfer to mask layer for exposing domain, if need to retain after exposure, development, fixing non-exposed
The photoresist in region, then select positive photoresist；And if to retain the photoresist of exposure area, negtive photoresist should be selected.
4. preparation method as described in claim 1, which is characterized in that in step 6), using with ultrahigh vacuum atmosphere
MBE cavity, decomposition temperature is at 750~1150 DEG C, and pressure is 1 × 10-6Below.
5. preparation method as described in claim 1, which is characterized in that in step 6), decomposable process utilizes residual gas point
Analyzer or reflection high energy electron diffraction carry out in-situ monitoring to adjust decomposition rate.
6. a kind of lossless preparation method towards micro-LED as described in claim 1, which is characterized in that the lossless system
Preparation Method the following steps are included:
1) nitride semiconductor LED epitaxial wafer is chosen, nitride semiconductor LED epitaxial wafer sequentially consists of substrate, N-type is mixed
Diamicton, luminescent active region and p-type doped layer, the lattice of nitride semiconductor LED epitaxial wafer, which has, decomposes anisotropy, oikocryst face
For polar surface, other crystal faces are semi-polarity face or non-polar plane, pre-process, make to nitride semiconductor LED epitaxial wafer
Obtain clean surface；
2) in nitride semiconductor epitaxial on piece elder generation deposited metal, redeposited mask layer, mask layer is using heat-resisting material, exposure mask
The decomposition temperature of the material of layer is higher than the decomposition temperature of nitride semiconductor epitaxial piece；
3) according to the requirement of prepared micro-LED mesa array, design exposure domain；
4) designed exposure domain is transferred on photoresist by the spin coating photoresist on mask layer using pattern transfer method；
5) it according to the positions and dimensions of institute's micro-LED mesa array, determines etching condition, dry etching is carried out to mask layer,
Obtain pattern mask；
6) according to the lattice polarity of the size of prepared micro-LED mesa array, position and material, annealing temperature is determined,
Lattice selective thermal chemical etching is carried out in MBE ultrahigh vacuum equipment；
7) under the protection of pattern mask, heat point will not occur for the nitride semiconductor LED epitaxial wafer under pattern mask
Solution, around then rapidly decompose, pattern from two dimension to it is one-dimensional excessively, pass through control heat chemistry etching temperature and time, obtain
Desired micro-LED mesa array, and evaded introducing etching injury, in heat chemistry etching process, adjust the temperature to shape
At Ohmic contact temperature and control the time so that deposition metal and p-type doped layer be formed simultaneously p-type Ohmic contact；
8) it is etched away pattern mask；
9) depositing insulating layer；
10) photoetching windowing at N-type electrode, deposited metal are being needed to form, rapid thermal annealing forms N-type electrode and is formed simultaneously N-type
Ohmic contact；
11) photoetching windowing at P-type electrode is being needed to form, deposited metal forms P-type electrode, and in P-type electrode and N-type electrode
Between deposited metal formed interconnecting electrode；
12) roughing in surface is carried out to the back side of nitride semiconductor LED epitaxial wafer.
7. lossless preparation method as claimed in claim 6, which is characterized in that in step 1), nitride semiconductor LED extension
Piece uses gallium nitride based nitride semiconductor epitaxial wafer；Shining for nitride semiconductor LED epitaxial wafer is selected according to application demand
Wavelength is that 300nm~500nm is adjustable.
8. lossless preparation method as claimed in claim 6, which is characterized in that in step 3), the figure of design is PIN type
Micro-LED table top.
9. lossless preparation method as claimed in claim 6, which is characterized in that fixed using development in step 4) in step 5)
The photoresist that movie queen leaves is performed etching as etch-resistant layer using ICP, and metal and mask layer outside mesa region are removed, real
The primary transfer of existing figure, this process etching gas do not cause to etch to nitride semiconductor LED epitaxial wafer.
10. lossless preparation method as claimed in claim 6, which is characterized in that in step 6), utilize the polarity driven of lattice
Plane of crystal energy anisotropy regulate and control heat chemistry etching process, basic law are as follows: it is main under heat chemistry etching temperature and pressure
Crystal face decomposition is slower, and semi-polarity face or non-polar plane decomposition rate are very fast.
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| CN111029446A (en) * | 2019-12-12 | 2020-04-17 | 电子科技大学 | Quantum dot single photon source and preparation method thereof |
| CN113903762A (en) * | 2021-10-08 | 2022-01-07 | 中紫半导体科技(东莞)有限公司 | Deep ultraviolet array interconnection micro-LED and preparation method thereof |
| CN114300501A (en) * | 2021-12-24 | 2022-04-08 | 湖南大学 | micro-LED in-situ driving unit manufacturing method and micro-LED device |
| CN114975700A (en) * | 2022-08-01 | 2022-08-30 | 北京大学 | Preparation and lossless interface separation method of nitride LED |
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| KR20160019679A (en) * | 2014-08-12 | 2016-02-22 | 엘지이노텍 주식회사 | Light emitting device and lighting system |
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| CN103199004A (en) * | 2013-02-22 | 2013-07-10 | 国家纳米科学中心 | Manufacturing method of III-group nitride nano-structure |
| KR20160019679A (en) * | 2014-08-12 | 2016-02-22 | 엘지이노텍 주식회사 | Light emitting device and lighting system |
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| CN113903762A (en) * | 2021-10-08 | 2022-01-07 | 中紫半导体科技(东莞)有限公司 | Deep ultraviolet array interconnection micro-LED and preparation method thereof |
| CN113903762B (en) * | 2021-10-08 | 2022-10-21 | 松山湖材料实验室 | Deep ultraviolet array interconnection micro-LED and preparation method thereof |
| CN114300501A (en) * | 2021-12-24 | 2022-04-08 | 湖南大学 | micro-LED in-situ driving unit manufacturing method and micro-LED device |
| CN114300501B (en) * | 2021-12-24 | 2023-01-03 | 湖南大学 | micro-LED in-situ driving unit manufacturing method and micro-LED device |
| CN114975700A (en) * | 2022-08-01 | 2022-08-30 | 北京大学 | Preparation and lossless interface separation method of nitride LED |
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