CN109427932A - LED epitaxial slice and its manufacturing method - Google Patents

LED epitaxial slice and its manufacturing method Download PDF

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Publication number
CN109427932A
CN109427932A CN201710739994.2A CN201710739994A CN109427932A CN 109427932 A CN109427932 A CN 109427932A CN 201710739994 A CN201710739994 A CN 201710739994A CN 109427932 A CN109427932 A CN 109427932A
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layer
gan
grown
epitaxial wafer
sapphire substrate
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CN109427932B (en
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谢春林
项博媛
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BYD Semiconductor Co Ltd
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BYD Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/12—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer

Abstract

This disclosure relates to a kind of LED epitaxial slice and its manufacturing method.The described method includes: providing a Sapphire Substrate (1), and GaN intrinsic layer (2), GaN n-layer (3), luminescent layer (4) and GaN p-type layer (5) are successively grown on the Sapphire Substrate (1), the growth stress adjustment layer (6) between the Sapphire Substrate (1) and the GaN n-layer (3), wherein, the lattice constant of the Stress relief layer (6) is between sapphire and GaN.The lattice mismatch between sapphire and GaN can be reduced in this way, to reduce the warpage that epitaxial wafer occurs during the growth process and after the completion of growth, improve the performance of extension flake products.

Description

LED epitaxial slice and its manufacturing method
Technical field
This disclosure relates to field of semiconductor manufacture, and in particular, to a kind of LED epitaxial slice and its manufacturing method.
Background technique
Light emitting diode (light emitting diode, LED) is a kind of knot that can convert the electrical signal to optical signal Type electroluminescent semiconductor devices.Gallium nitride (GaN) based light-emitting diode as solid state light emitter once appearance, just with its efficiently Rate, the long-life, energy conservation and environmental protection, it is small in size the advantages that be known as after the Edison invented electric light mankind and illuminate removing from office again in history Life, it has also become international semiconductor and lighting area research and development and industry focus of attention.
Wherein, with gallium nitride (GaN), InGaN (InGaN), aluminium gallium nitride alloy (AlGaN) and indium nitride gallium aluminium (AlGaInN) the direct bandwidth of the III-V nitride material based on is 0.7~6.2eV, is covered from ultraviolet light to infrared light Spectral region, be manufacture blue and green light and white light emitting device ideal material.
In general, the epitaxial wafer of GaN base light emitting, can using sapphire as substrate, on a sapphire substrate according to Secondary generation GaN intrinsic layer, GaN n-layer, luminescent layer and GaN p-type layer.
Summary of the invention
Purpose of this disclosure is to provide a kind of high performance LED epitaxial slice and its manufacturing methods.
Since GaN LED generallys use sapphire as substrate, and there are the mistakes of biggish lattice between sapphire and GaN Match, cause there are biggish stress inside GaN epitaxial layer, these stress make epitaxial layer during the growth process and growth is completed After warpage may occur.On the one hand warpage leverages the performances such as brightness, the wavelength of epitaxial wafer, on the other hand also result in The case where being ruptured in LED chip manufacturing process.And the size of epitaxial wafer is bigger, and this warpage is more serious.How to reduce The warpage degree of epitaxial wafer improves wavelength and brightness yield, becomes the key of epitaxial layer development.Inventor expects, Ke Yi Layer lattice constant Stress relief layer between sapphire and GaN is grown between Sapphire Substrate and GaN n-layer, to reduce Lattice mismatch between sapphire and GaN.
To achieve the goals above, the disclosure provides a kind of manufacturing method of LED epitaxial slice.The method packet It includes: a Sapphire Substrate, and successively long GaN intrinsic layer, GaN n-layer, luminescent layer and the GaN in the Sapphire Substrate is provided P-type layer, the growth stress adjustment layer between the Sapphire Substrate and the GaN n-layer, wherein the Stress relief layer Lattice constant is between sapphire and GaN.
Optionally, the step of growth stress adjustment layer between the Sapphire Substrate and the GaN n-layer is wrapped It includes: growing the Stress relief layer between the Sapphire Substrate and the GaN intrinsic layer.
Optionally, the method also includes: between the GaN intrinsic layer and the GaN n-layer grow AlGaN/GaN Superlattice reflection layer.
Optionally, the step of growth stress adjustment layer between the Sapphire Substrate and the GaN n-layer is wrapped It includes: growing the Stress relief layer between the GaN intrinsic layer and the GaN n-layer.
Optionally, the method also includes: it is super to grow between the GaN n-layer and the luminescent layer AlGaN/GaN Lattice reflecting layer.
Optionally, the Stress relief layer is SiC or GaN/SiC superlattices.
The disclosure also provides a kind of LED epitaxial slice, and the epitaxial wafer includes Sapphire Substrate and successively grows GaN intrinsic layer, GaN n-layer in the Sapphire Substrate, luminescent layer, GaN p-type layer, the epitaxial wafer further include growth Stress relief layer between the Sapphire Substrate and the GaN n-layer, wherein the lattice constant of the Stress relief layer Between sapphire and GaN.
Optionally, the Stress relief layer is grown between the Sapphire Substrate and the GaN intrinsic layer.
Optionally, the epitaxial wafer further include: AlGaN/GaN superlattice reflection layer is grown in the GaN intrinsic layer and institute It states between GaN n-layer.
Optionally, the Stress relief layer is grown between the GaN intrinsic layer and the GaN n-layer.
Optionally, the epitaxial wafer further include: AlGaN/GaN superlattice reflection layer is grown in the GaN n-layer and institute It states between luminescent layer.
Optionally, the Stress relief layer is SiC or GaN/SiC superlattices.
Through the above technical solutions, grown a layer lattice constant between Sapphire Substrate and GaN n-layer between indigo plant Stress relief layer between jewel and GaN.The lattice mismatch between sapphire and GaN can be reduced in this way, to reduce extension The warpage that piece occurs during the growth process and after the completion of growth, improves the performance of extension flake products.
Other feature and advantage of the disclosure will the following detailed description will be given in the detailed implementation section.
Detailed description of the invention
Attached drawing is and to constitute part of specification for providing further understanding of the disclosure, with following tool Body embodiment is used to explain the disclosure together, but does not constitute the limitation to the disclosure.In the accompanying drawings:
Fig. 1 is the flow chart of the manufacturing method for the LED epitaxial wafer that an exemplary embodiment provides；
Fig. 2 is the schematic diagram for the LED epitaxial wafer that an exemplary embodiment provides；
Fig. 3 is the schematic diagram for the LED epitaxial wafer that another exemplary embodiment provides；
Fig. 4 is the schematic diagram for the LED epitaxial wafer that another exemplary embodiment provides；
Fig. 5 is the schematic diagram for the LED epitaxial wafer that another exemplary embodiment provides；
Fig. 6 is the schematic diagram for the LED epitaxial wafer that another exemplary embodiment provides.
Description of symbols
1 Sapphire Substrate, 2 GaN intrinsic layer, 3 GaN n-layer
4 luminescent layer, 5 GaN p-type layer, 6 Stress relief layer
7 AlGaN/GaN superlattice reflection layers
Specific embodiment
It is described in detail below in conjunction with specific embodiment of the attached drawing to the disclosure.It should be understood that this place is retouched The specific embodiment stated is only used for describing and explaining the disclosure, is not limited to the disclosure.
Fig. 1 is the flow chart of the manufacturing method for the LED epitaxial wafer that an exemplary embodiment provides.As shown in Figure 1, the side Method may include lower step.
In step s 11, a Sapphire Substrate is provided.
In step s 12, GaN intrinsic layer, GaN n-layer, luminescent layer and GaN p-type are successively grown on a sapphire substrate Layer, wherein the growth stress adjustment layer between Sapphire Substrate and GaN n-layer.The lattice constant of Stress relief layer is between indigo plant Between jewel and GaN.
Stress relief layer for example can be SiC or GaN/SiC superlattices.
The disclosure also provide it is a kind of by the above method manufacture LED epitaxial wafer, the epitaxial wafer include Sapphire Substrate and Successively grow GaN intrinsic layer, GaN n-layer, luminescent layer, GaN p-type layer on a sapphire substrate.The epitaxial wafer further includes The Stress relief layer being grown between Sapphire Substrate and GaN n-layer.Wherein, the lattice constant of Stress relief layer is between blue precious Between stone and GaN.
Through the above technical solutions, grown a layer lattice constant between Sapphire Substrate and GaN n-layer between indigo plant Stress relief layer between jewel and GaN.The lattice mismatch between sapphire and GaN can be reduced in this way, to reduce extension The warpage that piece occurs during the growth process and after the completion of growth, improves the performance of extension flake products.
In one embodiment, Stress relief layer can be grown between Sapphire Substrate and GaN intrinsic layer.Fig. 2 is to show The schematic diagram for the LED epitaxial wafer that example property embodiment provides.As shown in Fig. 2, Stress relief layer 6 is grown in Sapphire Substrate 1 and GaN Between intrinsic layer 2.
It is above-mentioned between Sapphire Substrate 1 and GaN n-layer 3 in the manufacturing process of LED epitaxial wafer as shown in Figure 2 The step of growth stress adjustment layer 6 may include: the growth stress adjustment layer 6 between Sapphire Substrate 1 and GaN intrinsic layer 2.
Specifically, in one embodiment, the manufacturing process of LED epitaxial wafer shown in Fig. 2 is as follows:
1) Sapphire Substrate 1 is patterned using the method for wet etching or dry etching, patterned substrate knot Structure can be the cone-shaped patterned substrate of periodic arrangement, and the Ground Diameter of cone-shaped substrate can be 2.0~2.7um, high Degree can be 1.5~1.7um, and spacing can be 0.3~1.0um.
Wherein, patterned substrate structure can be the cone-shaped structure of periodic arrangement, or the step for protrusion of surface Shape structure, column structure etc..
Optionally, it can use the method epitaxial growth GaN of metal organic chemical compound vapor deposition in Sapphire Substrate 1 Nucleating layer (not shown).GaN nucleating layer can be by the way of low-temperature epitaxy, and growth temperature is 500~700 DEG C, with a thickness of 10 ~100nm.Nucleating layer is usually polycrystalline structure, and fission is independent island form one by one in temperature-rise period, is subsequent outer The growth for prolonging layer provides nuclearing centre, reduces the lattice mismatch between Sapphire Substrate 1 and epitaxial layer.
2) the high growth temperature SiC Stress relief layer 6 on Sapphire Substrate 1 (or GaN nucleating layer), SiC Stress relief layer 6 By the control to temperature, pressure, growth rate in growth course, to realize the control to subsequent epitaxial layer warpage degree.? In growth course, temperature range be 900~1400 DEG C, preferably 1200~1300 DEG C, pressure be 100~800mbar, preferably 200 ~600mbar.Since there is also lattice mismatch, this causes crystals there are stress between GaN and SiC, the size of stress with Respective thickness is related with growth conditions, and the concave-convex state of epitaxial wafer is influenced by stress intensity when subsequent light emitting layer grown, It can make extension by the thickness and growth course of control SiC come the formation state of epitaxial layer when adjusting subsequent light emitting layer grown Layer is equably grown.
3) high temperature GaN intrinsic layer 2 is grown on SiC Stress relief layer 6.By to temperature in the growth course of GaN intrinsic layer 2 The three peacekeeping two-dimensional growths of GaN are realized in the control of the technological parameters such as degree, pressure, III-V compound ratio, keep epitaxial surface flat Whole, defect is less.During the growth process temperature be 1000~1300 DEG C, preferably 1000~1100 DEG C, pressure be 100~ 400mbar, preferably 200~300mbar, III-V compound ratio are 600~1500, preferably 900~1200.GaN intrinsic layer 2 effect is the growth basis for providing a stabilization for subsequent GaN n-layer and luminescent layer, smooth, crystal quality is good.
4) Si is grown on GaN intrinsic layer 2 adulterate GaN n-layer 3.Si doping concentration is 5 × 1018~2 × 1019/cm3, With a thickness of 1000~4000nm.
5) multi-quantum well luminescence layer 4 is grown in GaN n-layer 3.The structure of multiple quantum wells is InxGa1-xN/GaN (0 < x < 1), for potential well layer with a thickness of 2~4nm, barrier layer thickness is 8~15nm, and the period of Quantum Well is 1~15, volume minor structure Growth temperature is 700~850 DEG C.
Optionally, AlGaN electronic barrier layer (not shown) can be grown on luminescent layer 4.
6) Mg is grown on luminescent layer 4 (or AlGaN electronic barrier layer) adulterate GaN p-type layer 5.
After epitaxial wafer is made, LED chip can also be manufactured by the epitaxial wafer according to the following steps:
P-type InGaN contact layer is grown in GaN p-type layer 5；
P-type InGaN contact layer is activated, the mode of activation be temperature be 600~800 DEG C vacuum or N2Atmosphere Lower carry out rapid thermal annealing, or bombarded using ion beam；
It is adopted vapor deposition method in epi-layer surface and prepares transparency conducting layer.Transparency conducting layer with a thickness of 1~1000nm, It is preferred that 80~300nm, transparency conducting layer can be ITO, or CTO, ZnO/Al, Ni/Au, Ni/Pd/Au, Pt/Au etc. are closed Any one in gold；
Using the method for inductive couple plasma body (inductively coupled plasma, ICP) etching by portion Subregion etches into GaN n-layer 3, and etches step-like structure in GaN n-layer 3, and step surface height is 500~ 2000nm；
Metal p-electrode is prepared using the method growth of vapor deposition over transparent conductive layer, metal p-electrode can close for Ti/Au Gold, or any two or more of alloys in Ni, Au, Al, Ti, Pd, Pt, Sn, Cr, metal p-electrode with a thickness of 0.2~1 μm；
Metal n-electrode is prepared on the ledge surface and side wall of the GaN n-layer 3 etched using the method for vapor deposition, gold Belonging to n-electrode can be Ti/Al alloy, or two or more of alloys in Ti, Al, Au, Pt, Sn, metal n-electrode With a thickness of 0.2~1 μm.
So far LED chip can be produced.
In the related art, since there are biggish lattice mismatches between sapphire and GaN, so causing to deposit in epitaxial layer In a large amount of defect, these defects extend to luminescent layer, often become non-radiative recombination center, to influence the effect that shines Rate.In the embodiment of fig. 2, Stress relief layer 6 is grown between Sapphire Substrate 1 and GaN intrinsic layer 2, can not only be reduced The warpage of GaN epitaxial layer, and can reduce the defect concentration of GaN epitaxial layer.
Optionally, the epitaxial wafer that the disclosure provides can also include AlGaN/GaN superlattice reflection layer.Fig. 3 is another shows The schematic diagram for the LED epitaxial wafer that example property embodiment provides.As shown in figure 3, on the basis of Fig. 2, AlGaN/GaN superlattice reflection Layer 7 is grown between GaN intrinsic layer 2 and GaN n-layer 3.
In the manufacturing process of LED epitaxial wafer as shown in Figure 3, on the basis of Fig. 1, the manufacturing method of LED epitaxial wafer Further include: AlGaN/GaN superlattice reflection layer 7 is grown between GaN intrinsic layer 2 and GaN n-layer 3.
Specifically, the embodiment of Fig. 3 can be to make some changes on the basis of the embodiment of Fig. 2.In above-mentioned steps 3) it Afterwards, step 3 ' can be increased): AlGaN/GaN superlattice reflection layer 7 is grown on GaN intrinsic layer 2, periodicity is 30~50, week Phase is 10~30% with a thickness of 2~5nm, the Al content of AlGaN.
Then, step 4) is changed are as follows: is grown Si on AlGaN/GaN superlattice reflection layer 7 and is adulterated GaN n-layer 3.
In the fig. 3 embodiment, AlGaN/GaN superlattice reflection layer 7 is increased, so that the light that luminescent layer 4 emits downwards It is reflected upwards via AlGaN/GaN superlattice reflection layer 7, reduces light loss.
Fig. 4 is the schematic diagram for the LED epitaxial wafer that another exemplary embodiment provides.As shown in figure 4, on the basis of Fig. 2, AlGaN/GaN superlattice reflection layer 7 is grown between GaN n-layer 3 and luminescent layer 4.
In the manufacturing process of LED epitaxial wafer as shown in Figure 4, on the basis of Fig. 1, the manufacturing method of LED epitaxial wafer Further include: AlGaN/GaN superlattice reflection layer 7 is grown between GaN n-layer 3 and luminescent layer 4.
Specifically, the embodiment of Fig. 4 can be to make some changes on the basis of the embodiment of Fig. 2.In above-mentioned steps 4) it Afterwards, step 4 ' can be increased): AlGaN/GaN superlattice reflection layer 7 is grown in GaN n-layer 3, periodicity is 30~50, week Phase is 10~30% with a thickness of 2~5nm, the Al content of AlGaN.
Then, step 5) is changed are as follows: multi-quantum well luminescence layer 4 is grown on AlGaN/GaN superlattice reflection layer 7.
Compared with the embodiment of Fig. 3, AlGaN/GaN superlattice reflection layer 7 has adjusted position, but can equally play reduction The effect of epitaxial wafer light loss.
In another embodiment, Stress relief layer 6 can be grown between GaN intrinsic layer 2 and GaN n-layer 3.Fig. 5 is The schematic diagram for the LED epitaxial wafer that another exemplary embodiment provides.As shown in figure 5, Stress relief layer 6 is grown in GaN intrinsic layer 2 Between GaN n-layer 3.
It is above-mentioned between Sapphire Substrate 1 and GaN n-layer 3 in the manufacturing process of LED epitaxial wafer as shown in Figure 5 The step of growth stress adjustment layer 6 may include: the growth stress adjustment layer 6 between GaN intrinsic layer 2 and GaN n-layer 3.
Specifically, in one embodiment, the manufacturing process of LED epitaxial wafer shown in fig. 5 is as follows:
A) Sapphire Substrate 1 is patterned using the method for wet etching or dry etching, patterned substrate knot Structure can be the cone-shaped patterned substrate of periodic arrangement, and the Ground Diameter of cone-shaped substrate can be 2.0~2.7um, high Degree can be 1.5~1.7um, and spacing can be 0.3~1.0um.
Wherein, patterned substrate structure can be the cone-shaped structure of periodic arrangement, or the step for protrusion of surface Shape structure, column structure etc..
Optionally, it can use the method epitaxial growth GaN of metal organic chemical compound vapor deposition in Sapphire Substrate 1 Nucleating layer (not shown).
B) high temperature GaN intrinsic layer 2 is grown on Sapphire Substrate 1 (or GaN nucleating layer).The growth course of GaN intrinsic layer 2 In by the technological parameters such as temperature, pressure, III-V compound ratio control realize GaN three peacekeeping two-dimensional growths, make Epitaxial surface is smooth, and defect is less.Temperature is 1000~1300 DEG C during the growth process, and preferably 1000~1100 DEG C, pressure is 100~400mbar, preferably 200~300mbar, III-V compound ratio are 600~1500, preferably 900~1200.
C) SiC Stress relief layer 6 is grown on GaN intrinsic layer 2, by temperature in the growth course of SiC Stress relief layer 6 The control of degree, pressure, growth rate, to realize the control to subsequent epitaxial layer warpage degree.During the growth process, temperature range It is 900~1400 DEG C, preferably 1200~1300 DEG C, pressure is 100~800mbar, preferably 200~600mbar.
D) Si is grown on SiC Stress relief layer 6 adulterate GaN n-layer 3.Si doping concentration is 5 × 1018~2 × 1019/ cm3, with a thickness of 1000~4000nm.
E) multi-quantum well luminescence layer 4 is grown in GaN n-layer 3.The structure of multiple quantum wells is InxGa1-xN/GaN (0 < x < 1), for potential well layer with a thickness of 2~4nm, barrier layer thickness is 8~15nm, and the period of Quantum Well is 1~15, volume minor structure Growth temperature is 700~850 DEG C.
Optionally, AlGaN electronic barrier layer (not shown) can be grown on luminescent layer 4.
F) Mg is grown on luminescent layer 4 (or AlGaN electronic barrier layer) adulterate GaN p-type layer 5.
In the 5 embodiment of figure 5, compared with the embodiment of above-mentioned Fig. 2-Fig. 4, Stress relief layer 6 has adjusted position, but same Sample can play the role of reducing epitaxial wafer warpage.UGaN in GaN intrinsic layer 2 can provide a comparison for the growth of SiC Good basis.The SiC layer grown on uGaN is mono-crystalline structures.Since there is also lattice mismatches between GaN and SiC, this causes There are stress for crystals, and the size of stress is related with respective thickness and growth conditions, and extension when subsequent light emitting layer grown The concave-convex state of piece is influenced by stress intensity.Subsequent luminescent layer can be adjusted by controlling thickness and the growth course of SiC The formation state of epitaxial layer, grows epitaxial layer equably when growth.
Similarly, on the basis of Fig. 5, epitaxial wafer can also increase AlGaN/GaN superlattice reflection layer 7.Fig. 6 is another The schematic diagram for the LED epitaxial wafer that exemplary embodiment provides.As shown in fig. 6, AlGaN/GaN superlattices are anti-on the basis of Fig. 5 Layer 7 is penetrated to be grown between GaN n-layer 3 and luminescent layer 4.
In the manufacturing process of LED epitaxial wafer as shown in FIG. 6, on the basis of Fig. 5, the manufacturing method of LED epitaxial wafer Further include: AlGaN/GaN superlattice reflection layer 7 is grown between GaN n-layer 3 and luminescent layer 4.
Specifically, the embodiment of Fig. 6 can be to make some changes on the basis of the embodiment of Fig. 5.Above-mentioned steps d) it Afterwards, step d ' can be increased): AlGaN/GaN superlattice reflection layer 7 is grown in GaN n-layer 3, periodicity is 30~50, week Phase is 10~30% with a thickness of 2~5nm, the Al content of AlGaN.
Then, step e) is changed are as follows: multi-quantum well luminescence layer 4 is grown on AlGaN/GaN superlattice reflection layer 7.
Compared with the embodiment of Fig. 5, in the embodiment in fig 6, epitaxial layer increases AlGaN/GaN superlattice reflection layer 7, So that the light that luminescent layer 4 emits downwards reflects upwards via AlGaN/GaN superlattice reflection layer 7, reduce light loss.
Stress relief layer 6 in above embodiments is described by taking SiC as an example.Stress relief layer 6 can also use GaN/SiC superlattices can equally play the role of adjusting subsequent light emitting layer grown stress, between preferably alleviation GaN and SiC Stress, avoid because growth SiC thick film caused by sliver phenomena such as.
Wherein, the periodicity of GaN/SiC superlattices can be 30~50, and periodic thickness is 2~5nm.It is super brilliant in GaN/SiC It, can be by the control to temperature, pressure, growth rate, to realize to subsequent outer in the growth course of the Stress relief layer 6 of lattice Prolong the control of layer warpage degree, during the growth process, temperature be 900~1400 DEG C, preferably 1200~1300 DEG C, pressure 100 ~800mbar, preferably 200~600mbar.
It is understood that although above embodiments are to be described by taking patterned substrate as an example, but the disclosure is not It is limited to the GaN base LED prepared in patterned substrate, further includes using epitaxial lateral overgrowth (Epitaxial Lateral Overgrow, ELOG) technology and pendeo epitaxy growth (Pendeo Epiatxy, PE) technology preparation GaN base LED.
The preferred embodiment of the disclosure is described in detail in conjunction with attached drawing above, still, the disclosure is not limited to above-mentioned reality The detail in mode is applied, in the range of the technology design of the disclosure, a variety of letters can be carried out to the technical solution of the disclosure Monotropic type, these simple variants belong to the protection scope of the disclosure.
It is further to note that specific technical features described in the above specific embodiments, in not lance In the case where shield, it can be combined in any appropriate way.In order to avoid unnecessary repetition, the disclosure to it is various can No further explanation will be given for the combination of energy.
In addition, any combination can also be carried out between a variety of different embodiments of the disclosure, as long as it is without prejudice to originally Disclosed thought equally should be considered as disclosure disclosure of that.

Claims (12)

1. a kind of manufacturing method of LED epitaxial slice, which comprises provide a Sapphire Substrate (1), and in institute It states and successively grows GaN intrinsic layer (2), GaN n-layer (3), luminescent layer (4) and GaN p-type layer (5) on Sapphire Substrate (1), It is characterized in that:
The growth stress adjustment layer (6) between the Sapphire Substrate (1) and the GaN n-layer (3), wherein the stress The lattice constant of adjustment layer (6) is between sapphire and GaN.
2. the method according to claim 1, wherein described in the Sapphire Substrate (1) and the GaN N-shaped The step of growth stress adjustment layer (6), includes: between layer (3)
The Stress relief layer (6) is grown between the Sapphire Substrate (1) and the GaN intrinsic layer (2).
3. according to the method described in claim 2, it is characterized in that, the method also includes:
AlGaN/GaN superlattice reflection layer (7) are grown between the GaN intrinsic layer (2) and the GaN n-layer (3).
4. the method according to claim 1, wherein described in the Sapphire Substrate (1) and the GaN N-shaped The step of growth stress adjustment layer (6), includes: between layer (3)
The Stress relief layer (6) is grown between the GaN intrinsic layer (2) and the GaN n-layer (3).
5. method according to claim 2 or 4, which is characterized in that the method also includes:
AlGaN/GaN superlattice reflection layer (7) are grown between the GaN n-layer (3) and the luminescent layer (4).
6. the method according to claim 1, wherein the Stress relief layer (6) is that SiC or GaN/SiC is super brilliant Lattice.
7. a kind of LED epitaxial slice, the epitaxial wafer includes Sapphire Substrate (1) and is successively grown in described blue precious GaN intrinsic layer (2), GaN n-layer (3) on stone lining bottom (1), luminescent layer (4), GaN p-type layer (5), which is characterized in that described Epitaxial wafer further includes the Stress relief layer (6) being grown between the Sapphire Substrate (1) and the GaN n-layer (3), In, the lattice constant of the Stress relief layer (6) is between sapphire and GaN.
8. epitaxial wafer according to claim 7, which is characterized in that the Stress relief layer (6) is grown in the sapphire Between substrate (1) and the GaN intrinsic layer (2).
9. epitaxial wafer according to claim 8, which is characterized in that the epitaxial wafer further include:
AlGaN/GaN superlattice reflection layer (7) is grown between the GaN intrinsic layer (2) and the GaN n-layer (3).
10. epitaxial wafer according to claim 7, which is characterized in that the Stress relief layer (6) is grown in the GaN sheet It levies between layer (2) and the GaN n-layer (3).
11. the epitaxial wafer according to claim 8 or 10, which is characterized in that the epitaxial wafer further include:
AlGaN/GaN superlattice reflection layer (7) is grown between the GaN n-layer (3) and the luminescent layer (4).
12. epitaxial wafer according to claim 7, which is characterized in that the Stress relief layer (6) is super for SiC or GaN/SiC Lattice.
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Cited By (1)

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