CN207818603U - A kind of light-emitting diode chip for backlight unit - Google Patents
A kind of light-emitting diode chip for backlight unit Download PDFInfo
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- CN207818603U CN207818603U CN201721569318.7U CN201721569318U CN207818603U CN 207818603 U CN207818603 U CN 207818603U CN 201721569318 U CN201721569318 U CN 201721569318U CN 207818603 U CN207818603 U CN 207818603U
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Abstract
The utility model provides a kind of light-emitting diode chip for backlight unit, including：Substrate；And buffer layer, n-type GaN layer, luminescent layer, electronic barrier layer, p-type GaN layer and the current-diffusion layer sequentially formed over the substrate；The electronic barrier layer is equipped with the hole of regular array, and described hole extends downward into luminous layer surface.The light-emitting diode chip for backlight unit, by etching the hole of regular array on electronic barrier layer, the stress between being released effectively in electronic barrier layer and multi-quantum well luminescence layer improves the luminous efficiency of LED chip to reduce the influence that Polarization field strength is brought.
Description
Technical field
The utility model is related to technical field of semiconductors, specifically, being related to a kind of light-emitting diode chip for backlight unit.
Background technology
Existing common gallium nitride light-emitting diode structure includes substrate, n-type semiconductor layer, multi-quantum well luminescence layer, electricity
Sub- barrier layer, p-type semiconductor layer and structure of transparent conductive layer.
The multi-quantum well luminescence layer of above structure generally uses InGaN/GaN multi-quantum pit structures as luminescent layer, wherein
Light-emitting zone is InGaN well layer, since there are lattice mismatches between InGaN and GaN so that InGaN/GaN multiple quantum wells memories
In serious Polarization field strength, which causes the electrons and holes into Quantum Well to be separated, and seriously affects luminous
Efficiency, and lattice mismatch is bigger, Polarization field strength is stronger, and the influence to luminous efficiency is more serious.On the other hand, due to gallium nitride
In LED structure, the higher concentration of n-layer electronics can reach 1021/ cm3 the orders of magnitude, and mobility is larger, can reach
200 ~ 500 cm2/V.S, and the carrier concentration in hole is very small in p-type layer, only 1017/ cm3 orders of magnitude or so, compare electronics
Small three orders of magnitude are wanted, and the mobility leaf in hole is very small, only 5 ~ 20 cm2/V. are smaller than the mobility of electronics very
It is more, thus electronics usually overflow to p layers with hole occur it is non-radiative meet, this greatly reduces luminous efficiency.
In order to solve this problem, it is typically employed between multi-quantum well luminescence layer and p-type layer that be inserted into an energy band higher
Electronic barrier layer stops the overflow of electronics.But there are lattice mismatches, lattice mismatch to get between the electronic barrier layer and luminescent layer
Greatly, then Polarization field strength bigger, has seriously affected luminous efficiency.How it is reduced while improving electronic barrier layer effect to hair
The influence of light efficiency becomes the key for improving LED luminous efficiencies.
Utility model content
The utility model one of to solve above-mentioned technical problem, provides a kind of light-emitting diode chip for backlight unit, the light emitting diode
Chip can reduce the Polarization field strength between electronic barrier layer and luminescent layer, improve luminous efficiency.
The utility model provides a kind of light-emitting diode chip for backlight unit, including：Substrate；And it sequentially forms over the substrate
Buffer layer, n-type GaN layer, luminescent layer, electronic barrier layer, p-type GaN layer and current-diffusion layer；The electronic barrier layer is equipped with
The hole of regular array, described hole extend downward into luminous layer surface.
In one embodiment, the luminescent layer is InGaN/GaN multiple quantum well layers.
In one embodiment, the electronic barrier layer is AlGaN layer, and wherein the degree of Al is 15-50%.
In one embodiment, a diameter of 0.3-3.0 microns of described hole.
In one embodiment, the spacing between adjacent holes is 0.3-3.0 microns.
In one embodiment, the buffer layer includes：
Semiconductor nucleating layer, the semiconductor nucleating layer setting is over the substrate；And
Semiconductor intrinsic layer, the semiconductor layer intrinsic layer are arranged in the semiconductor nucleating layer and the n-type GaN layer
Between.
In one embodiment, light-emitting diode chip for backlight unit further comprises：Stress release layer, the stress release layer setting
Between the n-type GaN layer and the luminescent layer, the stress release layer is the InGaN/GaN layers of multicycle.
Light-emitting diode chip for backlight unit provided by the utility model, by the hole for etching regular array on electronic barrier layer
Hole, the stress between being released effectively in electronic barrier layer and multi-quantum well luminescence layer, to reduce the shadow that Polarization field strength is brought
It rings, improves the luminous efficiency of LED chip.
Description of the drawings
Fig. 1 is the structural schematic diagram for the light-emitting diode chip for backlight unit that the utility model embodiment provides；
Fig. 2 is the structural schematic diagram of the electronic barrier layer for the light-emitting diode chip for backlight unit that the utility model embodiment provides；
Fig. 3 is another structural representation of the electronic barrier layer for the light-emitting diode chip for backlight unit that the utility model embodiment provides
Figure.
Specific implementation mode
The technical issues of in order to keep the utility model solved, technical solution and advantageous effect are more clearly understood, below
In conjunction with the embodiments, the present invention will be further described in detail.It should be appreciated that specific embodiment described herein is only
To explain the utility model, it is not used to limit the utility model.
In the description of the present invention, it should be understood that term "center", " longitudinal direction ", " transverse direction ", " length ", " width
Degree ", " thickness ", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom" "inner", "outside", " suitable
The orientation or positional relationship of the instructions such as hour hands ", " counterclockwise " is to be based on the orientation or positional relationship shown in the drawings, merely to just
In description the utility model and simplify description, specific side must be had by not indicating or implying the indicated device or element
Position, with specific azimuth configuration and operation, therefore should not be understood as limiting the present invention.
In addition, term " first ", " second " are used for description purposes only, it is not understood to indicate or imply relative importance
Or implicitly indicate the quantity of indicated technical characteristic.Define " first " as a result, the feature of " second " can be expressed or
Implicitly include one or more this feature.The meaning of " plurality " is two or two in the description of the present invention,
More than, unless otherwise specifically defined.
As shown in Figure 1, the utility model provides a kind of light-emitting diode chip for backlight unit, including：Substrate 1；And in the substrate
Buffer layer, first kind semiconductor layer 4, luminescent layer 6, electronic barrier layer 7,8 and of Second Type semiconductor layer sequentially formed on 1
Current-diffusion layer 10；The electronic barrier layer 7 is equipped with the hole 71 of regular array, and described hole 71 extends downward into luminescent layer
6 surfaces.
Light-emitting diode chip for backlight unit provided by the utility model, by the hole for etching regular array on electronic barrier layer 7
Hole 71, the stress between being released effectively in electronic barrier layer 7 and multi-quantum well luminescence layer 6, brings to reduce Polarization field strength
Influence, improve the luminous efficiency of LED chip.
In one embodiment of the utility model, the substrate 1 is sapphire, preferably patterned substrate；Described
One type semiconductor layer 4 is N-type GaN layer, and Second Type semiconductor layer 8 is p-type GaN layer, and the luminescent layer 6 is InGaN/GaN
Multiple quantum well layer, electronic barrier layer 7 are AlGaN layer, and current-diffusion layer 10 is ITO layer.Certainly, first kind semiconductor layer 4 can
Think that p type semiconductor layer, Second Type semiconductor layer 8 can be n type semiconductor layer, technical staff can set according to actual needs
It sets.
Compared with traditional epitaxial slice structure, due to there is crystalline substance between electronic barrier layer AlGaN and luminescent layer InGaN, GaN
Lattice mismatch exacerbates the Polarization field strength of multi-quantum well luminescence layer InGaN, influences luminous efficiency, and the utility model is hindered in electronics
The hole 71 with the arrangement of systematicness figure has been etched in barrier 7, can be released effectively AlGaN electronic barrier layers and multiple quantum wells
Stress between middle InGaN improves the luminous efficiency of LED chip to reduce the influence that Polarization field strength is brought.Further,
Electronic barrier layer using the above structure, it is possible to increase the content of Al in AlGaN electronic barrier layers, it is preferred that Al in AlGaN layer
Degree is 15 ~ 50%, can so increase the energy gap of electronic barrier layer, improves the barrier effect to electronics, to big
The big luminous efficiency for improving LED chip.
Specifically, the shape of the hole 71 of the electronic barrier layer 7 can be circle, as shown in Figure 2, or polygon
The other shapes such as shape, hexagon, as shown in Figure 3.A diameter of 0.3-3.0 microns of described hole 71；Between adjacent holes 71
Spacing is 0.3-3.0 microns, it is preferred that hole 71 is uniformly arranged on electronic barrier layer.The depth of described hole 71 and electricity
The consistency of thickness on sub- barrier layer 7, i.e. hole extend downward into 6 surface of luminescent layer.
In one embodiment of the utility model, the buffer layer includes：Semiconductor nucleating layer 2 and semiconductor layer are intrinsic
Layer 3, the semiconductor nucleating layer 2 are arranged on the substrate 1；The setting of semiconductor intrinsic layer 3 is nucleated in the semiconductor
Between layer 2 and the first kind semiconductor layer 4.Specifically, the semiconductor nucleating layer 2 is GaN nucleating layers, it is described partly to lead
Body intrinsic layer 3 is GaN intrinsic layers.
In the utility model one embodiment, the light-emitting diode chip for backlight unit further includes stress release layer 5, the stress
Releasing layer 5 is arranged between the first kind semiconductor layer 4 and the luminescent layer 6, and the stress release layer is the multicycle
InGaN/GaN layers.
The utility model also provides a kind of production method of light-emitting diode chip for backlight unit, including
S1, substrate 1 is provided；
S2, buffer layer, first kind semiconductor layer 4, luminescent layer 6 and electronic barrier layer 7 are sequentially formed on substrate 1；
S3, the mask layer with regular array hole is made on electronic barrier layer 7, place is performed etching to electronic barrier layer
Reason, is etched to 6 surface of luminescent layer by hole 71, obtains the electronic barrier layer 7 of the hole with regular array；
S4, deposition forms Second Type semiconductor layer 8 on electronic barrier layer 7；
S5, current-diffusion layer 10 is formed on the Second Type semiconductor layer 8.
In one embodiment of the utility model, when forming buffer layer over the substrate, specifically comprise the following steps：
Deposition forms semiconductor nucleating layer 2 on substrate 1；
Deposition forms semiconductor intrinsic layer 3 on the semiconductor nucleating layer 2.
In one embodiment of the utility model, in step s 2, after forming first kind semiconductor layer 4,
Stress release layer 5 is formed on the first kind semiconductor layer 4, and luminescent layer 6 is then formed on stress release layer 5；Specifically
The stress release layer 5 is the InGaN/GaN layers of multicycle.
The production method that a specific embodiment elaborates the LED chip of the utility model is provided below, to this practicality
Novel middle LED chip and advantage can also elaborate in production method, and in specific implementation process, this practicality is new
The growth of type LED epitaxial layers uses MOCVD（Metal Organic Chemical Vapor Deposition method）Method.
1, substrate 1 is provided, substrate is patterned using the method for wet etching or dry etching, patterned substrate
Structure is the cone-shaped patterned substrate of periodic arrangement, and cone-shaped a diameter of 2.0 ~ 2.8um is highly 1.5 ~ 1.788um,
Spacing is 0.2 ~ 1.0um, and patterned substrate is sapphire.
The patterned substrate structure that the utility model uses also includes protrusion of surface for the cone-shaped structure of periodic arrangement
Step-like structure, column structure etc..
2, the method epitaxial growth of gallium nitride nucleating layer 2 of metal organic chemical compound vapor deposition is utilized on substrate 1.
3, the high growth temperature gallium nitride intrinsic layer 3 on gallium nitride nucleating layer 2, in the growth course of high-temperature ammonolysis gallium intrinsic layer
By realizing three peacekeeping two-dimensional growths of gallium nitride to the control of the technological parameters such as temperature, pressure, III/V compounds of group ratios,
Keep epitaxial surface smooth, defect is less, and temperature range is between 1000 DEG C to 1300 DEG C during the control of technological parameter, preferably
1000 DEG C to 1100 DEG C；Pressure range in 100mbar between 400mbar, preferably 200 ~ 300mbar；III/V compounds of group ratios
Example is between 600 ~ 1500, between preferably 900 ~ 1200；
4, Si is grown on gallium nitride intrinsic layer 3 adulterates n-type gallium nitride layer 4, Si doping concentrations are 5E18 to 2E20/cm3,
Thickness is 1000 ~ 4000nm.
5, the stress release layer 5 of the InGaN/GaN of multicycle is grown in n-type gallium nitride layer 4, the wherein thickness of GaN is
The thickness of 20 ~ 40nm, InGaN are 1 ~ 5nm, and periodicity is 3 ~ 5, and the In contents of InGaN are 1 ~ 5%.InGaN/ can also be used
For GaN superlattices as stress release layer, periodicity is 10 ~ 30, and periodic thickness is 3 ~ 7nm.
6, multi-quantum well luminescence layer 6 is grown on stress release layer 5, the structure of multi-quantum well luminescence layer is InxGa1-xN/
GaN（0 ＜ x ＜ 1）；Potential well layer thickness is 2 ~ 4 nanometers, and barrier layer thickness is 8 ~ 15 nanometers, and the period of Quantum Well is 1 to 15 week
Phase.The growth temperature of multi-quantum pit structure is 700 ~ 850 DEG C.
7, growing aluminum nitride gallium electronic barrier layer 7 in multi-quantum well luminescence layer 6, thickness are 10 ~ 200 nanometers, AlGaN electronics
The degree of Al is 15 ~ 50% in barrier layer.
8, after the completion of aluminium gallium nitride alloy electronic barrier layer 7 is grown, take out epitaxial wafer be exposed, develop, etch cleaning etc.
Technique etches certain hole 71 on aluminium gallium nitride alloy electronic barrier layer, is arranged on electronic barrier layer.The shape of hole can
Think circle, or hexagonal, the size of hole is 0.3 ~ 3.0 micron, and the spacing between adjacent holes is 1.0 ~ 5.0 micro-
Rice, the depth of hole and the consistency of thickness of electronic barrier layer.
9, the continued growth Mg doped p types gallium nitride layer 8 on the aluminium gallium nitride alloy electronic barrier layer 7 after finishing hole.
10, optional, p-type InGaN contact layers 9 are grown on p-type gallium nitride layer 8.
11, p-type gallium nitride layer 8 is activated, the mode of activation be 600-800 DEG C in temperature vacuum or nitrogen atmosphere
Lower carry out rapid thermal annealing is enclosed, also includes to be bombarded using ion beam.
12, transparent current-diffusion layer 10, the thickness of current-diffusion layer 10 are prepared by the way of vapor deposition in epi-layer surface
Degree be 1 ~ 1000 nanometer, preferably 80 ~ 300 nanometers, current-diffusion layer ITO, or include CTO, ZnO:Al、Ni/Au、
One kind in the alloys such as Ni/Pd/Au, Pt/Au.
13, using inductive couple plasma body（Inductively coupled plasma, abbreviation ICP）Etching
The subregion of conductive layer is etched into n-layer GaN layer 4 by method, and etches step-like structure, step surface height in n-layer GaN layer
It is 500 ~ 2000 nanometers.
14, metal p-electrode 11, metal p-electrode Ti/Au are prepared using the method growth of vapor deposition on current-diffusion layer 10
Alloy can also be the alloy of arbitrary two kinds or various metals in Ni, Au, Al, Ti, Pd, Pt, Sn, Cr.Metal p-electrode 11
Thickness be 0.2 ~ 1 micron.
15, metal n-electrode 12 is prepared on the N-shaped gallium nitride ledge surface and side wall etched using the method for vapor deposition,
Metal n-electrode 12 is Ti/Al alloys, also includes the alloy of two or more metals in Ti, Al, Au, Pt, Sn, metal n-electrode
Thickness is 0.2 ~ 1 micron.
In conclusion light-emitting diode chip for backlight unit provided by the utility model, by etching rule on electronic barrier layer
The hole of arrangement, the stress between being released effectively in electronic barrier layer and multi-quantum well luminescence layer, to reduce Polarization field strength
The influence brought improves the luminous efficiency of LED chip.
In the description of this specification, reference term " one embodiment ", " some embodiments ", " example ", " specifically show
The description of example " or " some examples " etc. means specific features, structure, material or spy described in conjunction with this embodiment or example
Point is contained at least one embodiment or example of the utility model.Moreover, description specific features, structure, material or
Feature can be combined in any suitable manner in any one or more of the embodiments or examples.Although having been shown and retouching above
Stated the embodiments of the present invention, but above-described embodiment should not be understood as limiting the present invention, this field it is common
Technical staff can be to above-mentioned in the scope of the utility model in the case where not departing from the principles of the present invention and objective
Embodiment is changed, changes, replacing and modification.
Claims (8)
1. a kind of light-emitting diode chip for backlight unit, which is characterized in that including：
Substrate；
And buffer layer, n-type GaN layer, luminescent layer, electronic barrier layer, p-type GaN layer and the electricity sequentially formed over the substrate
Flow diffusion layer；
The electronic barrier layer is equipped with the hole of regular array, and described hole extends downward into luminous layer surface.
2. light-emitting diode chip for backlight unit as described in claim 1, which is characterized in that the luminescent layer is InGaN/GaN Multiple-quantums
Well layer.
3. light-emitting diode chip for backlight unit as claimed in claim 2, which is characterized in that the electronic barrier layer is AlGaN layer.
4. light-emitting diode chip for backlight unit as described in claim 1, which is characterized in that a diameter of 0.3-3.0 microns of described hole.
5. light-emitting diode chip for backlight unit as claimed in claim 4, which is characterized in that the spacing between adjacent holes is 0.3-3.0
Micron.
6. light-emitting diode chip for backlight unit according to claim 1, which is characterized in that the buffer layer includes：
Semiconductor nucleating layer, the semiconductor nucleating layer setting is over the substrate；And
Semiconductor intrinsic layer, semiconductor layer intrinsic layer setting the semiconductor nucleating layer and the n-type GaN layer it
Between.
7. light-emitting diode chip for backlight unit according to claim 1, which is characterized in that further comprise：Stress release layer, it is described
Stress release layer is arranged between the n-type GaN layer and the luminescent layer, and the stress release layer is the InGaN/ of multicycle
GaN layer.
8. light-emitting diode chip for backlight unit according to claim 1, which is characterized in that described hole is round or polygon.
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| CN201721569318.7U CN207818603U (en) | 2017-11-22 | 2017-11-22 | A kind of light-emitting diode chip for backlight unit |
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| CN201721569318.7U CN207818603U (en) | 2017-11-22 | 2017-11-22 | A kind of light-emitting diode chip for backlight unit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109802016A (en) * | 2019-01-11 | 2019-05-24 | 芜湖德豪润达光电科技有限公司 | Transparency conducting layer preparation method, light emitting diode and preparation method thereof |
-
2017
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109802016A (en) * | 2019-01-11 | 2019-05-24 | 芜湖德豪润达光电科技有限公司 | Transparency conducting layer preparation method, light emitting diode and preparation method thereof |
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| TR01 | Transfer of patent right |
Effective date of registration: 20191126 Address after: 518119 1 Yanan Road, Kwai Chung street, Dapeng New District, Shenzhen, Guangdong Patentee after: SHENZHEN BYD MICROELECTRONICS Co.,Ltd. Address before: 516083 Guangdong city of Huizhou province Dayawan xiangshuihe Patentee before: HUIZHOU BYD INDUSTRIAL Co.,Ltd. |
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| CP01 | Change in the name or title of a patent holder | ||
| CP01 | Change in the name or title of a patent holder |
Address after: 518119 No.1 Yan'an Road, Kuiyong street, Dapeng New District, Shenzhen City, Guangdong Province Patentee after: BYD Semiconductor Co.,Ltd. Address before: 518119 No.1 Yan'an Road, Kuiyong street, Dapeng New District, Shenzhen City, Guangdong Province Patentee before: BYD Semiconductor Co.,Ltd. |
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| CP03 | Change of name, title or address | ||
| CP03 | Change of name, title or address |
Address after: 518119 No.1 Yan'an Road, Kuiyong street, Dapeng New District, Shenzhen City, Guangdong Province Patentee after: BYD Semiconductor Co.,Ltd. Address before: 518119 No.1 Yan'an Road, Kwai Chung street, Dapeng New District, Shenzhen City, Guangdong Province Patentee before: SHENZHEN BYD MICROELECTRONICS Co.,Ltd. |