CN107919417A - Light emitting diode and preparation method thereof - Google Patents
Light emitting diode and preparation method thereof Download PDFInfo
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- CN107919417A CN107919417A CN201610881418.7A CN201610881418A CN107919417A CN 107919417 A CN107919417 A CN 107919417A CN 201610881418 A CN201610881418 A CN 201610881418A CN 107919417 A CN107919417 A CN 107919417A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
- H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/10—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a light reflecting structure, e.g. semiconductor Bragg reflector
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Abstract
The present invention proposes light emitting diode and preparation method thereof.The light emitting diode includes：Substrate；First kind semiconductor layer；Multi-quantum well luminescence layer；Second Type semiconductor layer；Superlattice reflection layer, the superlattice reflection layer are arranged between the multi-quantum well luminescence layer and the Second Type semiconductor layer；And substrate, the first kind electrode and the Second Type electrode upside-down mounting are on the substrate.Light emitting diode with said structure can utilize the light that superlattice reflection layer reflection luminous zone is sent, while inverted structure ensure that the light emitting diode and can have preferable heat dissipation performance.Thus, which has more excellent heat dissipation performance and higher luminous efficiency.
Description
Technical field
The present invention relates to semiconductor applications, and in particular, to light emitting diode and preparation method thereof.
Background technology
Light emitting diode (LED) is a kind of junction type electroluminescent semiconductor devices that can convert the electrical signal to optical signal,
Gallium nitride (GaN) based light-emitting diode is as solid state light emitter once appearance just with its high efficiency, long-life, energy conservation and environmental protection, volume
The advantages that small, become international semiconductor and lighting area research and development and industry focus of attention.With gallium nitride (GaN), InGaN
(InGaN), V group nitride materials of III- based on aluminium gallium nitride alloy (AlGaN) and indium nitride gallium aluminium (AlGaInN), due to
Continuously adjustable direct bandwidth (0.7~6.2eV), covers the spectral region from ultraviolet light to infrared light, become manufacture blue light,
The ideal material of green light and white light LED part.
However, current light emitting diode and preparation method thereof still has much room for improvement.
The content of the invention
It is contemplated that solve at least some of the technical problems in related technologies.
The present invention is the following discovery based on inventor and completes：
The LED of Sapphire Substrate is currently based on, the problem of generally existing is difficult to take into account heat dissipation performance and luminous efficiency.Hair
A person of good sense has found that this is mainly due to the LED of such as the positive assembling structure of use, then device thermal diffusivity by further investigation and many experiments
Can be poor, it is difficult among large-power light-emitting diodes.And general upside-down mounting diode structure, although substrate heat dissipation can be solved
The problem of, but on the one hand have stronger suction to light since the eutectic material between electrode and substrate is usually metal alloy
Adduction, on the other hand, the light that luminous zone issues come travel back and reflection between p-type layer, eutectic material and substrate,
The loss that thus shines is serious, has seriously affected luminous efficiency.Although the above problem can also be by using in one layer of p-type layer of outermost
Deposited metal reflection layer is eased between electrode, but due to the Ohmic contact between the metal reflection layer and p-type layer
It is poor, therefore cause the voltage performance of device to be deteriorated, and need the individually redeposition metallic reflection after epitaxial layer has been grown
Layer, manufacture craft are more complicated.
In view of this, in the first aspect of the present invention, the present invention proposes a kind of light emitting diode.It is real according to the present invention
Example is applied, which includes：Substrate；First kind semiconductor layer, the first kind semiconductor layer are arranged on the lining
On bottom, the first kind semiconductor layer has step, and the step is provided with first kind electrode with exterior domain；Multiple quantum wells
Luminescent layer, the multi-quantum well luminescence layer are arranged on the step；Second Type semiconductor layer, the Second Type semiconductor
Layer is arranged in the multi-quantum well luminescence layer, and Second Type electrode is provided with the Second Type semiconductor layer；Superlattices
Reflecting layer, the superlattice reflection layer are arranged between the multi-quantum well luminescence layer and the Second Type semiconductor layer；
And substrate, the first kind electrode and the Second Type electrode upside-down mounting are on the substrate.With said structure
Light emitting diode can utilize the light that superlattice reflection layer reflection luminous zone is sent, while inverted structure ensure that the light-emitting diodes
Manage and there can be preferable heat dissipation performance.Thus, which has more excellent heat dissipation performance and higher
Luminous efficiency.
In another aspect of this invention, the present invention proposes a kind of method for preparing foregoing light emitting diode.Root
According to the embodiment of the present invention, this method includes：First kind semiconductor layer and volume are sequentially formed on the upper surface of the substrate
Sub- trap luminescent layer, Second Type semiconductor layer and superlattice reflection are sequentially formed in the multi-quantum well luminescence layer upper surface
Layer, or sequentially form superlattice reflection layer and Second Type semiconductor layer；To the superlattice reflection layer or described
A part for the upper surface of two type semiconductor layers carries out downward etching processing, removes the superlattice reflection of etch areas
Layer, the Second Type semiconductor layer, the multi-quantum well luminescence layer and a part of first kind semiconductor layer, so as to
Make a part for the first kind semiconductor layer exposed to outer；Using vacuum evaporation technology, in the Second Type semiconductor
Second Type electrode is formed on layer, first kind electrode is formed exposed to outer region in the first kind semiconductor layer；With
And the first kind electrode and the Second Type electrode are inverted on substrate.Thus, it is possible to before easily obtaining
The light emitting diode.This method have operating procedure it is simple, it is of low cost, easy to using existing equipment realize production, have
At least one of the advantages that beneficial to large-scale promotion application.
Brief description of the drawings
Fig. 1 shows the structure diagram of light emitting diode according to an embodiment of the invention；
Fig. 2 shows the structure diagram of light emitting diode in accordance with another embodiment of the present invention；
Fig. 3 shows the structure diagram of the light emitting diode of another embodiment according to the present invention；
Fig. 4 shows the structure diagram of the light emitting diode of another embodiment according to the present invention；
Fig. 5 shows the structure diagram of the light emitting diode of another embodiment according to the present invention；
Fig. 6 shows the structure diagram of superlattice reflection layer according to an embodiment of the invention；And
Fig. 7 shows the structure diagram of first kind semiconductor layer according to an embodiment of the invention.
Reference numeral：
Substrate 100；First kind semiconductor layer 200；Multi-quantum well luminescence layer 300；Superlattice reflection layer 400；Second class
Type semiconductor layer 500；First kind electrode 600；Second Type electrode 700；Substrate 800；
First kind semiconductor nucleating layer 10；First kind semiconductor buffer layer 20；Stress release layer 30；Electronic barrier layer
40；50 Second Type contact layers；Eutectic material 70；Step 1；
AlGaN layer 410；GaN layer 420.
Embodiment
The embodiment of the present invention is described below in detail, the example of the embodiment is shown in the drawings, wherein from beginning to end
Same or similar label represents same or similar element or has the function of same or like element.Below with reference to attached
The embodiment of figure description is exemplary, and is only used for explaining the present invention, and is not considered as limiting the invention.
In one aspect of the invention, the present invention proposes a kind of light emitting diode.According to an embodiment of the invention, refer to
Fig. 1, the light emitting diode include：Substrate 100, first kind semiconductor layer 200, multi-quantum well luminescence layer 300, superlattice reflection
Layer 400, Second Type semiconductor layer 500, first kind electrode 600, Second Type electrode 700 and substrate 800.Wherein,
One type semiconductor layer 200 is arranged on the upper surface of substrate 100, and first kind semiconductor layer 200 has the (reference of step 1
Fig. 7).First kind electrode 600 is arranged on the region beyond the step 1 of first kind semiconductor layer 200, multiple quantum well light emitting
The layer structure setting such as 300 are on the upper surface of step 1.Wherein, superlattice reflection layer 400 is arranged on multi-quantum well luminescence layer 300
And between Second Type semiconductor layer 500.Also, first kind electrode 600 and Second Type electrode 700 are inverted in substrate
On 800.Light emitting diode with said structure can utilize the light that superlattice reflection layer reflection luminous zone is sent, while upside-down mounting
Structure ensure that the light emitting diode and can have preferable heat dissipation performance.Thus, which has more excellent
Heat dissipation performance and higher luminous efficiency.
The concrete structure of the light emitting diode is described in detail with reference to the specific embodiment of the present invention.
According to an embodiment of the invention, substrate 100 can be in advance by patterned.According to an embodiment of the invention,
With reference to figure 2, above-mentioned can be graphically multiple bulge-structures that periodic arrangement is formed in substrate surface.Above-mentioned bulge-structure is favourable
When directly first kind semiconductor layer 200 is prepared using growth technology on the substrate 100, Second Type semiconductor is improved
The quality of layer 200.It should be noted that the concrete shape of above-mentioned bulge-structure and the mode of its periodic arrangement are from spy
Do not limit, as long as template can be provided for the growth of Second Type semiconductor layer, limit Second Type in the horizontal direction and partly lead
The growth rate of body layer.For example, according to a particular embodiment of the invention, bulge-structure can be pointed cone, step and column
The structures such as shape, the bottom width of the bulge-structure can be 2~2.7 μm, highly can be 1.5~1.7 μm.The bulge-structure
Length can be equal with the length or width of 100 upper surface of substrate, and on the substrate 100 on surface along the width of substrate 100
Degree or length direction arrangement, the spacing of two neighboring bulge-structure can be 0.3~1 μm.
According to an embodiment of the invention, first kind semiconductor layer 200 can be N-type semiconductor or P-type semiconductor shape
Into, Second Type semiconductor layer can be that P-type semiconductor or N-type semiconductor are formed.Specific implementation according to the present invention
Example, first kind semiconductor layer 200 can be what n type gallium nitride (GaN) was formed.At this time, Second Type semiconductor layer 500 can be with
Formed by p-type gallium nitride.The quality of first kind semiconductor layer 200 is formed on 100 surface of substrate in order to further improve,
With reference to figure 2, may further include between substrate 100 and first kind semiconductor layer 200：First kind semiconductor nucleating layer
10 and first kind semiconductor layer cushion 20.First kind semiconductor nucleating layer 10 is set on the substrate 100, the first kind
Semiconductor layer cushion 20 is arranged between first kind semiconductor nucleating layer 10 and first kind semiconductor layer 200.Wherein,
First kind semiconductor buffer layer is also known as intrinsic first kind semiconductor layer.Above-mentioned first kind semiconductor nucleating layer 10 and
The methods of first kind semiconductor layer cushion 20 can pass through metal organic chemical compound vapor deposition, is formed directly into graphical
100 upper surface of substrate.When first kind semiconductor layer 200 is N-type GaN, first kind semiconductor nucleating layer can be GaN
Nucleating layer, first kind semiconductor layer cushion 20 can be formed by intrinsic gallium nitride.
According to an embodiment of the invention, multi-quantum well luminescence layer 300 is by multiple InxGa stacked gradually1-xN layers and
What GaN layer was formed.Wherein, 0 ＜ x ＜ 1.In the multi-quantum well luminescence layer, potential well layer thickness can be 2~4 nanometers, potential barrier thickness
Degree can be 8~15 nanometers, and multi-quantum well luminescence layer 300 can contain 1 to 15 InxGa1-xN layers.With the more of said structure
Mqw light emitting layer 300 can improve the combined efficiency of the light emitting diode, be conducive to improve the photism of the light emitting diode
Energy.
According to an embodiment of the invention, superlattice reflection layer 400 can be AlGaN/GaN superlattice structures.Wherein,
AlGaN structures adulterate AlGaN for p-type, and in AlGaN structures, the content of Al can be 10~30% (atomic ratios).AlGaN/GaN
The periodicity of superlattice structure is 20~50, and periodic thickness is 2~4nm.With reference to figure 6, a cycle is by layer successively from bottom to top
A folded AlGaN layer 410 and a GaN layer 420 forms.According to a particular embodiment of the invention, above-mentioned AlGaN/GaN surpasses
Lattice structure can be that Mg adulterates AlGaN/GaN superlattice structures, since the refraction coefficient between AlGaN and GaN is there are difference,
The superlattice structure for two kinds of materials being had differences using refraction coefficient can play light good reflex.Superlattices week
Issue is more, and reflecting effect is better.Al content in AlGaN is higher, and refraction coefficient difference is bigger, and reflecting effect is also better, but
It is that Al content more high-crystal quality is poorer, growth conditions requires harsher.Inventor has found by many experiments, when Al content control
System can obtain preferable reflecting effect when between 10~30%, while growth conditions is controlled in moderate scope, will not
Increase equipment cost.Periodic thickness should not be too thick at the same time, can not be too thin, the too thick effect for not having superlattices, too thin then difficult
To prepare.Inventor has found that periodic thickness control can be in preparation condition harshness not too much in 2~4nm by many experiments
Under the premise of, play preferable superlattice reflection effect.According to an embodiment of the invention, the specific location of above-mentioned superlattice reflection layer
It is not particularly limited, can sets in advance between multi-quantum well luminescence layer 300 and Second Type semiconductor layer 500, Huo Zheshe
Put in the upper surface of Second Type semiconductor layer 500.Inventor has found that superlattice reflection layer 400 is apart from more by many experiments
The distance of quantum trap luminous layer 300 is nearer, and the effect that its reflection luminous zone shines is better, the luminous efficiency of the light emitting diode
It is higher.The structure setting and Position Design of above-mentioned superlattice reflection layer are reasonable, it is possible to prevente effectively from substrate, eutectic material absorb
Shine, improve device light emitting efficiency.Also, the superlattice reflection layer with said structure can utilize growth technology system
It is standby, easy to prepare whole device using growth technology, so as to simplify preparation process, reduce equipment cost.
According to an embodiment of the invention, in order to further improve the performance of the light emitting diode, in first kind semiconductor
Stress release layer 30 is can further include between layer 200 and multi-quantum well luminescence layer 300.It is specific real according to the present invention
Example is applied, stress release layer 30 can be formed by multiple InGaN sub-layers stacked gradually and GaN sub-layers, the thickness of GaN sub-layers
Degree can be 20~40nm, and the thickness of InGaN sub-layers can be 1~5nm.Wherein, in InGaN sub-layers In contents can be 1~
5% (atomic ratio), can contain 3~5 InGaN sub-layers in stress release layer 30.Other embodiments according to the present invention, should
Power releasing layer 30 can also be InGaN/GaN superlattice structures.The periodicity of InGaN/GaN superlattice structures can be 10~
30, periodic thickness is 3~7nm.
According to an embodiment of the invention, in order to further improve the performance of the light emitting diode, which may be used also
To further comprise：Electronic barrier layer 40.With reference to figure 2 and Fig. 3, electronic barrier layer 40 can be arranged on multi-quantum well luminescence layer
Between 300 and the Second Type semiconductor layer 500, electronic barrier layer 40 can be formed by AlGaN.At this time, according to
The embodiment of the present invention, with reference to figure 5, superlattice reflection layer 400 can be arranged on multi-quantum well luminescence layer 300 and electronic blocking
Between layer 40.Other embodiments according to the present invention, with reference to figure 2, superlattice reflection layer 400 can also be arranged on electronic blocking
Between layer 40 and Second Type semiconductor layer 500.
According to an embodiment of the invention, in order to further improve the performance of the light emitting diode, with reference to 2~Fig. 5 of figure, the hair
Optical diode can further include：Second Type contact layer 50.Second Type contact layer 50 is arranged on Second Type and partly leads
On the upper surface of body layer 500, Second Type contact layer 50 can be formed by InGaN.At this time, some realities according to the present invention
Example is applied, with reference to figure 3, superlattice reflection layer 400 can be arranged on Second Type semiconductor layer 500 and Second Type contact layer 50
Between, or (with reference to figure 4) is arranged on the upper surface of Second Type contact layer 50.
According to an embodiment of the invention, figure 1 and Fig. 7,200 upper surface of first kind semiconductor layer are provided with first
Type electrode 600,500 upper surface of Second Type semiconductor layer are provided with Second Type electrode 700.First kind semiconductor layer
200 have step 1, so as to which first kind electrode 600 to be arranged on to the region beyond step 1, it is hereby achieved that the first kind
Electrode 600 and Second Type electrode 700 are located at the structure of light emitting diode the same side.The height H of step 1 can be 500~
2000nm.Specifically, first kind electrode 600 can be by least two metallic elements in Ti, Al, Au, Pt and Sn
Formed, thickness can be 0.2~1 μm.Second Type electrode can be by Ni, Au, Al, Ti, Pd, Pt, Sn and Cr
At least two metallic elements are formed, and thickness is 0.2~1 μm.In order to alleviate the problem of Sapphire Substrate heat dissipation performance is poor, according to this
The embodiment of invention, can pass through Second Type electrode 700 and first kind electrode 600 in eutectic upside-down mounting to substrate 800.
Specifically, eutectic material 70 can be utilized, by the Second Type electrode 700 with mentioned component, 600 upside-down mounting of first kind electrode
Onto substrate 800.In positive assembling structure, the shining for two adapters that shine after encapsulation sends from Second Type semiconductor layer side.
And in inverted structure according to embodiments of the present invention, can be by 600 upside-down mounting of Second Type electrode 700 and first kind electrode
On the substrate 800 of good heat dispersion performance, and shining for device is projected from 100 side of Sapphire Substrate.Eutectic weld with tin cream, lead
The welding materials such as electric elargol are compared, and have more excellent heat conductivility, and eutectic weldering is easy to operate, and cost is also more cheap.
Thus, it is possible to the defects of alleviating the LED heat radiating poor-performing, so as to which according to embodiments of the present invention is shone
Diode applications are in high-power chip.
In conclusion light emitting diode proposed by the present invention has at least one of following advantages：
(1) structure setting of the superlattice reflection layer of the light emitting diode and Position Design are reasonable, it is possible to prevente effectively from
Substrate, eutectic material, which absorb, to shine, and improves device light emitting efficiency；
(2) the superlattice reflection layer of the light emitting diode can be prepared using growth technology, easy to utilize extension
Growing technology prepares whole device, so as to simplify preparation process, reduces equipment cost；
(3) inverted structure can effectively alleviate the shortcomings that device heat dissipation performance is bad, so that the light emitting diode can answer
Among high-power chip；
(4) realize upside-down mounting using eutectic material, be conducive to improve device heat conductivility, reduce production cost.
In another aspect of this invention, the present invention proposes a kind of method for preparing foregoing light emitting diode.Root
According to the embodiment of the present invention, this method includes：
(1) epitaxial growth ray structure
According to an embodiment of the invention, in this step, first kind semiconductor is sequentially formed on the upper surface of the substrate
Layer and multi-quantum well luminescence layer, Second Type semiconductor layer and superlattices are sequentially formed in multi-quantum well luminescence layer upper surface
Reflecting layer, or sequentially form superlattice reflection layer and Second Type semiconductor layer.Wherein, the specific ginseng of said structure is formed
Number is not particularly limited, and those skilled in the art may be referred to the particular type of previously described above-mentioned ray structure, structure etc.
Parameter, is configured the parameter of epitaxial growth.For example, according to an embodiment of the invention, can when growing multi-quantum well luminescence layer
To control growth temperature as 700~850 degrees Celsius.
In order to improve the quality of epitaxial growth first kind semiconductor layer, substrate can pre- first pass through graphical treatment.
Specifically, wet etching or dry etching can be utilized, surface forms multiple bulge-structures of periodic arrangement on substrate.Close
In the concrete shape and arrangement mode of bulge-structure, before detailed description has been carried out, details are not described herein.
According to an embodiment of the invention, can also surface on substrate in advance before first kind type semiconductor layer is grown
Sequentially form first kind semiconductor nucleating layer and first kind semiconductor buffer layer.Specifically, metal can be utilized organic
Vapor Deposition technology, epitaxial lateral overgrowth technology or pendeo epitaxy growing technology formed first kind semiconductor into
Stratum nucleare, then forms first kind semiconductor buffer on first kind semiconductor nucleating layer using high-temperature vacuum evaporation growth
Layer.Wherein, the temperature of high-temperature vacuum evaporation growth can be 900 DEG C to 1300 DEG C, for example, specific implementation according to the present invention
Example, temperature can be 1000 DEG C to 1100 DEG C；Pressure for 100mbar to 800mbar, for example, according to the present invention specific implementation
Example, can be 200~600mbar；The atomic ratio of N atoms and Ga atoms can be 600~1500 in target, specifically, can
Think 900~1200.On first kind semiconductor layer, first kind semiconductor nucleating layer and first kind semiconductor buffer
Layer particular type, before detailed description has been carried out, details are not described herein.Thus, be conducive to further improve preparation
First kind semiconductor layer quality.
According to an embodiment of the invention, before multi-quantum well luminescence layer is prepared, can further include：In the first kind
Stress release layer is formed in type semiconductor layer；Electronics is set to hinder between multi-quantum well luminescence layer and Second Type semiconductor layer
Barrier；And Second Type contact layer is set in Second Type semiconductor layer upper surface.Hindered on above-mentioned stress release layer, electronics
The particular type and structure of barrier and Second Type contact layer, before detailed description has been carried out, it is no longer superfluous herein
State.
According to an embodiment of the invention, the specific location of superlattice reflection layer is not particularly limited, as long as being located at Multiple-quantum
Between trap luminescent layer and Second Type semiconductor layer, or positioned on Second Type semiconductor layer.This area
The concrete structure that technical staff can be included according to the light emitting diode, selects the specific location of superlattice reflection layer.For example,
According to an embodiment of the invention, which can be arranged between multi-quantum well luminescence layer and electronic barrier layer,
Or it is arranged between electronic barrier layer and Second Type semiconductor layer.Other embodiments according to the present invention, superlattices
Reflecting layer can also be arranged between Second Type semiconductor layer and Second Type contact layer, or is arranged on Second Type and is connect
The upper surface of contact layer.
According to an embodiment of the invention, can also be to Second Type semiconductor after the growth of said structure is completed
Layer is activated.Specifically, activation can be under 600-800 DEG C of vacuum or nitrogen atmosphere, to Second Type semiconductor layer
Anneal, or Second Type semiconductor is bombarded using ion beam.
(2) etching forms step
According to an embodiment of the invention, in this step, to the part of the upper surface of previously obtained ray structure into
The downward etching processing of row, to remove all structures of first kind semiconductor layer in said structure, and etches away the
A part for one type semiconductor layer.Thus, it is possible to by a part for first kind semiconductor layer exposed to outer, formation step.
Specific method and etching parameters on etching are not particularly limited, if the said structure of etch areas can be removed, and
Step is formed in first kind semiconductor layer.For example, according to a particular embodiment of the invention, can utilize inductively etc.
Plasma etching technology realizes above-mentioned etching.It will be appreciated to those of skill in the art that the step of above-mentioned etching forms step
It is in order to which the region etch beyond step forms step, to set electrode in subsequent step.To first kind semiconductor
The etching depth that layer performs etching processing can be 500~2000nm, in other words, the height of the step of formation be etched in the step
It can be 500~2000nm to spend (H with reference to shown in figure 7).
(3) electrode is set
According to an embodiment of the invention, in this step, using vacuum evaporation technology, the shape on Second Type semiconductor layer
Into Second Type electrode, first kind electrode is formed on first kind semiconductor.Wherein, first kind electrode is formed in first
Type semiconductor layer upper surface is on outer position, and in other words, first kind electrode is formed in the region beyond step
On.It should be noted that in this step, the design parameter of vacuum evaporation is not particularly limited, those skilled in the art can be with
It is designed according to the concrete condition of electrode.Concrete composition and ruler on first kind electrode and Second Type electrode
It is very little, before have been carried out being described in detail, details are not described herein.
(4) upside-down mounting
According to an embodiment of the invention, in this step, first kind electrode and Second Type electrode are inverted in base
On plate.According to a particular embodiment of the invention, first kind electrode and the can be realized using eutectic weldering by eutectic material
The upside-down mounting of two type electrodes.Thus, it is possible to easily obtain foregoing light emitting diode.
Generally speaking, this method have operating procedure it is simple, it is of low cost, easy to using existing equipment realize production, have
At least one of the advantages that beneficial to large-scale promotion application.
Below by specific embodiment, the present invention will be described, it will be appreciated to those of skill in the art that below
The purpose that is merely to illustrate that of specific embodiment, without limiting the scope of the invention in any way.In addition, below
Embodiment in, unless stated otherwise, used material and facility is commercially available.If in embodiment below
In, specific treatment conditions and processing method are not expressly recited, then can use condition as known in the art and side
Method is handled.
Embodiment 1
(1) substrate is patterned using the method for wet etching, patterned substrate structure is the point of periodic arrangement
Taper is raised, and cone-shaped raised basal diameter is 2.2 μm, is highly 1.5 μm, and spacing is 0.5 μm, and patterned substrate is blue precious
Stone.
(2) it is nucleated in patterned substrate using the method epitaxial growth of gallium nitride of metal organic chemical compound vapor deposition
Layer.Then, high growth temperature intrinsic gallium nitride (first kind semiconductor buffer layer) on gallium nitride nucleating layer, growth temperature is
900 DEG C, pressure 200mbar, the atomic ratio of N atoms and Ga atoms is 900 in target.Finally, grown on intrinsic gallium nitride
Silicon doping N-shaped gallium nitride (first kind semiconductor layer).
(3) the InGaN/GaN structures of multicycle are grown on first kind semiconductor layer as stress release layer.Wherein
The thickness of GaN is 30nm, and the thickness of InGaN is 2nm, and periodicity is 3, and the In contents of InGaN are 2%.
(4) multi-quantum well luminescence layer is grown on stress release layer.The structure of multi-quantum well luminescence layer is InxGa1-xN/
GaN (0 ＜ x ＜ 1)；Potential well layer thickness is 3 nanometers, and barrier layer thickness is 10 nanometers, and the cycle of Quantum Well is 10 cycles.Volume
The growth temperature of minor structure is 700~850 DEG C.
(5) Mg doping AlGaN/GaN superlattices reflector layers, periodic thickness 2nm, week are grown in multi-quantum well luminescence layer
Issue is that the Al content in 20, AlGaN structures is 10%.
(6) the growing aluminum nitride gallium electronic barrier layer on AlGaN/GaN superlattices reflector layers.
(7) Mg doped p types gallium nitride (Second Type semiconductor layer) is grown on aluminium gallium nitride alloy electronic barrier layer.
(8) p-type InGaN contact layers 10 are grown on Second Type semiconductor layer.
(9) Second Type semiconductor layer is activated：Fast speed heat is carried out in the case where temperature is 600-800 DEG C of vacuum
Annealing.
(10) step is etched：The upper surface of structure prepared above is etched using inductive couple plasma body.
Etch areas is etched into first kind semiconductor layer, removes the structure of first kind semiconductor layer in etch areas, and
A part of first kind semiconductor layer is etched away, forms step-like structure.Shoulder height is 500 nanometers.
(11) Second Type electrode, Second Type electricity are prepared using the method growth of evaporation on Second Type semiconductor layer
Extremely Ti/Au alloys, thickness are 0.5 micron.Ti/Al alloys the are prepared on the outer region in first kind semiconductor layer
One type electrode, thickness are 0.5 micron.
(12) by chip using on eutectic material eutectic to substrate.
The structure of the light emitting diode of acquisition is as shown in Figure 5.
Embodiment 2
(1) substrate is patterned using the method for wet etching, patterned substrate structure is the point of periodic arrangement
Taper is raised, and cone-shaped raised basal diameter is 2.5 μm, is highly 1.5 μm, and spacing is 0.8 μm, and patterned substrate is blue precious
Stone.
(2) it is nucleated in patterned substrate using the method epitaxial growth of gallium nitride of metal organic chemical compound vapor deposition
Layer.Then, high growth temperature intrinsic gallium nitride (first kind semiconductor buffer layer) on gallium nitride nucleating layer, growth temperature is
1000 DEG C, pressure 300mbar, the atomic ratio of N atoms and Ga atoms is 1000 in target.Finally, it is raw on intrinsic gallium nitride
Long silicon doping N-shaped gallium nitride (first kind semiconductor layer).
(3) the InGaN/GaN structures of multicycle are grown on first kind semiconductor layer as stress release layer.Wherein
The thickness of GaN is 35nm, and the thickness of InGaN is 5nm, and periodicity is 4, and the In contents of InGaN are 3%.
(4) multi-quantum well luminescence layer is grown on stress release layer.The structure of multi-quantum well luminescence layer is InxGa1-xN/
GaN (0 ＜ x ＜ 1)；Potential well layer thickness is 3 nanometers, and barrier layer thickness is 12 nanometers, and the cycle of Quantum Well is 12 cycles.Volume
The growth temperature of minor structure is 700~850 DEG C.
(5) the growing aluminum nitride gallium electronic barrier layer in multi-quantum well luminescence layer.
(6) Mg doping AlGaN/GaN superlattices reflector layers, periodic thickness 3nm, periodicity are grown on electronic barrier layer
It is 15% for the Al content in 30, AlGaN structures.
(7) Mg doped p types gallium nitride (Second Type semiconductor layer) is grown on superlattices reflector layer.
(8) p-type InGaN contact layers 10 are grown on Second Type semiconductor layer.
(9) Second Type semiconductor layer is activated：Fast speed heat is carried out in the case where temperature is 600-800 DEG C of nitrogen atmosphere
Annealing.
(10) step is etched：The upper surface of structure prepared above is etched using inductive couple plasma body.
Etch areas is etched into first kind semiconductor layer, removes the structure of first kind semiconductor layer in etch areas, and
A part of first kind semiconductor layer is etched away, forms step-like structure.Shoulder height is 1 micron.
(11) Second Type electrode, Second Type electricity are prepared using the method growth of evaporation on Second Type semiconductor layer
Extremely Ti/Au alloys, thickness are 0.8 micron.Ti/Al alloys the are prepared on the outer region in first kind semiconductor layer
One type electrode, thickness are 0.8 micron.
(12) by chip using on eutectic material eutectic to substrate.
The structure of the light emitting diode of acquisition is as shown in Figure 2.
Embodiment 3
(1) substrate is patterned using the method for wet etching, patterned substrate structure is the point of periodic arrangement
Taper is raised, and cone-shaped raised basal diameter is 2.7 μm, is highly 1.7 μm, and spacing is 1 μm, and patterned substrate is blue precious
Stone.
(2) it is nucleated in patterned substrate using the method epitaxial growth of gallium nitride of metal organic chemical compound vapor deposition
Layer.Then, high growth temperature intrinsic gallium nitride (first kind semiconductor buffer layer) on gallium nitride nucleating layer, growth temperature is
1100 DEG C, pressure 400mbar, the atomic ratio of N atoms and Ga atoms is 1100 in target.Finally, it is raw on intrinsic gallium nitride
Long silicon doping N-shaped gallium nitride (first kind semiconductor layer).
(3) multi-quantum well luminescence layer is grown on stress release layer.The structure of multi-quantum well luminescence layer surpasses for InGaN/GaN
Lattice, periodicity 20, periodic thickness 4nm.
(4) multi-quantum well luminescence layer is grown on stress release layer.The structure of multi-quantum well luminescence layer is InxGa1-xN/
GaN (0 ＜ x ＜ 1)；Potential well layer thickness is 4 nanometers, and barrier layer thickness is 15 nanometers, and the cycle of Quantum Well is 14 cycles.Volume
The growth temperature of minor structure is 700~850 DEG C.
(5) the growing aluminum nitride gallium electronic barrier layer in multi-quantum well luminescence layer.
(6) Mg doped p types gallium nitride (Second Type semiconductor layer) is grown on electronic barrier layer.
(7) the growth Mg doping AlGaN/GaN superlattices reflector layers on Second Type semiconductor layer, periodic thickness 4nm,
Periodicity is that the Al content in 35, AlGaN structures is 20%.
(8) p-type InGaN contact layers 10 are grown on superlattices reflector layer.
(9) bombarded using ion beam and Second Type semiconductor layer is activated.
(10) step is etched：The upper surface of structure prepared above is etched using inductive couple plasma body.
Etch areas is etched into first kind semiconductor layer, removes the structure of first kind semiconductor layer in etch areas, and
A part of first kind semiconductor layer is etched away, forms step-like structure.Shoulder height is 1.5 microns.
(11) Second Type electrode, Second Type electricity are prepared using the method growth of evaporation on Second Type semiconductor layer
Extremely Ti/Au alloys, thickness are 1 micron.Ti/Al alloys first are prepared on outer region in first kind semiconductor layer
Type electrode, thickness are 1 micron.
(12) by chip using on eutectic material eutectic to substrate.
The structure of the light emitting diode of acquisition is as shown in Figure 3.
Embodiment 4：
Remaining step is with embodiment 3, the difference is that using InGaN/GaN superlattices as stress release layer, periodicity
For 30, periodic thickness 5nm；After Second Type semiconductor layer is formed, p-type InGaN contact layers are grown on it, are then existed
Mg doping AlGaN/GaN superlattices reflector layers are grown on p-type InGaN contact layers 10.The periodic thickness of superlattices reflector layer is
4nm, periodicity 40, Al content 30%.
The light emitting diode construction of acquisition is as shown in Figure 4.
The luminescent properties of the light emitting diode prepared to 1~embodiment of embodiment 4 carry out test discovery, above-mentioned light-emitting diodes
Pipe is respectively provided with preferable luminous efficiency, and heat dissipation performance is good.Luminous light efficiency under its high current density can reach 100lm/W
More than, the maximum junction temperature under working normally is less than 150 degree.
In the description of the present invention, term " interior ", " outer ", " on ", " under ", "front", "rear", " vertical ", " level ",
The orientation or position relationship of the instructions such as " top ", " bottom " are based on orientation shown in the drawings or position relationship, are for only for ease of and retouch
State the present invention rather than require the present invention must with specific azimuth configuration and operation, therefore it is not intended that to the present invention limit
System.
In the present invention, unless otherwise clearly defined and limited, term " connected ", " connection ", " with reference to ", " fitting " etc.
Term should be interpreted broadly, for example, it may be being connected directly, can also be indirectly connected by intermediate member.For this area
For those of ordinary skill, the concrete meaning of above-mentioned term in the present invention can be understood as the case may be, as long as meeting root
According to the connection relation between all parts of the embodiment of the present invention.
Fisrt feature can be that the first and second features directly contact "above" or "below" second feature, or first and second
Feature passes through intermediary mediate contact.Moreover, fisrt feature second feature " on ", " top " and " above " but first
Feature is directly over second feature or oblique upper, or is merely representative of fisrt feature level height and is higher than second feature.Fisrt feature
Second feature " under ", " lower section " and " below " can be fisrt feature immediately below second feature or obliquely downward, or only
Represent that fisrt feature level height is less than second feature.
In the description of this specification, the description of reference term " one embodiment ", " another embodiment " etc. means to tie
The embodiment particular features, structures, materials, or characteristics described are closed to be contained at least one embodiment of the present invention.At this
In specification, a schematic expression of the above terms does not necessarily refer to the same embodiment or example.Moreover, the tool of description
Body characteristics, structure, material or feature may be combined in any suitable manner in any one or more of the embodiments or examples.This
Outside, without conflicting with each other, those skilled in the art by the different embodiments described in this specification or can show
Example and different embodiments or exemplary feature are combined and combine.
Although the embodiment of the present invention has been shown and described above, it is to be understood that above-described embodiment is example
Property, it is impossible to limitation of the present invention is interpreted as, those of ordinary skill in the art within the scope of the invention can be to above-mentioned
Embodiment is changed, changes, replacing and modification.
Claims (12)
- A kind of 1. light emitting diode, it is characterised in that including：Substrate；First kind semiconductor layer, the first kind semiconductor layer are set over the substrate, the first kind semiconductor Layer has step, and the step is provided with first kind electrode with exterior domain；Multi-quantum well luminescence layer, the multi-quantum well luminescence layer are arranged on the step；Second Type semiconductor layer, the Second Type semiconductor layer are arranged in the multi-quantum well luminescence layer, and described second Second Type electrode is provided with type semiconductor layer；Superlattice reflection layer, the superlattice reflection layer is arranged on the multi-quantum well luminescence layer and the Second Type is partly led Between body layer；AndSubstrate, the first kind electrode and the Second Type electrode upside-down mounting are on the substrate.
- 2. light emitting diode according to claim 1, it is characterised in that the superlattice reflection layer surpasses for AlGaN/GaN Lattice structure, the AlGaN adulterate AlGaN for p-type, and Al atom contents are 10~30% in the AlGaN.
- 3. light emitting diode according to claim 2, it is characterised in that, the cycle of the AlGaN/GaN superlattice structures Number is 20~50.
- 4. light emitting diode according to claim 3, it is characterised in that the substrate and the first kind semiconductor Further comprise between layer：First kind semiconductor nucleating layer, the first kind semiconductor nucleating layer are set over the substrate；AndFirst kind semiconductor layer cushion, the first kind semiconductor layer cushion are arranged on the first kind semiconductor Between nucleating layer and the first kind semiconductor layer.
- 5. light emitting diode according to claim 1, it is characterised in that further comprise：Stress release layer, the stress Releasing layer is arranged between the first kind semiconductor layer and the multi-quantum well luminescence layer.
- 6. light emitting diode according to claim 1, it is characterised in that further comprise：Electronic barrier layer, the electronics Barrier layer is arranged between the multi-quantum well luminescence layer and the Second Type semiconductor layer.
- 7. light emitting diode according to claim 6, it is characterised in that the superlattice reflection layer is arranged on the volume Between sub- trap luminescent layer and the electronic barrier layer, or it is arranged on the electronic barrier layer and the Second Type is partly led Between body layer.
- A kind of 8. method for preparing light emitting diode, it is characterised in that including：First kind semiconductor layer and multi-quantum well luminescence layer are sequentially formed on the upper surface of the substrate, in the multiple quantum wells Luminescent layer upper surface sequentially forms Second Type semiconductor layer and superlattice reflection layer, or sequentially forms superlattice reflection layer And Second Type semiconductor layer；Downward etching is carried out to a part for the upper surface of the superlattice reflection layer or the Second Type semiconductor layer Processing, remove the superlattice reflection layer, the Second Type semiconductor layer, the multi-quantum well luminescence layer of etch areas with And a part of first kind semiconductor layer, to make a part for the first kind semiconductor layer exposed to outer；Using vacuum evaporation technology, Second Type electrode is formed on the Second Type semiconductor layer, in the first kind Semiconductor layer forms first kind electrode exposed to outer region；AndThe first kind electrode and the Second Type electrode are inverted on substrate.
- 9. according to the method described in claim 8, it is characterized in that, further comprise in step (1)：On the substrate Jing Guo the graphical treatment, metal organic chemical compound vapor deposition technology, horizontal extension are utilized Outgrowth technology or pendeo epitaxy growing technology form the first kind semiconductor nucleating layer, are partly led in the first kind On body nucleating layer the first kind semiconductor buffer layer is formed using high-temperature vacuum evaporation growth.
- 10. according to the method described in claim 8, it is characterized in that, before the multi-quantum well luminescence layer is formed, further Including：Stress release layer is formed on the first kind semiconductor layer.
- 11. according to the method described in claim 8, it is characterized in that, further comprise：In the multi-quantum well luminescence layer and Electronic barrier layer is set between the Second Type semiconductor layer.
- 12. according to the method for claim 11, it is characterised in that the superlattice reflection layer is arranged on the Multiple-quantum Between trap luminescent layer and the electronic barrier layer, or it is arranged on the electronic barrier layer and the Second Type semiconductor Between layer.
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