CN110416070A - 半导体器件和制造 - Google Patents

半导体器件和制造 Download PDF

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Publication number
CN110416070A
CN110416070A CN201910343213.7A CN201910343213A CN110416070A CN 110416070 A CN110416070 A CN 110416070A CN 201910343213 A CN201910343213 A CN 201910343213A CN 110416070 A CN110416070 A CN 110416070A
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China
Prior art keywords
semiconductor devices
protective substances
semiconductor substrate
plasma
layer
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CN201910343213.7A
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Inventor
M.卡恩
O.胡姆贝尔
R.K.约希
P.S.科赫
A.科普罗夫斯基
B.莱特尔
C.迈尔
G.施密特
J.施泰因布伦纳
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Infineon Technologies AG
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Infineon Technologies AG
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Abstract

公开了半导体器件和制造。一种用于制造高电压半导体器件的方法，包括将半导体衬底暴露于等离子体以在半导体衬底上形成保护物质层。半导体器件包括半导体衬底和在半导体衬底上的保护物质层。

Description

半导体器件和制造
背景技术
在恶劣条件下，例如，当在高温下或者在高湿度环境中操作时，在功率半导体器件中使用的电介质膜倾向于不稳定。例如，在恶劣条件下，当在大约100小时的持续时间内暴露于具有80%或者更高的湿度、在80℃或者更高的温度处的大气时，作为电介质膜使用的氧化物层吸收水分，导致电漂移现象并且电介质膜无法耐受等于或者大于大约80%的功率半导体器件的最大设计电压。
已经将非晶碳化硅（a-SiC）膜用于增加功率半导体电阻。当暴露于如在功率半导体器件的操作中是典型的强电场时，水经历蛋白质水解。作为结果，在功率半导体器件中的阳极部分中，非晶碳化硅被氧化。
独立权利要求在各个方面限定本发明。从属权利要求说明在各个方面的根据本发明的实施例的所选择的要素。
发明内容
在一方面中，公开了用于制造高电压半导体器件的方法。该方法包括将半导体衬底暴露于等离子体以在衬底上形成保护物质层。所述等离子体包括惰性类别。
在一方面中，公开了一种半导体器件。半导体器件包括半导体衬底和保护物质层。保护物质层包括由如下组成的组中的一个或多个：晶体碳化硅、非晶碳化硅、氮化物。
独立权利要求在各方面说明本发明。从属权利要求说明根据本发明的实施例。
附图说明
随附附图被包括以提供对本发明进一步的理解并且随附附图被合并在本说明书中并且构成本说明书的一部分。附图图示本发明的实施例并且与描述一起服务于解释本发明的原理。
图1是图示根据一些实施例的方法的流程图。
图2A是示意性地图示根据一些实施例的半导体衬底的横截面局部视图的示意图。
图2B是示意性地图示根据一些实施例的半导体半成品的横截面局部视图的示意图。
图2C是示意性地图示根据一些实施例的半导体器件的横截面局部视图的示意图。
同样的参考标号指定对应的相似部分。附图的元件不必要相对于彼此成比例。特别是，横截面视图并未按比例画出并且图示结构的尺寸关系可以与图示的那些不同。因为根据本发明的实施例的组件可以被定位在许多不同的定向上，所以可以将方向术语用于图示的目的，然而，除非明确相反地规定，否则决不加以限制。应当注意的是示范性实施例的视图仅仅是为了图示实施例的选择的特征。
根据本发明的其它实施例以及本发明的很多意图的优点将容易被领会，因为通过参照以下详细描述它们变得更好理解。要理解的是可以利用其它实施例并且可以在不脱离本发明的范围的情况下作出结构上或者逻辑上的改变。因此，以下的详细描述不意图在限制意义上取得，并且本发明的范围是由所附权利要求来限定的。
具体实施方式
下面，参照随附附图公开实施例、实现和相关联的效果。
图1是图示根据一些实施例的方法100的流程图。一般地，所述方法可以在（例如从晶片）制造高电压半导体器件中使用。当在下面解释所述方法时，还将参照在图2A、图2B和图2C中图示的示例性半导体器件200。然而，应当理解的是，如技术人员将容易地领会那样，方法100还能够被用于制造可以与仅仅是示范性实施例的半导体器件200不同的半导体器件。
在S110处，提供诸如晶片的衬底210（图2A）。例如，衬底210可以是晶体。在一些实施例中，衬底210的材料是半导体。在一些实施例中，晶体衬底210包括由如下组成的一组材料中的一个或多个：硅、碳化硅、砷化镓、氮化镓。
在S120处，将氧化物211从衬底210移除。例如，移除可以通过抛光衬底210来实现。在一些实施例中，将衬底210放置在等离子体室中。等离子体室可以封闭等离子体。然后，在等离子体室中，可以将氧化物211从衬底210移除。特别是，通过将表面212暴露于等离子体可以将氧化物211从衬底210的面对该室中开放空间的表面212移除。至少一个效果可以是要被制造的半导体器件变得更加可靠。特别是，如参照图2B可以看到那样，在没有氧化物211的情况下，可以很好地限定在衬底210的边界表面212处到另外的物质层的转变。
在S130处，将衬底210暴露于第二等离子体。应当理解的是在一些实施例中，第一等离子体也是第二等离子体。在一些实施例中，第二等离子体包括惰性类别。例如，等离子体可以包括氦和/或氩。在一些实施例中，等离子体包括由如下组成的一组成分中的一个或多个：氮离子、碳离子、甲烷、次乙基、乙烯。至少一个效果可以是等离子体在衬底210上沉积等离子体粒子，由此在衬底上构建保护物质层220。因此在一些实施例中，保护物质层直接构建在衬底上。在一些实施例中，在一个步骤中执行将氧化物从衬底210的表面移除以及将表面210暴露于等离子体。
在一些实施例中，方法包括在等离子体室中提供气体。所述气体可以被暴露于交变电场。至少一个效果可以是等离子体的一些粒子被剥离掉一个或多个电子以便变成带电粒子，即，因此形成等离子体的离子。
在一些实施例中，等离子体的成分中的一些（即，包括在等离子体中的粒子中的一些）与衬底材料或者其它材料化学地反应。因此，在一些实施例中，在衬底210上形成的保护物质层220包括由如下组成的一组材料中的一个或多个：晶体碳化硅、非晶碳化硅、氮化物。
在一些实施例中，方法包括将衬底加热到从300℃至500℃的温度。在一些实施例中，方法包括将衬底加热到从350℃至450℃的温度。在一些实施例中，方法包括将衬底加热到从390℃至410℃的温度。至少一个效果可以是能够特别高效地完成氧化物移除和/或沉积处理。
在一些实施例中，将等离子体保持在小于或者等于大气压力的压力下。至少一个效果可以是能够利用有益于沉积如所要求的那么多物质的精度水平来控制沉积处理，以在衬底210上形成想要的保护层220。在一些实施例中，将等离子体保持在从0.1 kPa至2kPa的范围中的压力下。例如，将等离子体保持在从1 kPa至1.2kPa的范围中的压力下。
在一些实施例中，将衬底210暴露于等离子体的步骤（S130）包括在等离子体中提供交变电场。至少一个效果可以是离子通过交变电场被加速。因此，一些离子可以猛烈撞击暴露于等离子体的衬底表面。因此，衬底210的表面被加热，衬底210的原子可以与等离子体粒子进行反应，并且离子可以被捕获在衬底的表面上。在一些实施例中，电场以射频频率交替。在一些实施例中电场以从10MHz至30MHz的频率交替。例如，该方法包括使得电场以从13.5MHz至13.6MHz的频率交替，诸如使得电场以13.56MHz的频率交替。至少一个效果可以是可以利用上面规定的成分中的一个或多个来特别高效地完成等离子体沉积处理。
在S140处在保护层220上提供结构层230。结构层230的至少一个效果可以是向半导体器件200提供功能。
图2C是示意性地图示根据一些实施例的示范性半导体器件200的横截面局部视图的示意图。半导体器件200包括衬底210以及在边界表面212处部署在衬底210上方的保护物质层220。在一些实施例中，将保护物质层220原位沉积在衬底210上。保护物质层的至少一个效果可以是确保高的击穿电压。
在一些实施例中，如将在下面更详细地解释的那样，半导体器件200包括被配置为向半导体器件200提供功能的至少一个器件结构层230。在一些实施例中，器件结构层230被形成在保护物质层220上。然而，在一些实施例中（未示出），器件结构层也可以被形成在保护物质层下方。
半导体器件200可以包括各种类型的有源器件和无源器件，诸如二极管、晶体管、晶闸管、电容器、电感器、电阻器、光电器件、传感器、微电子机械系统和其它。在各种实施例中，半导体器件200可以包括集成电路或者单个电的、机械的或者机械电子的元件。另外，半导体器件200可以是微电子机械系统（MEMS）器件、功率晶体管、逻辑芯片、存储器芯片、模拟芯片、混合信号芯片及其组合，诸如芯片上系统或者其它适合类型的器件。
在一些实施例中，半导体器件200是功率半导体器件。至少一个效果可以是半导体器件200可以在高电压下操作。另一个效果可以是半导体器件200可以利用高电流操作。
在一些实施例中，衬底210是晶体。在一些实施例中，晶体衬底210包括由如下组成的组中的一个或多个：硅、碳化硅、砷化镓、氮化镓。
在一些实施例中，保护物质层220包括由如下组成的组中的一个或多个：晶体碳化硅、非晶碳化硅、氮化物。
在一些实施例中，保护物质层220具有从2至3 g/cm^3（hex.）的密度。
在一些实施例中，保护物质层220大多包括碳化硅并且具有至少2.2 g/cm^3（hex.）的密度。
在一些实施例中，保护物质层220大多包括氮化硅并且具有至少2.2 g/cm^3（hex.）的密度。
在一些实施例中，保护物质层220具有重量上小于百分之一的聚合物含量。在一些实施例中，保护物质层220具有重量上小于千分之一的聚合物含量。至少一个效果可以是抵抗杂质扩散的保护特别强。
在一些实施例中，保护物质层220具有多于1千伏每微米的击穿电压。在一些实施例中，该保护物质层具有多于10千伏每微米的击穿电压。
在一些实施例中，保护物质层220在+/-0.5GPa的量程范围（corridor）中（优选地在+/-0.2GPa的量程范围中）具有与按照表达式y=-15.375x+10.825的直线相关的硬度y[GPa]相对于压缩应力x[GPa]的特性。
在一些实施例中，物质层220的在从3350nm至2350nm的波长范围中的吸收谱本质上是波长的线性函数。
在一些实施例中，电介质层的在从2350nm至1850nm的波长范围中的谱中的吸收峰具有多于50nm（优选地为多于60nm）的整体宽度，其中整体宽度被定义为峰面积/峰最大值的比率，并且其中峰面积是在吸收谱（减去背景）的曲线下的面积。
要理解的是，除非另外具体地指出，否则在此描述的各种实施例的特征可以被彼此组合。
虽然已经在此图示并且描述了特定的实施例，但是本领域普通技术人员将领会的是，在不脱离本发明的范围的情况下，各种各样的替换和/或等同的实现可以代替所示出和描述的特定实施例。本申请意图覆盖在此讨论的特定实施例的任何适配或者变化。
在一些实例中，省略或者简化了众所周知的特征以阐明示范性实现的描述。
如在此使用的那样，词语“示范性”意味着充当示例、实例或者图示。不必要将在此作为“示范性”而描述的任何方面或者设计解释为较之其它方面或者设计是优选的或者有利的。相反，词语“示范性”的使用意图以具体的方式呈现概念和技术。例如，如通过在此描述的上下文指示的那样，术语“技术”可以指代一个或多个器件、装置、系统、方法、制造的物品和/或计算机可读指令。
如在此使用的那样，除非另外指定或者从上下文中清楚地得出单数形式，否则量词“一”和“一个”一般应当被解释为意味着“一个或多个”。
如在此使用的那样，术语“具有”、“包含”、“包括”、“带有”或者其变型等的术语是意图为包括性的开放式术语。这些术语指示所声明的要素或者特征的存在但是不排除附加的要素或者特征。

Claims (19)

1.一种用于制造高电压半导体器件（200）的方法，所述方法包括：
将半导体衬底（210）暴露于等离子体以在衬底（210）上形成保护物质层（220），
其中所述等离子体包括惰性类别，并且
其中所述等离子体包括由如下组成的组中的一个或多个：氢类别、碳类别、甲烷、次乙基、乙烯。
2.如权利要求1所述的方法，
其中所述惰性类别是从由氦类别和氩类别组成的一组类别中的一个或多个选择的。
3.如权利要求1或者权利要求2所述的方法，所述方法包括：
将所述半导体衬底（210）加热到从300℃至500℃的温度。
4.如权利要求1至权利要求3中的任何一个所述的方法，
提供交变电场，并且
将气体暴露于所述交变电场，
其中电场以射频频率交替。
5.如权利要求1至权利要求4中的任何一个所述的方法，
其中所述等离子体被保持在小于或者等于大气压力的压力下。
6.如权利要求1至权利要求5中的任何一个所述的方法，
所述方法进一步包括：
将氧化物（211）从所述半导体衬底（210）移除。
7.如权利要求6所述的方法，
将所述半导体衬底（210）放置在室中；并且
然后在执行将所述半导体衬底（210）暴露于所述等离子体之前，执行将所述氧化物（211）从所述半导体衬底（210）移除。
8.一种半导体器件（200），包括：
半导体衬底（210）；以及
在所述半导体衬底（210）上的保护物质层（220），
其中所述保护物质层（220）包括由如下组成的组中的一个或多个：晶体碳化硅、非晶碳化硅。
9.如权利要求8所述的半导体器件（200），进一步包括：
在所述保护物质层（220）上的器件结构层（230）。
10.如权利要求9所述的半导体器件（200），
其中所述保护物质层（220）被原位沉积在所述半导体衬底（210）上。
11.如权利要求8至权利要求10中的任何一个所述的半导体器件（200），
其中所述保护物质层（220）具有从2至3g/cm^3（hex.）的密度。
12.如权利要求11所述的半导体器件（200），
其中所述保护物质层（200）大多包括碳化硅并且具有至少2.2g/cm^3（hex.）的密度。
13.如权利要求8至权利要求12中的任何一个所述的半导体器件（200），
其中所述保护物质层（220）具有重量上小于百分之一的聚合物含量。
14.如权利要求8至权利要求13中的任何一个所述的半导体器件（200），
其中所述保护物质层（220）具有多于1千伏/微米的击穿电压。
15.如权利要求8至权利要求14中的任何一个所述的半导体器件（200），
其中所述保护物质层（220）在+/-0.5GPa的量程范围中具有与按照表达式y=-15.375x+10.825的直线相关的硬度y[GPa]相对于压缩应力x[GPa]的特性。
16.如权利要求8至权利要求15中的任何一个所述的半导体器件（200），
其中所述保护物质层（220）的在从3350nm至2350nm的波长范围中的吸收谱本质上是波长的线性函数。
17.如权利要求8至权利要求16中的任何一个所述的半导体器件（200），
其中所述保护物质层（220）的在从2350nm至1850nm的波长范围中的谱中的吸收峰具有多于50nm的整体宽度。
18.如权利要求8至权利要求17中的任何一个所述的半导体器件（200），
其中所述半导体衬底（210）是晶体。
19.如权利要求18所述的半导体器件（200），
其中所述晶体半导体衬底（210）包括由如下组成的组中的一个或多个：硅、碳化硅、砷化镓、氮化镓。
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