CN110414158A - A kind of laminated chips hot property optimization method - Google Patents
A kind of laminated chips hot property optimization method Download PDFInfo
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- CN110414158A CN110414158A CN201910705941.8A CN201910705941A CN110414158A CN 110414158 A CN110414158 A CN 110414158A CN 201910705941 A CN201910705941 A CN 201910705941A CN 110414158 A CN110414158 A CN 110414158A
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Abstract
The present invention provides a kind of laminated chips hot property optimization method, and the optimization method step is step 1: the initial junction temperature value of chip is obtained according to the original dimension of chip various components and the emulation of corresponding material；Step 2: seven kinds of factors for influencing junction temperature are chosen, and determine suitable orthogonal arrage；Step 3: obtaining effect tendency figure using the range analysis of orthogonal arrage, and variation range of each factor under different value conditions is in observation figure to obtain influencing the principal element of junction temperature and the optimal value of each factor；Step 4: the optimal value combination post-simulation of each factor is obtained into optimal junction temperature, optimal junction temperature is made comparisons with initial junction temperature before, discovery junction temperature decreased significantly, and chip hot property is optimized.After the optimization method, the optimal value of final junction temperature reduces by 8.38% than initial junction temperature value.
Description
Technical field
The present invention relates to chip encapsulation technology field more particularly to a kind of laminated chips based on orthogonal are hot
It can optimization method.
Background technique
Nowadays, the short interconnection that Stacked Die Packaging has due to it, high interconnection density, the advantages such as high reliability,
It is widely used in small size portable electronic product.However, chip heat production also correspondingly increases with the increase of power consumption, knot
Warm constantly to increase, final chip is failed due to overheat.Therefore, laminated chips are optimized to improve the change of its hot property
It obtains more and more important.
There are mainly two types of schemes for the design method optimized for laminated chips hot property.Certain a kind of for for chip
A component optimizes, for example reduces heat sink thermal resistance to improve the heat dissipation performance of chip, increases the area of substrate to mention
The radiating efficiency etc. of high chip.The deficiency of this method is, does not account for the factor of various aspects, and effect of optimization is not
Obviously.Another kind is the size and material for comprehensively considering chip interior various components, constantly changes combination and comes to chip
It is hot to can be carried out comprehensive analysis, to obtain optimal design scheme, reduce junction temperature of chip.The deficiency of this method is: for
For the experiment of multifactor, more values, experimental quantities are more if carrying out analysis comprehensively, and experimental data management is inconvenient, therefore low efficiency.
Summary of the invention
To solve the above problems, it is an object of the invention to provide a kind of, the laminated chips hot property based on orthogonal is excellent
Change method can determine the optimal value of the principal element and each factor that influence junction temperature of chip by less experiment, therefore described
Method test number is less, high-efficient；The material of various components, size can freely be chosen in orthogonal arrage, therefore flexibility is good；Separately
Outside, after using the optimization method, the optimal value of final junction temperature reduces by 8.38% than initial junction temperature value, therefore, optimization method effect
Fruit is particularly evident.
The present invention provides a kind of laminated chips hot property optimization method, and the optimization method step is
Step 1: the initial junction temperature of chip is obtained according to the original dimension of chip various components and the emulation of corresponding material
Value；
Step 2: seven kinds of factors for influencing junction temperature are chosen, and determine suitable orthogonal arrage；
Step 3: effect tendency figure is obtained using the range analysis of orthogonal arrage, each factor is in different values in observation figure
In the case of variation range to obtain influence junction temperature principal element and each factor optimal value；
Step 4: obtaining optimal junction temperature for the optimal value of each factor combination post-simulation, by optimal junction temperature with before just
Beginning junction temperature is made comparisons, and discovery junction temperature decreased significantly, and chip hot property is optimized.
Further improvement lies in that: the factor for the influence junction temperature chosen in the step 2 is respectively welding layer material, layer thickness
Degree, baseplate material, substrate thickness, chip bonding glue material, chip adhesive glue thickness and pin material.
Further improvement lies in that: suitable orthogonal arrage is that four factor four is horizontal and three factor two is horizontal in the step 2
Orthogonal array, be denoted as L16(44×23)。
Further improvement lies in that: the welding layer material selects BiAgX or PbSn5Ag2.5 or CRM-1800 or Sintering
Silver, for layer with a thickness of 0.04~0.1mm, baseplate material uses Al2O3 or BN or BeO or Cu-C, and substrate thickness is 0.5~
0.8mm, chip adhesive glue material selection Epoxy resin or DAF, chip adhesive glue is with a thickness of 0.02mm~0.04mm, pin
Material selection Cu or Al.
Further improvement lies in that: the orthogonal arrage carries out 16 groups of experiments altogether.
Further improvement lies in that: the effect tendency figure in the step 3 is drawn according to the result of orthogonal arrage range analysis
It obtains, each factor corresponding junction temperature in different values is contained in figure, each factor junction temperature in different values has
Variation, variation range is bigger, then the factor is bigger to junction temperature influence degree.
Further improvement lies in that: in effect tendency figure, if a factor corresponding junction temperature value under some value condition
It is minimum, then it is assumed that this value is the optimal value of the factor.
Beneficial effects of the present invention: core is obtained according to the original dimension of chip various components and the emulation of corresponding material first
The initial junction temperature value of piece；Secondly seven kinds of factors for influencing junction temperature are chosen, and determine suitable orthogonal arrage.Using the very poor of orthogonal arrage
Analysis obtains effect tendency figure, and variation range of each factor under different value conditions is in observation figure to obtain influencing junction temperature
Principal element and each factor optimal value；The optimal value combination post-simulation of each factor is finally obtained into optimal junction temperature,
Optimal junction temperature is made comparisons with initial junction temperature before, after the optimization method, the optimal value of final junction temperature is than initial knot
Temperature value reduces by 8.38%.
Detailed description of the invention
Fig. 1 is laminated chips structural schematic diagram of the invention.
Fig. 2 is laminated chips internal structure enlarged drawing of the invention.
Fig. 3 is initial temperature cloud charts of the invention.
Fig. 4 is the effect tendency figure of each factor of the invention.
Fig. 5 is optimal junction temperature of chip figure of the invention.
Specific embodiment
Technical solution of the present invention is described in further detail with reference to the accompanying drawings of the specification.
The present invention provides a kind of laminated chips hot property optimization method, and the optimization method step is
Step 1: the initial junction temperature of chip is obtained according to the original dimension of chip various components and the emulation of corresponding material
Value；
Step 2: seven kinds of factors for influencing junction temperature are chosen, and determine suitable orthogonal arrage；
Step 3: effect tendency figure is obtained using the range analysis of orthogonal arrage, each factor is in different values in observation figure
In the case of variation range to obtain influence junction temperature principal element and each factor optimal value；
Step 4: obtaining optimal junction temperature for the optimal value of each factor combination post-simulation, by optimal junction temperature with before just
Beginning junction temperature is made comparisons, and discovery junction temperature decreased significantly, and chip hot property is optimized.
It as shown in Figure 1, 2, is laminated chips structure chart and chip internal structure enlarged drawing, by first level logical chip
(Die3), two layers of storage chip (Die2 and Die1), wall (Spacer), chip adhesive glue (Adh3, Adh2 and Adh1), weldering
Layer (Adh0), substrate (Substrate) and pin (Pin) composition.The size and material of various components in chip such as 1 institute of table
Show.
The size and material property of 1 chip assembly of table
As shown in figure 3, being the initial temperature cloud charts of chip.At this point, apply 1W on logic chip, two layers of storage chip
Upper application 0.25W, environment temperature are set as 25 DEG C, and chip is under conditions of free convection, and convection transfer rate is set as 6W/
m2·K.From the figures it is clear that the junction temperature of chip is 79.577 DEG C, appear on top layer chip.The junction temperature is initial
Junction temperature, next work is that the material for being directed to initial chip assembly and size optimize, to obtain optimal junction temperature, and will most
Excellent junction temperature is made comparisons with initial junction temperature (79.577 DEG C).
As shown in figure 4, being the effect tendency figure of each factor.Before selecting suitable orthogonal arrage, need to determine first
Influence the factor of junction temperature.This patent mainly considers seven kinds of factors, is respectively as follows: welding layer material, layer thickness, baseplate material, substrate
Thickness, chip bonding glue material, chip adhesive glue thickness and pin material.Four levels are arranged in each factor of first four factor,
Two levels are arranged in other factors.Table 2 lists the specific material or specific size of each level representation of all factors.Table 3
List the thermal conductivity of all material.
The each factor of table 2 and its level
The material thermal conductivity of each component of table 3
After the factor for choosing influence junction temperature, so that it may determine corresponding orthogonal arrage, the orthogonal arrage that this patent is chosen is mixed
Close orthogonal arrage L16(44×23), which is horizontal by four factor four and three factors, two horizontal combination forms, and carries out 16 times altogether
Experiment.Specific material and size are substituted into orthogonal arrage, and simulate the junction temperature under each combined situation, as shown in table 4.
The experimental result of 4 orthogonal arrage of table
After the experimental result for obtaining orthogonal arrage, need on orthogonal arrage carry out range analysis with obtain influence junction temperature it is crucial because
The optimal value of plain and each factor.Shown in the calculation formula of the range analysis of first four factor such as formula (1), rear three factors
Shown in the calculation formula of range analysis such as formula (2).
Wherein, TilRefer to the junction temperature of chip, KiRefer to for some specific factor, if its level index is i,
It sums, final stack result is exactly Ki。kiRefer to KiIt averages, R refers to the maximum value of some specific factor kx
Minimum value is subtracted, as the factor is very poor.Calculation method more than can carry out range analysis to each factor, most
The results are shown in Table 5 eventually.
The range analysis result of 5 factor of table
Factor it is very poor bigger, illustrate that influence of the factor to junction temperature of chip is more significant, from the point of view of the sequence of very poor result,
Chip bonds the influence > influence of the baseplate material to junction temperature of chip > of glue material and chip adhesive glue thickness to junction temperature of chip and draws
Foot material is to influence > substrate thickness of junction temperature of chip to influence > welding layer material of junction temperature of chip to influence > layer of junction temperature of chip
Influence of the thickness to junction temperature of chip.Chip bonds glue material and the two factors of chip adhesive glue thickness to the shadow of junction temperature of chip
Sound is the most obvious, and the influence very little of welding layer material and its thickness to junction temperature.In order to more clearly from find out each factor to knot
Data in table 5 are depicted as chart, as shown in Figure 4 by the influence degree of temperature.For a factor, if in some value
In the case of, junction temperature value is minimum, then the value is known as to the optimal value (optimal level) of the factor.From Fig. 3, it can be determined that go out each
The corresponding optimal level of a factor: the optimal level of factor A is 4, and the optimal level of factor B is 3, and the optimal level of factor C is
The optimal level of 4, factor D are 4, and the optimal level of factor E is 2, and the optimal level of factor F is 1, and the optimal level of factor G is
1。
As shown in figure 5, being optimal junction temperature of chip figure.It is emulated again after combining the optimal value of each factor, i.e.,
Optimal junction temperature of chip can be obtained.It is the minimum of all experiments it can be found that the junction temperature of chip is 72.909 DEG C from figure.
Optimal junction temperature value is made comparisons with initial junction temperature value, as shown in table 6.
The initial junction temperature of table 6 is compared with optimal junction temperature
| Initial junction temperature (DEG C) | 79.577 |
| Optimal junction temperature (DEG C) | 72.909 |
| Reduction ratio (%) | 8.38 |
It can be found that the hot property of chip can be effectively improved using Orthogonal Experiment and Design from table 6, final junction temperature decline
8.38%.
Claims (7)
1. a kind of laminated chips hot property optimization method, it is characterised in that: the optimization method step is
Step 1: the initial junction temperature value of chip is obtained according to the original dimension of chip various components and the emulation of corresponding material；
Step 2: seven kinds of factors for influencing junction temperature are chosen, and determine suitable orthogonal arrage；
Step 3: effect tendency figure is obtained using the range analysis of orthogonal arrage, each factor is in different value conditions in observation figure
Under variation range to obtain influence junction temperature principal element and each factor optimal value；
Step 4: the optimal value combination post-simulation of each factor is obtained into optimal junction temperature, by optimal junction temperature and initial knot before
Temperature is made comparisons, and discovery junction temperature decreased significantly, and chip hot property is optimized.
2. a kind of laminated chips hot property optimization method as described in claim 1, it is characterised in that: chosen in the step 2
Influence junction temperature factor be respectively welding layer material, layer thickness, baseplate material, substrate thickness, chip bonding glue material, chip
Adhesive glue thickness and pin material.
3. a kind of laminated chips hot property optimization method as described in claim 1, it is characterised in that: suitable in the step 2
Orthogonal arrage be four factor four is horizontal and three factor two is horizontal orthogonal array, be denoted asL 16(44×23)。
4. a kind of laminated chips hot property optimization method as claimed in claim 2, it is characterised in that: the welding layer material is selected
BiAgX or PbSn5Ag2.5 or CRM-1800 or Sintering silver, layer are adopted with a thickness of 0.04 ~ 0.1mm, baseplate material
With Al2O3 or BN or BeO or Cu-C, substrate thickness is 0.5 ~ 0.8mm, chip adhesive glue material selection Epoxy resin or
DAF, chip adhesive glue is with a thickness of 0.02mm ~ 0.04mm, pin material selection Cu or Al.
5. a kind of laminated chips hot property optimization method as claimed in claim 3, it is characterised in that: the orthogonal arrage carries out altogether
16 groups of experiments.
6. a kind of laminated chips hot property optimization method as described in claim 1, it is characterised in that: the shadow in the step 3
Ringing tendency chart is drawn according to the result of orthogonal arrage range analysis, and each factor is contained in figure in different values pair
The junction temperature answered, each factor junction temperature in different values can change, and variation range is bigger, then the factor is to junction temperature influence degree
It is bigger.
7. a kind of laminated chips hot property optimization method as claimed in claim 6, it is characterised in that: in effect tendency figure,
If a factor corresponding junction temperature value under some value condition is minimum, then it is assumed that this value is the optimal value of the factor.
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Cited By (3)
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| CN113128171A (en) * | 2019-12-12 | 2021-07-16 | 南通大学 | Optimization method for optimizing wafer level packaging reliability |
| CN113139277A (en) * | 2021-03-30 | 2021-07-20 | 深圳佰维存储科技股份有限公司 | Packaging structure heat dissipation optimization method and device, readable storage medium and electronic equipment |
| CN113326617A (en) * | 2021-06-02 | 2021-08-31 | 郑州大学 | Microfluidic chip injection molding process parameter optimization method based on PB test and orthogonal test |
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