CN202736904U - Copper pour silicon basal plate - Google Patents
Copper pour silicon basal plate Download PDFInfo
- Publication number
- CN202736904U CN202736904U CN 201220401857 CN201220401857U CN202736904U CN 202736904 U CN202736904 U CN 202736904U CN 201220401857 CN201220401857 CN 201220401857 CN 201220401857 U CN201220401857 U CN 201220401857U CN 202736904 U CN202736904 U CN 202736904U
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- copper
- copper layer
- electrode lead
- silicon
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
The utility model belongs to the technique of electronic packaging and relates to a copper pour silicon basal plate for power device packaging. The basal plate is provided with a chip welding area copper layer and an upper electrode lead area copper layer on the upper surface of a silicon slice. The chip welding area copper layer and the upper electrode lead area copper layer are formed by thermo-compression bonding. A heat conducting and stress-compression copper layer formed in a mode of thermo-compression bonding and a lower electrode lead area are arranged on the lower surface of the silicon slice. The upper electrode lead area copper layer and the lower electrode lead area copper layer are connected with each other through a copper cylinder in the inner hole of the silicon slice. Each copper layer is of the same thickness and is manufactured in a mode of bonding on the silicon slice surface after the alternative erosion on the surface of the copper foil. The copper pour silicon basal plate causes the existence of a nano-porous copper layer through the alternative erosion on the surface of the copper foil and the copper layer is taken as the thermo-compression bonding layer between the copper foil and the silicon slice. High intensity bonding between the copper foil and the silicon slice can be achieved under lower temperature and pressure because of nanoscale effect. The thermal stress between the metal copper layer and the silicon slice can be effectively released and the usability and the reliability of the copper pour silicon basal plate can be improved because of the existence of the nanopore structure, and therefore the requirements of power device packaging and heat dissipation are satisfied.
Description
Technical field
The utility model belongs to the Electronic Packaging manufacturing technology, is specifically related to a kind of power device package with covering the copper silicon substrate.
Prior art
Along with three-dimensional packaging technology development and level of integrated system improve, take large-power light-emitting diodes (LED), igbt (IGBT), laser (LD) in the power device manufacture process of representative, selecting of heat-radiating substrate becomes crucial sport technique segment, and directly has influence on serviceability and the reliability of device.For Electronic Packaging, heat-radiating substrate mainly is high heat conductance itself that utilize its material to have, and heat is derived from chip, realizes and extraneous electrical interconnection and heat exchange.But for power device package, substrate is except possessing basic wiring (electrical interconnection) function, also require to have higher heat conduction, insulation, high temperature resistant, proof voltage ability and thermal matching energy, the general ceramic copper-clad base plate (be exactly the composite construction of metal copper layer and potsherd, this structure takes full advantage of the insulation of high conduction, the capacity of heat transmission and the ceramic substrate of copper layer, heat-resisting, proof voltage ability) that adopts.Ceramic copper-clad plate commonly used comprise the preparation of thick film firing technique metallized ceramic base plate, the preparation of high temperature Direct Bonding technique cover that copper ceramic wafer (DBC) and directly electroplating technology prepare cover copper ceramic wafer (DPC).Ceramic Substrate Material commonly used then is aluminium oxide, aluminium nitride, carborundum and beryllium oxide etc.Wherein, the thermal conductivity of aluminium oxide lower (20-30W/mK), the price of aluminium nitride and carborundum is higher, and beryllium oxide has certain toxicity, and the thermal coefficient of expansion of ceramic material and chip material (being generally semi-conducting material) differs larger, thereby has affected to a certain extent the use of ceramic copper-clad base plate.
As a kind of semi-conducting material, the advantage such as silicon chip has technical maturity, cost is low, thermal conductivity is high (greater than 120W/mK), and thermal coefficient of expansion and chip material are suitable is suitable as the substrate material of heat-radiating substrate very much.Silicon chip surface method for metallising commonly used comprises evaporation, sputter, plating etc.But evaporation and sputtering technology are difficult to prepare the metal film (but the thickness of metal film of heat-radiating substrate is generally greater than 10 μ m) of large (greater than 1 μ m) of thickness, and cost is high; Electroplating technology prepares metal level at silicon chip surface, has problems such as wanting between sputtering seed layer, metal and silicon chip thermal stress large (owing to coefficient of thermal expansion differences is larger), is difficult to satisfy the heat-radiating substrate requirement.Fig. 1 has shown the physical property contrast of silicon chip and ceramic material commonly used.
The utility model content
For the deficiency of ceramic substrate performance and the problem of silicon chip surface metallization existence, the utility model proposes a kind of copper silicon substrate that covers, can effectively alleviate the thermal stress between metallic copper and silicon chip, improve serviceability and the reliability of covering the copper silicon substrate.
The utility model provides covers the copper silicon substrate, it is characterized in that, be provided with chips welding district copper floor and the top electrode lead district copper floor that thermocompression bonding forms at the silicon chip upper surface, be provided with heat conduction and the stress compensation copper layer that thermocompression bonding forms at the silicon chip lower surface, and bottom electrode lead district copper layer, on, bottom electrode lead-in wire copper layer is realized interconnection by the copper post in the silicon chip endoporus, chips welding district copper floor, heat conduction and stress compensation copper layer, the thickness of top electrode lead district copper layer and bottom electrode lead district copper layer equates, and all for by the copper layer that is prepared from the silicon chip surface bonding after the copper foil surface selective corrosion.
As improvement of the technical scheme, the thickness of described chips welding district copper floor, heat conduction and stress compensation copper floor, top electrode lead district copper floor and bottom electrode lead district copper floor is 10 μ m to 500 μ m.
The beneficial effects of the utility model are: by obtaining the nano porous copper layer in copper foil surface selective corrosion, and with this copper layer as the bonded layer between Copper Foil and silicon chip, obtain covering the copper silicon substrate.Because nanoscale effect can be at lower temperature (300-400 ℃) and the lower high strength bonding of realizing between Copper Foil-silicon chip of pressure (3.0-20.0MPa).And because the thermal stress between metallic copper and silicon chip can be effectively alleviated in the existence of nano-porous structure, improve serviceability and the reliability of covering the copper silicon substrate.The utility model can satisfy power device (such as great power LED, IGBT, LD etc.) package cooling demand.
Particularly, the copper silicon substrate that covers of the utility model preparation has following features:
(1) perfect heat-dissipating, adhesive strength is high between copper layer and silicon chip, thermal stress is little.Silicon chip is high thermal conducting material (the silicon chip thermal conductivity is 120-140W/mK), and the thermal conductivity of copper reaches 398W/mK.Particularly the copper layer adopts low-temperature thermocompression bonding technique to be combined with between silicon chip, and interfacial stress is little, thermal resistance is little, adhesion strength is high;
(2) thermal shock resistance is strong.The thermal coefficient of expansion (CTE) that covers the copper silicon substrate is determined by silicon chip, and the CTE of the CTE of silicon chip and power device chip (being generally semi-conducting material) is close, has avoided the high thermal stress between chip and substrate after the welded encapsulation;
(3) copper layer thickness depends on copper thickness, can (10 microns to 500 microns) select in wide range, satisfies power device package conduction, heat radiation requirement;
(4) solderability is good.Copper layer smooth surface is conducive to that power device chip mounts and routing;
(5) production cost is low, covers the copper silicon substrate and adopts Copper Foil and silicon chip thermocompression bonding preparation, and technique is simple, is fit to large-scale production, and satisfies chip on board encapsulation technology (COB) development.
Description of drawings
Fig. 1 is that the utility model covers copper silicon substrate schematic cross-section.Wherein 1 is silicon chip, and 2 is the chips welding district copper floor of silicon chip upper surface, and 3,3 ' is upper and lower contact conductor district copper floor, the heat conduction of 4 silicon chip lower surfaces and stress compensation copper layer, and 5 are the copper post that interconnects up and down.
Fig. 2 is the process chart of the utility model embodiment.
Embodiment
Below by by embodiment the utility model being described in further detail, but following examples only are illustrative, and protection range of the present utility model is not subjected to the restriction of these embodiment.
As shown in Figure 1, the copper silicon substrate that covers that the utility model provides comprises silicon chip 1, the chips welding district copper floor 2 of silicon chip upper surface, top electrode lead district copper layer 3, the heat conduction of silicon chip lower surface and stress compensation copper layer 4, bottom electrode lead district copper layer 3 ', and interconnection copper post 5.Wherein, the thickness of silicon chip upper and lower surface copper layer is identical.
Substrate of the present utility model is comprised of copper layer and the interconnection copper post of silicon chip, upper and lower surface, and the copper layer adopts the techniques such as Copper Foil plating, selective corrosion, thermocompression bonding to be produced on the silicon chip, and its preparation technology's flow process as shown in Figure 2.The below is specified for example:
1) 4 cun silicon chips (two-sided do not polish) through clean/oven dry after, adopt laser drilling, electroplate techniques such as filling out copper, in silicon chip, form the up and down copper post of interconnection, then at each sputter 20nm titanium film (Ti) of silicon chip upper and lower surface and 50nm copper film (Cu);
2) will be of a size of 100mm * 100mm, thickness is the ultrasonic cleaning 10 minutes in acetone of the electrolytic copper foil of 50 μ m, dries up to be placed on that to electroplate a layer thickness in the copper-plated zinc liquid be the copper zinc layer of 5 μ m, and deionized water (DI) washes, dries up; Then this Copper Foil being put into concentration and be 8% hydrochloric acid solution soaks, until without till the γ-ray emission, obtain the nanoporous steel structure that aperture size is about 20nm at copper foil surface, with drying up with nitrogen after the rinsed with deionized water, be stored in the nitrogen cabinet for subsequent use after taking out.
3) Copper Foil that the surface is contained the nanoporous steel structure is upside down in above-mentioned silicon chip upper and lower surface (the nano porous copper layer contacts with silicon chip surface TiCu film) of filling out behind copper, the plated film, then places together on the heating plate of hot press, closes the chamber door; Open vacuum pump and heating power supply, be evacuated down to 10
-2Pa when hot plate temperature is elevated to more than 200 ℃, applies 5MPa pressure; Continuation with hot plate temperature be elevated to 350 ℃ and be incubated 30 minutes after cooling, when hot plate temperature was lower than 100 ℃, unloading pressure obtained the copper-silicon of two-sided copper containing layer-copper base;
4) copper-silicon sample after bonding is finished takes out in the bonding chamber, adopts resist as mask, graphically corrodes the copper layer and obtains covering the copper silicon substrate.
Copper Foil can be electrolytic copper foil or rolled copper foil, and the silicon chip surface copper layer thickness depends on copper thickness, can select the conduction when encapsulating to satisfy different components and heat radiation requirement in 10um to 500um.
The above only is a kind of preferred embodiment of covering the copper silicon substrate of the present utility model, is not that the utility model technical scope is made any restriction.Copper Foil can be electrolytic copper foil or rolled copper foil as described, and its thickness is 10 μ m to 500 μ m.Every foundation technical spirit of the present utility model is made any modification or equivalent variations, modification to above-described embodiment, all belongs to the scope of the utility model technology contents.
The physical property of table 1 substrate material commonly used
Claims (3)
1. one kind covers the copper silicon substrate, it is characterized in that, be provided with chips welding district copper floor (2) and the top electrode lead district copper floor (3) that thermocompression bonding forms at silicon chip (1) upper surface, be provided with heat conduction and the stress compensation copper layer (4) that thermocompression bonding forms at silicon chip (1) lower surface, and bottom electrode lead district copper layer (3 '), on, bottom electrode lead-in wire copper layer (3,3 ') realize interconnection by the copper post (5) in silicon chip (1) endoporus, chips welding district copper floor (2), heat conduction and stress compensation copper layer (4), the thickness of top electrode lead district copper layer (3) and bottom electrode lead district copper layer (3 ') equates, and all for by the copper layer that is prepared from the silicon chip surface bonding after the copper foil surface selective corrosion.
2. the copper silicon substrate that covers according to claim 1 is characterized in that, the thickness of chips welding district copper floor (2), heat conduction and stress compensation copper floor (4), top electrode lead district copper floor (3) and bottom electrode lead district copper floor (3 ') is 10 μ m to 500 μ m.
3. the copper silicon substrate that covers according to claim 1 and 2 is characterized in that, described Copper Foil is electrolytic copper foil or rolled copper foil.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220401857 CN202736904U (en) | 2012-08-14 | 2012-08-14 | Copper pour silicon basal plate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220401857 CN202736904U (en) | 2012-08-14 | 2012-08-14 | Copper pour silicon basal plate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202736904U true CN202736904U (en) | 2013-02-13 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN 201220401857 Expired - Lifetime CN202736904U (en) | 2012-08-14 | 2012-08-14 | Copper pour silicon basal plate |
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| CN (1) | CN202736904U (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103481583A (en) * | 2013-10-09 | 2014-01-01 | 北京科技大学 | Treated copper foil with porous structure on surface and preparation method thereof |
| CN103928300A (en) * | 2014-04-14 | 2014-07-16 | 河南省科学院应用物理研究所有限公司 | Bonding method based on multi-field coupling |
| CN104362135A (en) * | 2014-11-05 | 2015-02-18 | 共青城超群科技股份有限公司 | High-heat-dissipativity organic resin copper-clad plate |
| CN106463376A (en) * | 2014-06-19 | 2017-02-22 | 汉阳大学校Erica产学协力团 | Method for peeling surface of silicon substrate |
| CN108091633A (en) * | 2017-12-13 | 2018-05-29 | 广东工业大学 | Nano porous copper interconnection layer structure and preparation method thereof |
| CN114284369A (en) * | 2021-12-29 | 2022-04-05 | 明冠新材料股份有限公司 | Hollowed-out copper foil and preparation method thereof |
-
2012
- 2012-08-14 CN CN 201220401857 patent/CN202736904U/en not_active Expired - Lifetime
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103481583A (en) * | 2013-10-09 | 2014-01-01 | 北京科技大学 | Treated copper foil with porous structure on surface and preparation method thereof |
| CN103481583B (en) * | 2013-10-09 | 2017-01-04 | 北京科技大学 | A kind of surface has the preparation method processing Copper Foil of loose structure |
| CN103928300A (en) * | 2014-04-14 | 2014-07-16 | 河南省科学院应用物理研究所有限公司 | Bonding method based on multi-field coupling |
| CN103928300B (en) * | 2014-04-14 | 2016-06-01 | 河南省科学院应用物理研究所有限公司 | A kind of bonding method based on multi-scenarios method |
| CN106463376A (en) * | 2014-06-19 | 2017-02-22 | 汉阳大学校Erica产学协力团 | Method for peeling surface of silicon substrate |
| CN106463376B (en) * | 2014-06-19 | 2019-09-27 | 汉阳大学校Erica产学协力团 | Method for peeling surface of silicon substrate |
| CN104362135A (en) * | 2014-11-05 | 2015-02-18 | 共青城超群科技股份有限公司 | High-heat-dissipativity organic resin copper-clad plate |
| CN108091633A (en) * | 2017-12-13 | 2018-05-29 | 广东工业大学 | Nano porous copper interconnection layer structure and preparation method thereof |
| CN114284369A (en) * | 2021-12-29 | 2022-04-05 | 明冠新材料股份有限公司 | Hollowed-out copper foil and preparation method thereof |
| CN114284369B (en) * | 2021-12-29 | 2023-09-01 | 明冠新材料股份有限公司 | Hollowed-out copper foil and preparation method thereof |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address | ||
| CP03 | Change of name, title or address |
Address after: 430200 Wuhan four East Lake Road Development Zone, Hubei 40 Gezhouba Dam 40 Sun City 23 building 103 room. Patentee after: WUHAN LIZHIDA TECHNOLOGY CO.,LTD. Address before: 430074 Ding Yuan Lou, international business center, Optics Valley Avenue, Wuhan, Hubei, A423 Patentee before: WUHAN LIZHIDA SCIENCE & TECHNOLOGY Co.,Ltd. |
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| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20130213 |