CN110400842A - 高压半导体装置 - Google Patents

高压半导体装置 Download PDF

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Publication number
CN110400842A
CN110400842A CN201910187396.8A CN201910187396A CN110400842A CN 110400842 A CN110400842 A CN 110400842A CN 201910187396 A CN201910187396 A CN 201910187396A CN 110400842 A CN110400842 A CN 110400842A
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trap
conduction type
isolation structure
high pressure
semiconductor device
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CN110400842B (zh
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韦维克
陈鲁夫
陈柏安
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Nuvoton Technology Corp
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Nuvoton Technology Corp
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  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)

Abstract

本发明提供了一种高压半导体装置，包含半导体衬底，具有第一导电类型，源极区和漏极区设置于半导体衬底上，其中漏极区具有与第一导电类型相反的第二导电类型，且源极区包含分别具有第一导电类型和第二导电型的两个部分，第一隔离结构和第二隔离结构分别设置于漏极区的相对两侧，其中第一隔离结构在源极区与漏极区之间，第一阱设置于第二隔离结构下且具有第一导电类型，其中第一阱的顶面邻接第二隔离结构的底面，以及第一埋层设置于半导体衬底内且具有第一导电类型，其中第一埋层与第一阱重迭。

Description

高压半导体装置
技术领域
本发明是关于半导体装置，特别是关于高压半导体装置。
背景技术
高压半导体装置技术适用于高电压与高功率的集成电路领域。传统高压半导体装置，例如垂直式扩散金属氧化物半导体(vertically diffused metal oxidesemiconductor,VDMOS)晶体管及横向扩散金属氧化物半导体(laterally diffused metaloxide semiconductor,LDMOS)晶体管，主要用于12V以上的元件应用领域。高压装置技术的优点在于符合成本效益，且易相容于其它工艺，已广泛应用于显示器驱动IC元件、电源供应器、电力管理、通信、车用电子或工业控制等领域中。
虽然现存的高压半导体装置已逐步满足它们既定的用途，但它们仍未在各方面皆彻底的符合要求。因此，关于高压半导体装置和制造技术仍有一些问题需要克服。
发明内容
本发明提供了高压半导体装置的实施例，特别是横向扩散金属氧化物半导体(LDMOS)晶体管的实施例。通常藉由在工艺中调整横向扩散金属氧化物半导体的阱的掺杂浓度，使得横向扩散金属氧化物半导体产生特定的击穿电压，以符合不同产品应用的需求。然而，在实际的工艺，例如整合式的双载子-互补式金属氧化物半导体-扩散金属氧化物半导体(bipolar-CMOS-DMOS，BCD)的工艺中，调整阱的掺杂浓度将会需要在工艺中添加额外的掩膜，使得整体的工艺成本也跟着提高。
为了提高横向扩散金属氧化物半导体晶体管的击穿电压，本发明的一些实施例在横向扩散金属氧化物半导体晶体管中，在漏极区相对于源极区的另一侧设置具有与漏极区相反导电类型的第一阱和第一埋层，第一阱和第一埋层相连形成L形的结构，且L形的水平部分是朝向源极区的方向延伸。藉由L形结构的设置，当对横向扩散金属氧化物半导体晶体管的漏极端施加反向电压时，可增加耗尽区的大小，进而提升装置的击穿电压。拥有高击穿电压的横向扩散金属氧化物半导体晶体管可被广泛地应用于电平移位器(level shifter)及高压集成电路(high voltage integrated circuit，HVIC)芯片中。
根据一些实施例，提供高压半导体装置。高压半导体装置包含半导体衬底，具有第一导电类型，以及源极区和漏极区设置于半导体衬底上，其中漏极区具有与第一导电类型相反的第二导电类型，且源极区包含分别具有第一导电类型和第二导电型的两个部分。高压半导体装置也包含第一隔离结构和第二隔离结构，分别设置于漏极区的相对两侧，以及第一阱设置于第二隔离结构下且具有第一导电类型，其中第一阱的顶面邻接第二隔离结构的底面。半导体装置更包含第一埋层，设置于半导体衬底内且具有第一导电类型，其中第一埋层与第一阱重迭。
根据一些实施例，提供高压半导体装置。高压半导体装置包含半导体衬底，具有第一导电类型，以及外延层设置于半导体衬底上。高压半导体装置也包含源极区和第一漏极区设置于外延层内，其中第一漏极区具有与第一导电类型相反的第二导电类型，且源极区包含分别具有第一导电类型和第二导电型的两个部分，以及第一隔离结构和第二隔离结构设置于外延层上，其中第一漏极区位于第一隔离结构与第二隔离结构之间，且第一隔离结构在源极区与第一漏极区之间。高压半导体装置更包含第一阱，设置于外延层内和第二隔离结构下，其中第一阱具有第一导电类型且由第二隔离结构完全覆盖，以及第一埋层设置于第一阱下且具有第一导电类型，其中第一埋层接触第一阱，且第一埋层延伸至第一漏极区的正下方。
本发明的半导体装置可应用于多种类型的半导体装置，为让本发明的特征和优点能更明显易懂，下文特举出应用于横向扩散金属氧化物半导体晶体管的实施例，并配合所附图式，作详细说明如下。
附图说明
藉由以下的详述配合所附图式，我们能更加理解本发明实施例的观点。值得注意的是，根据工业上的标准惯例，一些部件(feature)可能没有按照比例绘制。事实上，为了能清楚地讨论，不同部件的尺寸可能被增加或减少。
图1是根据本发明的一些实施例，显示高压半导体装置的剖面示意图；
图2是根据本发明的一些实施例，显示高压半导体装置的剖面示意图；
图3是根据本发明的一些实施例，显示高压半导体装置的剖面示意图；以及
图4是根据本发明的一些实施例，显示高压半导体装置的剖面示意图。
附图标号：
100、200、300、400：高压半导体装置；
101：半导体衬底；
103、103’：第二埋层；
105、205、305：第一埋层；
107：外延层；
109、109’、111、111’、113、113’、115、115’：高压阱；
117、123、123’、125、125’：阱；
119a、119a’、119b、119b’、119c、119c’、119d：隔离结构；
121、121’：栅极结构；
127、127’、129、129’、131、131’、133、133’：掺杂区；
135：介电层；
137a、137a’、137b、137b’、137c、137c’、137d、137d’：导孔；
139、139’：衬底电极；
141、141’：源极电极；
143：漏极电极；
305a、305b、305c、305d：区段；
306a、306b：连接部；
L1、L2、L3、L4：长度；
D1、D2：距离。
具体实施方式
以下揭露提供了很多不同的实施例或范例，用于实施所提供的高压半导体装置的不同元件。各元件和其配置的具体范例描述如下，以简化本发明实施例。当然，这些仅仅是范例，并非用以限定本发明。举例而言，叙述中若提及第一元件形成在第二元件之上，可能包含第一和第二元件直接接触的实施例，也可能包含额外的元件形成在第一和第二元件之间，使得它们不直接接触的实施例。此外，本发明实施例可能在不同的范例中重复参考数字及/或字母。如此重复是为了简明和清楚，而非用以表示所讨论的不同实施例及/或形态之间的关系。
以下描述实施例的一些变化。在不同图式和说明的实施例中，相似的参考数字被用来标明相似的元件。可以理解的是，在方法的前、中、后可以提供额外的操作，且一些叙述的操作可为了该方法的其他实施例被取代或删除。
图1是根据本发明的一些实施例，显示高压半导体装置100的剖面示意图。高压半导体装置100包含半导体衬底101。半导体衬底101可由硅或其他半导体材料制成，或者，半导体衬底101可包含其他元素半导体材料，例如锗(Ge)。一些实施例中，半导体衬底101由化合物半导体制成，例如碳化硅、氮化镓、砷化镓、砷化铟或磷化铟。一些实施例中，半导体衬底101由合金半导体制成，例如硅锗、碳化硅锗、磷化砷镓或磷化铟镓。
此外，半导体衬底101可包含绝缘层上覆硅(silicon-on-insulator，SOI)衬底。一些实施例中，半导体衬底101可为轻掺杂的P型或N型衬底。在本实施例中，半导体衬底101为P型，其内部具有P型掺质(例如硼(B))，且后续于半导体衬底101上形成的高压半导体装置100可包含N型的横向扩散金属氧化物半导体晶体管。
高压半导体装置100可包含设置于半导体衬底101上的外延层107。一些实施例中，外延层107可为N型或P型。外延层107可藉由金属有机物化学气相沉积法(metal organicchemical vapor deposition，MOCVD)、等离子体增强化学气相沉积法(plasma-enhancedCVD，PECVD)、分子束外延法(molecular beam epitaxy，MBE)、氢化物气相外延法(hydridevapour phase epitaxy，HVPE)、液相外延法(liquid phase epitaxy，LPE)、氯化物气相外延法(chloride-vapor phase epitaxy，Cl-VPE)、其他相似的工艺方法或前述的组合以形成。在其他实施例中，高压半导体装置100可不包含外延层107，后续形成于外延层107内的高压阱、阱、掺杂区可直接形成于半导体衬底101内(即靠近半导体衬底101的顶面的位置)。
此外，如图1所示，高压半导体装置100包含设置在半导体衬底101内和外延层107内的第一埋层105和第二埋层103。第一埋层105和第二埋层103具有相反的导电类型，在本实施例中，第一埋层105为P型，且第二埋层103为N型。此外，第一埋层105和第二埋层103的掺杂浓度在约1x1016原子/cm3至约1x1019原子/cm3的范围内。
第一埋层105和第二埋层103的形成方法包含在形成外延层107之前，在半导体衬底101内离子注入P型掺质(例如硼(B))或N型掺质(例如磷(P)或砷(As))，实施热处理将注入的离子驱入(drive in)半导体衬底101内，然后在半导体衬底101上形成外延层107。一些实施例中，由于外延层107是在高温的条件下形成，故注入的离子会扩散进入外延层107内，如图1所示，第一埋层105和第二埋层103位于半导体衬底101和外延层107的界面附近，且分别具有一部分在半导体衬底101内，以及另一部分在外延层107内。
接续前述，高压半导体装置100包含位于外延层107内的阱117(又称为第一阱)、高压阱115(又称为第一高压阱)、高压阱113(又称为第二高压阱)、高压阱111和高压阱109(又称为第三高压阱)。高压阱109、高压阱113和阱117具有相同于第一埋层105的导电类型，而高压阱111和高压阱115具有相同于第二埋层103的导电类型。在本实施例中，高压阱109和113以及阱117为P型，而高压阱111和115为N型。
此外，高压阱109、111、113和115以及阱117的形成方法包含离子注入工艺和热驱入(drive in)工艺。一些实施例中，阱117的掺杂浓度大于或等于高压阱109、111、113和115。举例而言，高压阱109、111、113和115的掺杂浓度在约1x1015原子/cm3至约5x1017原子/cm3的范围内，且阱117的掺杂浓度在约5x1015原子/cm3至约1x1018原子/cm3的范围内。
在形成高压阱109、111、113和115以及阱117之后，在高压阱115内形成阱125(又称为第二阱或漂移(drift)区)，且在高压阱113内形成阱123(又称为第三阱或基体(body)区)。阱123和125具有相反的导电类型。明确而言，阱123具有相同于高压阱113的导电类型，而阱125具有相同于高压阱115的导电类型。在本实施例中，阱123为P型，且阱125为N型。用于形成阱123和125的工艺相同或相似于阱117的工艺，在此便不重复叙述。一些实施例中，阱123和125的掺杂浓度大于阱117的掺杂浓度，在约5x1016原子/cm3至约5x1018原子/cm3的范围内。
根据一些实施例，如图1所示，高压半导体装置100包含设置于外延层107上的隔离结构119a、隔离结构119b(又称为第三隔离结构)、隔离结构119c(又称为第一隔离结构)和隔离结构119d(又称为第二隔离结构)。明确而言，隔离结构119a、119b、119c和119d的一部分是嵌入外延层107内。一些实施例中，隔离结构119a、119b、119c和119d由氧化硅制成，且为藉由热氧化法所形成的硅局部氧化(local oxidation of silicon，LOCOS)隔离结构。在其他实施例中，隔离结构119a、119b、119c和119d可以是藉由刻蚀和沉积工艺所形成的浅沟道隔离(shallow trench isolation，STI)结构。
一些实施例中，在形成隔离结构119a、119b、119c和119d之后，在外延层107上形成栅极结构121。如图1所示，栅极结构121自阱123延伸至隔离结构119c上，且栅极结构121覆盖阱123的一部分、高压阱113的一部分和高压阱115的一部分。
栅极结构121包含栅极介电层(未绘示)以及设置于其上的栅极电极(未绘示)。可先依序毯覆性沉积介电材料层(用以形成栅极介电层)及位于其上的导电材料层(用以形成栅极电极)于外延层107上，再藉由光刻工艺与刻蚀工艺将介电材料层及导电材料层分别图案化以形成包含栅极介电层及栅极电极的栅极结构121。
上述介电材料层的材料(即栅极介电层的材料)可包含氧化硅、氮化硅、氮氧化硅、高介电常数(high-k)的介电材料、前述的组合或其它合适的介电材料。一些实施例中，介电材料层可藉由化学气相沉积法(chemical vapor deposition，CVD)或旋转涂布(spincoating)以形成。上述导电材料层的材料(即栅极电极的材料)可为非晶硅、多晶硅、一或多种金属、金属氮化物、导电金属氧化物、前述的组合或其他合适的导电材料。导电材料层的材料可藉由化学气相沉积法(CVD)、溅射(sputtering)、电阻加热蒸镀法、电子束蒸镀法、或其它合适的沉积方式形成。另外，栅极结构121可包含设置于栅极结构121的两侧侧壁上的绝缘间隙物(未绘示)。
如图1所示，高压半导体装置100包含掺杂区127、掺杂区129、掺杂区131和掺杂区133。掺杂区127位于隔离结构119a与隔离结构119b之间。掺杂区129邻接于掺杂区131，且掺杂区129和131位于隔离结构119b与栅极结构121之间。掺杂区133位于隔离结构119c与隔离结构119d之间。一些实施例中，在形成栅极结构121之后，形成掺杂区127、129、131和133。
在本实施例中，掺杂区127和129为P型，且掺杂区131和133为N型。掺杂区127、129、131和133的掺杂浓度高于阱117、123和125的掺杂浓度，一些实施例中，掺杂区127、129、131和133的掺杂浓度在约1x1019原子/cm3至约5x1020原子/cm3的范围内。值得注意的是，掺杂区129和131可作为高压半导体装置100的源极区，且掺杂区133可作为高压半导体装置100的漏极区。
接续前述，高压半导体装置100包含设置于外延层107上的介电层135。介电层135包含由多个介电材料所形成的多层结构，如氧化硅、氮化硅、氮氧化硅、磷硅酸盐玻璃(phosphosilicate glass,PSG)、硼磷硅玻璃(borophosphosilicate glass,BPSG)、低介电常数(low-k)介电材料或其他合适的介电材料。
再者，如图1所示，高压半导体装置100包含设置于外延层107上和介电层135内的导孔(hole)137a、137b、137c和137d。此外，高压半导体装置100也包含设置于导孔137a上的衬底电极139，设置于导孔137b和137c上的源极电极141，以及设置于导孔137d上的漏极电极143。一些实施例中，导孔137a、137b、137c、137d、衬底电极139、源极电极141以及漏极电极143的材料可包含铝(Al)、铜(Cu)、钨(W)、钛(Ti)、钽(Ta)、氮化钛(TiN)、氮化钽(TaN)、硅化镍(NiSi)、硅化钴(CoSi)、碳化钽(TaC)、硅氮化钽(TaSiN)、碳氮化钽(TaCN)、铝化钛(TiAl)，铝氮化钛(TiAlN)、前述的组合或其他合适的导电材料。
明确而言，衬底电极139藉由导孔137a与掺杂区127电连接，源极电极141藉由导孔137b和137c与掺杂区129和131(即源极区)电连接，漏极电极143藉由导孔137d与掺杂区133(即漏极区)电连接。
根据一些实施例，如图1所示，在形成衬底电极139、源极电极141和漏极电极143之后，完成高压半导体装置100。一些实施例中，第一埋层105的长度L1在约4μm至约30μm的范围内，第一阱117的长度L2在约3μm至约15μm的范围内，且第一阱117与阱125之间的距离D1在约2μm至约20μm的范围内。
一些实施例中，第一阱117的顶面邻接隔离结构119d的底面。一些实施例中，第一阱117由隔离结构119d所完全覆盖。换言之，第一阱117在半导体衬底101的顶面上的投影范围在隔离结构119d在半导体衬底101的顶面上的投影范围内。再者，第一埋层105与第一阱117重迭。一些实施例中，如图1所示，第一埋层105接触第一阱117且延伸至漏极区133、阱125和隔离结构119c的正下方。在其他实施例中，第一埋层105可不延伸至隔离结构119c的正下方，或者，第一埋层105可不延伸至漏极区133的正下方。
为了提高高压半导体装置100的击穿电压，本发明的一些实施例藉由在漏极区133相对于源极区129和131的另一侧设置具有与漏极区133相反导电类型的第一阱117和第一埋层105，第一阱117和第一埋层105相连形成L形的结构，且L形的水平部分是朝向源极区129和131的方向延伸。藉由L形结构的设置，当对横向扩散金属氧化物半导体晶体管的漏极端施加反向电压时，可增加耗尽区的大小，进而提升装置的击穿电压。拥有高击穿电压的横向扩散金属氧化物半导体晶体管可被广泛地应用于电平移位器(level shifter)及高压集成电路(high voltage integrated circuit，HVIC)芯片中。
图2是根据本发明的一些实施例，显示高压半导体装置200的剖面示意图。高压半导体装置200与高压半导体装置100的差异在于第一埋层205的形状，高压半导体装置200的其他元件的工艺和材料相同或相似于高压半导体装置100，在此便不重复叙述。如图2所示，高压半导体装置200的第一埋层205的厚度可沿着隔离结构119d往隔离结构119c的方向递增。
图3是根据本发明的一些实施例，显示高压半导体装置300的剖面示意图。高压半导体装置300与高压半导体装置100的差异在于第一埋层305的形状，高压半导体装置300的其他元件的工艺和材料相同或相似于高压半导体装置100，在此便不重复叙述。
如图3所示，高压半导体装置300的第一埋层305可包含多个区段，例如区段305a、305b、305c和305d，且区段305a、305b、305c和305d之间藉由连接部306a、306b彼此连接。一些实施例中，第一埋层305的形成方法包含藉由图案化的光刻胶实施离子刻蚀工艺，以在半导体衬底101内形成多个不连续的掺杂区段(未绘示)，然后，实施热处理(即驱入)工艺使得掺杂区段内的离子向外扩散以彼此连接。
如图3所示，区段305a藉由连接部306a与区段305b连接，区段305c藉由连接部306b与区段305d连接。在其他实施例中，区段305a、305b、305c和305d可藉由连接部完全连接，彼此之间不分离。值得注意的是，藉由形成多个不连续的掺杂区段以形成第一埋层305的方法可调整各个掺杂区段的掺杂浓度，使得形成的高压半导体装置300的特性可由工艺上进行更深入地调控，第一埋层305耗尽的情况会有所不同，藉此调整元件可承受的击穿电压。
图4是根据本发明的一些实施例，显示高压半导体装置400的剖面示意图。高压半导体装置400在图4的剖面中以第一埋层105和第一阱117的中心线为对称轴具有两侧对称的形状。换言之，高压半导体装置400的左半侧即为高压半导体装置100，且其右半侧即为高压半导体装置100的镜像。
值得注意的是，高压半导体装置400为以漏极电极143为中心的结构，由左至右依序为衬底电极139、源极电极141、漏极电极143、源极电极141’和衬底电极139’。隔离结构119d两侧的漏极区133和133’分别藉由导孔137d和137d’电连接于漏极电极143。
相似于高压半导体装置400的左侧结构，高压半导体装置400的右侧结构包含导孔137c’、137b’和137a’、隔离结构119c’、119b’和119a’、栅极结构121’、掺杂区131’和129’(又称为源极区)、掺杂区127’、阱125’和123’、高压阱115’、113’、111’和109’，以及第一埋层103’。上述高压半导体装置400的元件的工艺和材料相同或相似于高压半导体装置100，在此便不重复叙述。
根据一些实施例，如图4所示，第一埋层105的长度L3在约10μm至约60μm的范围内，第一阱117的长度L4在约6μm至约30μm的范围内。此外，相似于图1的高压半导体装置100，高压半导体装置400的第一阱117与阱125之间的距离D1在约2μm至约20μm的范围内，而第一阱117与另一侧的阱125’之间的距离D2也在约2μm至约20μm的范围内。
以上概述数个实施例，以便在本发明所属技术领域的技术人员可以更理解本发明实施例的观点。在本发明所属技术领域的技术人员应该理解，他们能以本发明实施例为基础，设计或修改其他工艺和结构，以达到与在此介绍的实施例相同的目的及/或优势。在本发明所属技术领域的技术人员也应该理解到，此类等效的工艺和结构并无悖离本发明的精神与范围，且他们能在不违背本发明的精神和范围之下，做各式各样的改变、取代和替换。

Claims (10)

1.一种高压半导体装置，其特征在于，包括：
一半导体衬底，具有一第一导电类型；
一源极区和一漏极区，设置于该半导体衬底上，其中该漏极区具有与该第一导电类型相反的一第二导电类型，且该源极区包括分别具有该第一导电类型和该第二导电型的两个部分；
一第一隔离结构和一第二隔离结构，分别设置于该漏极区的相对两侧，其中该第一隔离结构在该源极区与该漏极区之间；
一第一阱，设置于该第二隔离结构下且具有该第一导电类型，其中该第一阱的顶面邻接该第二隔离结构的底面；以及
一第一埋层，设置于该半导体衬底内且具有该第一导电类型，其中该第一埋层与该第一阱重迭。
2.如权利要求1所述的高压半导体装置，其特征在于，该第一埋层的长度大于该第一阱的长度和该第二隔离结构的长度。
3.如权利要求1所述的高压半导体装置，其特征在于，更包括：
一第一高压阱，设置于该第一埋层上且具有该第二导电类型，其中该第一高压阱邻接该第一阱和该第一埋层；以及
一第二阱，设置于该第一高压阱内且具有该第二导电类型，其中该第二阱位于该第一隔离结构与该第二隔离结构之间，且该漏极区位于该第二阱内。
4.如权利要求3所述的高压半导体装置，其特征在于，更包括：
一第二高压阱，邻接该第一高压阱且具有该第一导电类型；
一第二埋层，设置于该半导体衬底内且具有该第二导电类型，其中该第二埋层位于该第二高压阱下；
一第三阱，设置于该第二高压阱内且具有该第一导电类型，其中该源极区位于该第三阱内；以及
一栅极结构，设置于该半导体衬底上且自该第三阱延伸至该第一隔离结构上。
5.如权利要求1所述的高压半导体装置，其特征在于，更包括：
一第三隔离结构，设置于该半导体衬底上，其中该源极区位于该第一隔离结构和该第三隔离结构之间；以及
一第三高压阱和一掺杂区，设置于该半导体衬底上且具有该第一导电类型，其中该掺杂区位于该第三高压阱内，该第三隔离结构位于该掺杂区与该源极区之间，且该掺杂区与该半导体衬底电连接。
6.一种高压半导体装置，其特征在于，包括：
一半导体衬底，具有一第一导电类型；
一外延层，设置于该半导体衬底上；
一源极区和一第一漏极区，设置于该外延层内，其中该第一漏极区具有与该第一导电类型相反的一第二导电类型，且该源极区包括分别具有该第一导电类型和该第二导电型的两个部分；
一第一隔离结构和一第二隔离结构，设置于该外延层上，其中该第一漏极区位于该第一隔离结构与该第二隔离结构之间，且该第一隔离结构在该源极区与该第一漏极区之间；
一第一阱，设置于该外延层内和该第二隔离结构下，其中该第一阱具有该第一导电类型且由该第二隔离结构完全覆盖；以及
一第一埋层，设置于该第一阱下且具有该第一导电类型，其中该第一埋层接触该第一阱，且该第一埋层延伸至该第一漏极区的正下方。
7.如权利要求6所述的高压半导体装置，其特征在于，更包括：
一第一高压阱、一第二高压阱和一第三高压阱设置于该外延层内，其中该第二高压阱位于该第一高压阱和该第三高压阱之间，该第一漏极区设置于该第一高压阱内，该源极区设置于该第二高压阱内，且该第一高压阱具有该第二导电类型，该第二高压阱和该第三高压阱具有该第一导电类型；以及
一掺杂区，设置于该第三高压阱内且具有该第一导电类型，其中该掺杂区与该半导体衬底电连接。
8.如权利要求6所述的高压半导体装置，其特征在于，该第一埋层的厚度沿着该第二隔离结构往该第一隔离结构的方向递增。
9.如权利要求6所述的高压半导体装置，其特征在于，该第一埋层包括多个区段，所述多个区段藉由一连接部相连，且该连接部的厚度小于所述多个区段的厚度。
10.如权利要求6所述的高压半导体装置，其特征在于，更包括：
一第二漏极区，设置于该外延层内且具有该第二导电类型，其中该第一阱和该第二隔离结构位于该第一漏极区与该第二漏极区之间，且该第一埋层延伸至该第二漏极区的正下方。
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