CN110391223B - ESD protection circuit in flyback primary side feedback switch power supply control chip - Google Patents
ESD protection circuit in flyback primary side feedback switch power supply control chip Download PDFInfo
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- CN110391223B CN110391223B CN201910687578.1A CN201910687578A CN110391223B CN 110391223 B CN110391223 B CN 110391223B CN 201910687578 A CN201910687578 A CN 201910687578A CN 110391223 B CN110391223 B CN 110391223B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
- H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
Abstract
The invention discloses an ESD protection circuit in a flyback primary side feedback switch power supply control chip, which is arranged at an FB end of the chip and comprises a semiconductor P-type substrate, a BN buried layer diffused in the P substrate, a P well and an N well formed on the upper surface of the BN buried layer, a high-concentration P-type doped P + injection region and a high-concentration N-type doped N + injection region. The ESD protection circuit can clamp the negative voltage to a voltage Vss-VBEThe low-voltage device of the internal circuit is protected, and meanwhile, the ESD protection circuit can resist high voltage and has the highest withstand voltage of 48V.
Description
Technical Field
The invention relates to a flyback primary side feedback AC-DC switching power supply, in particular to an ESD protection circuit in a control chip of a reverse-payment type primary side feedback switching power supply, and belongs to the technical field of semiconductor integrated circuits.
Background
The flyback primary side feedback AC-DC switching power supply can convert a high-voltage alternating current signal into a low-voltage direct current signal, and is widely applied to the fields of chargers, adapters, LED driving and the like due to the advantages of few peripheral system devices, low cost, simple structure and the like. As shown in fig. 1, the primary side modulation technique does not require a secondary optocoupler and a secondary control circuit, but uses an auxiliary winding NA to accurately reflect the output voltage condition through mutual inductance. The control circuit of the flyback primary side feedback AC-DC switching power supply comprises a sample-and-hold circuit, an error amplifier, a comparator, a PFM modulator and a driving circuit, and is integrated in a control chip. The feedback sampling signal is connected with the input end of a sampling and holding circuit (namely the FB end of a chip) through a voltage dividing resistor of an auxiliary winding NA, the output of the sampling and holding circuit and a reference voltage VREF1 are connected with one input end of a PFM modulator after passing through an error amplifier, the sampling signal obtained through a sampling resistor of a primary winding NP and a reference voltage VREF1 are connected with the other input end of the PFM modulator after passing through a comparator COMP, and the output of the PFM modulator controls a power tube MOS1 of a switching power supply through a driving circuit. When the power tube MOS1 is turned on, a high-voltage signal loads two ends of a primary winding NP of a transformer, the voltage polarity of an auxiliary winding NA is opposite, high negative voltage with equal proportion appears, the high negative voltage enters a chip internal circuit from a chip pin FB end, and low-voltage devices of the internal circuit can be damaged if the high negative voltage is not controlled.
An ESD protection circuit is designed on an FB pin inside a primary side feedback switch power supply control chip, and when an ESD phenomenon occurs, the ESD protection circuit can convert high-voltage static electricity into transient low-voltage large current and discharge the current, so that the aim of protecting an integrated circuit inside the chip is fulfilled. As shown in fig. 2, if a common ESD circuit is used, the circuit has a parasitic transistor Q1 formed by a diode of the ESD protection circuit and an N + injection region of a MOS2 transistor in the sample-and-hold circuit inside the chip, when a pin FB is a high negative voltage (less than-0.7V), the BE junction of Q1 is turned on in the forward direction, and further the CE junction of the parasitic transistor Q1 is turned on, so that the voltage value of the drain D of the MOS2 transistor is equal to the negative voltage value of the pin FB, an erroneous circuit signal is generated, which seriously affects the normal operation of the circuit, and even damages the MOS2 transistor.
Disclosure of Invention
The invention provides an ESD protection circuit in a reverse-payment type primary side feedback switch power supply control chip, which has an isolation ring protection structure and can effectively avoid the problem of parasitic triode switching-on when negative voltage exists. The ESD protection circuit can clamp the negative voltage to a voltage Vss-VBEProtecting the low-voltage device of the internal circuit of the chip; meanwhile, the ESD protection circuit can resist high voltage with the maximum withstand voltage of 48V.
In order to achieve the purpose, the invention adopts the following technical scheme: an ESD protection circuit in a flyback primary side feedback switch power supply control chip is characterized in that a sampling and holding circuit, an error amplifier, a comparator, a PFM modulator, a driving circuit and an ESD protection circuit are integrated in the control chip, an output sampling signal is connected with the input end of the sampling and holding circuit, namely an FB port of the control chip, through a divider resistor of an auxiliary winding NA, the output of the sampling and holding circuit and a reference voltage VREF1 are connected with one input end of the PFM modulator after passing through the error amplifier, a sampling signal obtained through a CS port of the control chip, namely a peak current sampling resistor of a primary side winding NP and a reference voltage VREF1 are connected with the other input end of the PFM modulator after passing through a comparator COMP, a GATE port of the control chip, namely the output of the PFM modulator is connected with a power tube MOS1 of the switch power supply through the driving circuit, and the ESD protection circuit is arranged at the FB port of the control chip;
the method is characterized in that: the ESD protection circuit comprises a semiconductor P-type substrate, a first buried layer BN1, a second buried layer BN2, a first N well NW1, a second N well NW2, a first P well PW1, a second P well PW2, a first high-concentration N-type doped N + injection region, a second high-concentration N-type doped N + injection region, a third high-concentration N-type doped N + injection region, a first high-concentration P-type doped P + injection region, a second high-concentration P-type doped P + injection region and a third high-concentration P-type doped P + injection region; wherein:
the first buried layer BN1 is diffused in the P-type substrate, the first N well NW1 is generated on the upper surface of the first buried layer BN1 and distributed annularly, the first P well PW1 is generated on the upper surface of the first buried layer BN1 and located in the annular first N well NW1, the first high-concentration N-type doped N + injection region is annularly arranged on the upper portion of the first N well NW1, the first high-concentration P-type doped P + injection region is annularly arranged on the upper portion of the first P well PW1, the second high-concentration N-type doped N + injection region is arranged on the upper portion of the first P well PW1 and located in the annular center of the first high-concentration P-type doped P + injection region, and the first high-concentration N-type doped N + injection region and the first high-concentration P-type doped P + injection region are both connected with a ground wire V of a control chipSSThe second high-concentration N-type doped N + injection region is connected with the FB end of the control chip, the second high-concentration N-type doped N + injection region and the first P well PW1 form a first diode D1, the first high-concentration P-type doped P + injection region serves as the anode of a diode D1, and the second high-concentration N-type doped N + injection region serves as the cathode of a diode D1;
a second buried layer BN2 is diffused in the P-type substrate and is isolated from the first buried layer BN1, a second N well NW2 is generated on the upper surface of the second buried layer BN2 and is distributed in a ring shape, a second P well PW2 is generated on the upper surface of the second buried layer BN2 and is positioned in a ring-shaped second N well NW2, a third high-concentration N-type doped N + injection region is annularly arranged on the upper part of the second N well NW2, a second high-concentration P-type doped P + injection region is arranged on the upper part of the second P well PW2 and is positioned in the center of the ring shape of the third high-concentration N-type doped N + injection region, the third high-concentration N-type doped N + injection region is connected with a control chip power supply Vdd, the second high-concentration P-type doped P + injection region is connected with the FB end of the control chip, the second N well NW2 and the second P well PW2 form a second diode D2, the second high-concentration P-type doped P + injection region serves as an anode of the diode D2, and the third high-concentration N + injection region serves as a cathode 2 of the diode D2;
a third high concentration P + implantation region disposed on the P-type substrate and between the first N well NW1 and the second N well NW2, serving as ohmic contact of the P-type substrate and connected to the ground line V of the control chipSS。
The first diode structure and the second diode structure are diodes formed by PN junctions or diode structures formed by MOS tubes.
The substrate is doped in a P type, and an isolation ring formed by a BN1 buried layer arranged on the P type substrate and an N well NW1 is doped in an N type; the isolating ring is one of a circular ring, a square ring or a rectangular ring.
The invention has the advantages and obvious effects that:
(1) the ESD protection circuit has an isolation ring protection structure, the BN1 buried layer and the N trap NW1 form an isolation ring, the diode D1 in the isolation ring is isolated from other device structures, parasitic triodes are avoided, and the problems that the parasitic triodes are generated and the parasitic triodes are turned on when negative voltage works are effectively avoided.
(2) The ESD protection circuit can clamp the negative voltage to the voltage Vss-VBEAnd low-voltage devices of the internal circuit of the chip are protected.
(3) The ESD protection circuit can resist high voltage, and the maximum withstand voltage is 48V.
Drawings
FIG. 1 is an application diagram of a flyback primary-side feedback AC-DC switching power supply system in the prior art;
FIG. 2 is a cross-sectional view of a prior art ESD protection circuit;
FIG. 3 is a cross-sectional view of a process structure of the ESD protection circuit of the present invention;
fig. 4 is an equivalent circuit diagram of the ESD protection circuit of the present invention.
Detailed Description
Referring to fig. 3, the ESD protection circuit operating on a negative voltage according to the present invention includes a semiconductor P-type substrate, a BN buried layer diffused inside the P-type substrate, a P-well and an N-well formed on an upper surface of the BN buried layer, a high concentration P-type doped P + implantation region and a high concentration N-type doped N + implantation region.
The buried layer BN1 is generated in the P-sub of the P substrate through diffusion, the N well NW1 is generated on the upper surface of the buried layer BN1 and distributed in a ring shape, the P well PW1 is generated on the surface of the buried layer BN1 and in the ring-shaped N well NW1, and the high-concentration P-type doped P + injection region is arranged on the P substrate and used as ohmic contact of the P substrate and used for grounding Vss of a lead of the P substrate. The high-concentration N-type doped N + injection region is arranged in the N well NW1 and is used as ohmic contact of an N well NW1 and used for grounding Vss of a lead of the N well, and the BN1 buried layer and the N well NW1 form an isolation ring to isolate the internal diode D1 from other device structures, so that parasitic triodes are avoided. The high-concentration P-type doped P + injection region is arranged on the upper part of a P well PW1, the high-concentration N-type doped N + injection region is arranged on the upper part of a P well PW1, the high-concentration N-type doped N + injection region and the P well PW1 form a diode structure D1, the high-concentration N-type doped N + injection region and the high-concentration P + injection region which are arranged on the NW1 are connected with the anode of the diode D1 through metal wires and connected with the ground wire Vss of a chip, and the high-concentration N + injection region which is arranged on the PW1 is used as the cathode of the diode D1 and connected with the FB end of a chip input pin through the metal wires.
The buried layer BN2 is generated in a P substrate through diffusion, an N well NW2 is generated on the upper surface of the buried layer BN2 and distributed annularly, a P well PW2 is generated on the surface of the BN2 and in the annular N well NW2, a high-concentration N-type doped N + injection region is arranged on the N well NW2, a high-concentration P-type doped P + injection region is arranged on the upper portion of the P well PW2, the N well NW2 and the P well PW2 form a diode structure D2, the high-concentration N-type doped N + injection region arranged on the NW2 forms a cathode of the diode D2 and is connected with a power supply Vdd of a chip through a metal wire, and the high-concentration P-type doped P + injection region arranged on the PW2 serves as an anode of the diode D2 and is connected with an input terminal FB of the chip through the metal wire.
In fig. 4, diodes D1 and D2 form an ESD protection circuit that operates with a negative voltage of a switching power supply, a buried layer BN1 and an N well NW1 form an N-type isolation ring as a dotted line around D1, and a high-concentration N-type doped N + implantation region provided in the isolation ring is connected to each other through a metal lineThe chip ground line Vss is connected to the anode of the diode D1, the P substrate is also connected to the ground line Vss, and the cathode of the diode D1 is connected to the terminal FB of the input terminal of the circuit. When the FB end of the circuit has negative voltage, the diode D1 is conducted in the forward direction, and the diode is isolated from the external circuit by the grounded isolation ring, so that the generation of parasitic devices is avoided; the anode of the forward conducting diode D1 is grounded to Vss, and the FB pin voltage can be clamped at Vss-V by combining the current limiting effect of an external resistorBEIn which V isBEThe forward conduction voltage drop of the diode D1 avoids the high negative voltage value of the FB pin, and protects the low-voltage device of the internal circuit. The N well NW2 and the P well PW2 form a diode D2, the anode of the D2 is connected with the FB end of the circuit, the cathode of the D2 is connected with a chip power supply Vdd, and the reverse withstand voltage of the diode D2 can reach 48V due to the low doping concentrations of the N well NW2 and the P well PW 2.
Claims (3)
1. An ESD protection circuit in a flyback primary feedback switch power supply control chip is characterized in that a sampling and holding circuit, an error amplifier, a comparator, a PFM modulator, a driving circuit and an ESD protection circuit are integrated in the control chip, an output sampling signal is connected with the input end of the sampling and holding circuit, namely an FB port of the control chip, through a divider resistor of an auxiliary winding NA, the output of the sampling and holding circuit and a reference voltage VREF1 are connected with one input end of the PFM modulator after passing through the error amplifier, the connection end of a source electrode of a power tube MOS1 of the switch power supply and a peak current sampling resistor is connected with the positive end of a comparator COMP through a current detection port CS of the control chip, the negative end of the comparator COMP is connected with a reference voltage VREF2, the output of the comparator COMP is connected with the other input end of the PFM modulator, the output of the PFM modulator is connected with the grid electrode of the power tube MOS1 through a power tube driving port GATE of the control chip after passing through the driving circuit, the ESD protection circuit is arranged at the FB port of the control chip;
the method is characterized in that: the ESD protection circuit comprises a semiconductor P-type substrate, a first buried layer BN1, a second buried layer BN2, a first N well NW1, a second N well NW2, a first P well PW1, a second P well PW2, a first high-concentration N-type doped N + injection region, a second high-concentration N-type doped N + injection region, a third high-concentration N-type doped N + injection region, a first high-concentration P-type doped P + injection region, a second high-concentration P-type doped P + injection region and a third high-concentration P-type doped P + injection region; wherein:
the first buried layer BN1 is diffused in the P-type substrate, the first N well NW1 is generated on the upper surface of the first buried layer BN1 and distributed annularly, the first P well PW1 is generated on the upper surface of the first buried layer BN1 and located in the annular first N well NW1, the first high-concentration N-type doped N + injection region is annularly arranged on the upper portion of the first N well NW1, the first high-concentration P-type doped P + injection region is annularly arranged on the upper portion of the first P well PW1, the second high-concentration N-type doped N + injection region is arranged on the upper portion of the first P well PW1 and located in the annular center of the first high-concentration P-type doped P + injection region, and the first high-concentration N-type doped N + injection region and the first high-concentration P-type doped P + injection region are both connected with a ground wire V of a control chipSSThe second high-concentration N-type doped N + injection region is connected with the FB end of the control chip, the second high-concentration N-type doped N + injection region and the first P well PW1 form a first diode D1, the first high-concentration P-type doped P + injection region serves as the anode of a diode D1, and the second high-concentration N-type doped N + injection region serves as the cathode of a diode D1;
a second buried layer BN2 is diffused in the P-type substrate and is isolated from the first buried layer BN1, a second N well NW2 is generated on the upper surface of the second buried layer BN2 and is distributed in a ring shape, a second P well PW2 is generated on the upper surface of the second buried layer BN2 and is positioned in a ring-shaped second N well NW2, a third high-concentration N-type doped N + injection region is annularly arranged on the upper part of the second N well NW2, a second high-concentration P-type doped P + injection region is arranged on the upper part of the second P well PW2 and is positioned in the center of the ring shape of the third high-concentration N-type doped N + injection region, the third high-concentration N-type doped N + injection region is connected with a control chip power supply Vdd, the second high-concentration P-type doped P + injection region is connected with the FB end of the control chip, the second N well NW2 and the second P well PW2 form a second diode D2, the second high-concentration P-type doped P + injection region serves as an anode of the diode D2, and the third high-concentration N + injection region serves as a cathode 2 of the diode D2;
a third high concentration P + implantation region disposed on the P-type substrate and between the first N well NW1 and the second N well NW2, serving as ohmic contact of the P-type substrate and connected to the ground line V of the control chipSS。
2. The ESD protection circuit in a flyback primary feedback switching power supply control chip according to claim 1, wherein: the first diode D1 and the second diode D2 are diodes formed by PN junctions or diode structures formed by MOS transistors.
3. The ESD protection circuit in a flyback primary feedback switching power supply control chip according to claim 1, wherein: the substrate is doped in a P type, and an isolation ring formed by a BN1 buried layer arranged on the P type substrate and an N well NW1 is doped in an N type; the isolating ring is one of a circular ring, a square ring or a rectangular ring.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910687578.1A CN110391223B (en) | 2019-07-29 | 2019-07-29 | ESD protection circuit in flyback primary side feedback switch power supply control chip |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910687578.1A CN110391223B (en) | 2019-07-29 | 2019-07-29 | ESD protection circuit in flyback primary side feedback switch power supply control chip |
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| CN110391223B true CN110391223B (en) | 2021-07-20 |
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| CN111046623B (en) * | 2019-11-05 | 2023-07-21 | 芯创智创新设计服务中心(宁波)有限公司 | Layout design method of ESD diode |
| CN113192952B (en) * | 2021-07-01 | 2021-09-28 | 微龛(广州)半导体有限公司 | High-voltage-resistant ESD protection device, structure and preparation method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2424098A1 (en) * | 2010-08-27 | 2012-02-29 | Nxp B.V. | Primary side sensing of an isolated converter |
| CN103427650A (en) * | 2013-07-16 | 2013-12-04 | 广州金升阳科技有限公司 | Input voltage sampling compensating circuit |
| CN106024779A (en) * | 2016-07-14 | 2016-10-12 | 中国电子科技集团公司第五十八研究所 | Two-way high voltage-withstanding ESD protection device structure |
| CN108512442A (en) * | 2017-11-27 | 2018-09-07 | 昂宝电子（上海）有限公司 | Switching power control system |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7116563B2 (en) * | 2004-05-19 | 2006-10-03 | Semtech Corporation | Dual mode over-current protection for switching mode power converter |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2424098A1 (en) * | 2010-08-27 | 2012-02-29 | Nxp B.V. | Primary side sensing of an isolated converter |
| CN103427650A (en) * | 2013-07-16 | 2013-12-04 | 广州金升阳科技有限公司 | Input voltage sampling compensating circuit |
| CN106024779A (en) * | 2016-07-14 | 2016-10-12 | 中国电子科技集团公司第五十八研究所 | Two-way high voltage-withstanding ESD protection device structure |
| CN108512442A (en) * | 2017-11-27 | 2018-09-07 | 昂宝电子（上海）有限公司 | Switching power control system |
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