CN112420691B - Distributed ESD device with embedded SCR structure - Google Patents
Distributed ESD device with embedded SCR structure Download PDFInfo
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- CN112420691B CN112420691B CN202011348372.5A CN202011348372A CN112420691B CN 112420691 B CN112420691 B CN 112420691B CN 202011348372 A CN202011348372 A CN 202011348372A CN 112420691 B CN112420691 B CN 112420691B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
- H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
Abstract
The invention relates to the technical field of electrostatic discharge protection of integrated circuits, in particular to a distributed ESD device embedded into an SCR structure, which comprises a substrate, wherein the substrate comprises a deep N well region and a cascade diode unit arranged on the deep N well region, the cascade diode unit comprises a third N well region and a P well region which are adjacently arranged, a third P + injection region is arranged in the third N well region, and a third N + injection region is arranged in the third P + injection region in an isolated manner; a fourth N + injection region is arranged in the P well region, and a fourth P + injection region is arranged in the fourth N + injection region in an isolated manner; the third P + injection region is connected with the anode, the third N + injection region is connected with the fourth P + injection region, and the fourth N + injection region is connected with the cathode. The invention solves the problem that the current processing capability of the existing ESD device with the cascade diode structure is low.
Description
Technical Field
The invention relates to the technical field of electrostatic discharge protection of integrated circuits, in particular to a distributed ESD device embedded into an SCR structure.
Background
ESD, i.e., electrostatic discharge, is a phenomenon that is ubiquitous in nature. ESD exists in every corner of people's daily life. Such conventional electrical phenomena are fatal threats to sophisticated integrated circuits.
With the improvement of the integrated circuit manufacturing process, the minimum line width of the integrated circuit is reduced to the submicron or even nanometer level, so that the performance of the chip is improved, and the anti-ESD striking capability is also greatly reduced, and therefore, the electrostatic damage is more serious. The contradiction between process development and the ESD immunity of the chip becomes a problem that must be considered by the integrated circuit designer.
Diodes are widely used for on-chip or system-level ESD protection due to their simple structure, high transparency, accurate model, etc. A cross-sectional view and an equivalent circuit of a conventional ESD device having a cascade diode structure composed of two diodes connected in series are shown in fig. 1, and a surface structure of the conventional ESD device having a cascade diode structure is shown in fig. 3. The device structure includes:
a P-type silicon substrate 110;
two spaced-apart nwell regions, namely a first nwell region 120 and a second nwell region 130, are formed on the silicon substrate 110;
a first N + injection region 121 is arranged in the first N well region 120, a first P + injection region 122 is arranged in the middle of the first N + injection region 121, and the first P + injection region 122 is connected with the anode;
a second N + injection region 131 is arranged in the second N well region 130, a second P + injection region 132 is arranged in the middle of the second N + injection region 131, the first N + injection region 121 is connected with the second P + injection region 132, and the second N + injection region 131 is connected with the cathode.
In the device, a first diode is formed between the first P + implantation region 122 and the first N + implantation region 121, the first N + implantation region 121 is an anode, and the first N + implantation region 121 is a cathode. A second diode is formed between the second P + implantation region 132 and the second N + implantation region 131, the second P + implantation region 132 is an anode, and the second N + implantation region 131 is a cathode. Since the first N + implant region 121 (first diode cathode) is connected to the second P + implant region 132 (second diode anode), two diodes in series are obtained. Vertical PNP transistors are formed among the first P + implantation region 122, the first nwell region 120, and the P-type silicon substrate 110, and vertical PNP transistors are also formed among the second P + implantation region 132, the second nwell region 130, and the P-type silicon substrate 110. The path formed by only two diodes connected in series can discharge ESD current, and the two parasitic PNPs can form a structure similar to a Darlington (Darlington tube), wherein the Darlington tube is also called a composite tube and is formed by connecting two triodes in series to form an equivalent new triode. The amplification factor of the equivalent triode is the product of the two, so that the equivalent triode is characterized by very high amplification factor but does not participate in the discharge of ESD current, and the existing ESD device with the cascade diode structure has lower leakage current and is not beneficial to the protection of a precise integrated circuit.
Disclosure of Invention
The invention aims to provide a distributed ESD device embedded into an SCR structure, and solves the problem that the current handling capacity of the existing ESD device with a cascade diode structure is low.
In order to achieve the above object, a distributed ESD device embedded in an SCR structure is provided, including a substrate, where the substrate includes a deep N-well region and a cascade diode unit disposed on the deep N-well region, the cascade diode unit includes a third N-well region and a P-well region disposed adjacently, a third P + injection region is disposed in the third N-well region, and a third N + injection region is separately disposed in the third P + injection region; a fourth N + injection region is arranged in the P well region, and a fourth P + injection region is arranged in the fourth N + injection region in an isolated manner; the third P + injection region is connected with the anode, the third N + injection region is connected with the fourth P + injection region, and the fourth N + injection region is connected with the cathode.
The working principle and the advantages are as follows:
1. in the ESD device provided by the scheme, an SCR structure is formed on a substrate due to the distribution arrangement among a deep N well region, a third P + injection region, a third N well region, a P well region and a fourth N + injection region, two diodes connected in series are formed by the distribution arrangement among the third P + injection region, the third N well region, the P well region and the fourth N + injection region and the external connecting line arrangement, the SCR structure and the diodes connected in series are cascaded diode units, and the SCR structure is parallel to a diode path between an anode and a cathode. When the I/O pad is subjected to ESD stress, the series diodes will first conduct quickly to drain ESD current. As the current increases, the voltage between the anode and cathode increases, triggering the parasitic SCR structure and creating a positive feedback between transistor Q1 and transistor Q2 in the SCR structure, creating another ESD current path to bleed ESD current. And the on-resistance of the SCR path is much smaller than the on-resistance of the diode path, so that the SCR structure will drain ESD current more strongly, which will dominate the ESD current drainage, while the series-connected diodes will assist the SCR structure in draining ESD current. The ESD device provided by the scheme not only increases the discharge path of the ESD current path, but also integrally improves the current handling capacity of the ESD device under the ESD stress.
2. The arrangement of the cascade diode unit can reduce the on-resistance of the ESD device, thereby reducing the clamping voltage of an ESD current path in the whole ESD device.
Furthermore, a resistor is externally connected between the third N + injection region and the fourth P + injection region of the cascade diode unit.
The SCR structure and the diodes connected in series can form a parallel loop, and the resistance of the whole diode connected in series can be increased by inserting the resistor between the two diodes connected in series, so that the characteristics of the parallel circuit show that the parallel voltage is the same, the larger the resistance is, the smaller the current flows through, and therefore the parasitic SCR structure can be triggered more effectively by the external resistor between the third N + injection region and the fourth P + injection region, and the current handling capacity of the ESD device under ESD stress is improved.
Furthermore, a plurality of cascade diode units which are arranged in parallel and at equal intervals are distributed on the deep N well region, third N + injection regions of the cascade diode units are connected through a lead, fourth P + injection regions of the cascade diode units are connected through a lead, and the sum of the areas of the cascade diode units on the surface of the substrate is equal to the area of the single cascade diode unit on the surface of the substrate.
The third N + injection regions of the cascade diode units are connected through a lead, and the fourth P + injection regions of the cascade diode units are connected through a lead, so that the cascade diode units are connected in parallel, each of the cascade diode units also forms two diodes and an SCR structure which are connected in series, and the current handling capacity of the ESD device under ESD stress can be ensured. And distributed and the setting of parallel and equidistant arrangement for every cascade diode unit is dispersed, and the heat that its produced is more for the heat that only cascade diode unit produced and is dispersed and be difficult for concentrating, thereby on the same area, the cascade diode unit radiating effect that the dispersion set up is better, can prevent that only cascade diode unit from concentrating on one point because of the heat and overheated and lead to the ESD device to become invalid more effectively, and then improved the robustness of ESD device.
Further, the number of the cascade diode units is more than or equal to two. The larger the number of cascaded diode units, the better the heat dissipation effect.
Furthermore, the N + injection region and the P + injection region which are arranged on the substrate are isolated by arranging an STI structure.
The STI structure is a process for manufacturing isolation regions between active regions of transistors on a substrate, and can effectively ensure that N-type and P-type doped regions can be thoroughly separated. Compared with the traditional intrinsic oxidation isolation technology, the shallow trench isolation technology can reduce the leakage current between electrodes and bear larger breakdown voltage.
Further, the third P + implantation region and the fourth N + implantation region are both annularly arranged. ESD current distribution efficiency can be improved.
Drawings
Fig. 1 is a cross-sectional view and an equivalent circuit diagram of a conventional ESD device having a cascade diode structure;
FIG. 2 is a cross-sectional and equivalent circuit diagram of a distributed ESD device with embedded SCR structures according to the present invention;
fig. 3 is a schematic surface structure diagram of a conventional ESD device with a cascade diode structure;
fig. 4 is a schematic surface structure diagram of a distributed ESD device embedded in an SCR structure according to an embodiment of the present invention;
FIG. 5 is a current-voltage graph of a TLP measurement;
FIG. 6 shows DS typ And DS new Two transient response waveforms at a 30V vf TLP impact.
Detailed Description
The following is further detailed by way of specific embodiments:
reference numerals in the drawings of the specification include: the semiconductor device includes a silicon substrate 110, a first N well region 120, a first N + implantation region 121, a first P + implantation region 122, a second N well region 130, a second N + implantation region 131, a second P + implantation region 132, a substrate 210, a third N well region 220, a third P + implantation region 221, a third N + implantation region 222, a P well region 230, a fourth N + implantation region 231, a fourth P + implantation region 232, and a deep N well region 240.
Examples
A distributed ESD device embedded in an SCR structure substantially as shown in figure 2 of the accompanying drawings: including a substrate 210, the substrate 210 including a deep nwell region 240 and cascaded diode cells disposed on the deep nwell region 240. As shown in fig. 4, the substrate 210 is arranged in a distributed layout structure, and the number of the cascade diode units is greater than or equal to two. In this embodiment, four cascade diode units are arranged in parallel and at equal intervals, and each of the cascade diode units has the same structure. As shown in fig. 3 and 4, the sum of the areas of the four cascaded diode units on the surface of the substrate 210 is equal to the area of the single cascaded diode unit on the surface of the substrate.
As shown in fig. 2, the cascode diode unit includes a third N well region 220 and a P well region 230 that are adjacently disposed, a third P + injection region 221 is disposed in the third N well region 220, and a third N + injection region 222 is disposed in the third P + injection region 221 by an STI structure isolation. A fourth N + implantation region 231 is disposed in the P well region 230, and a fourth P + implantation region 232 is disposed in the fourth N + implantation region 231 and isolated by an STI structure. The third P + implant region 221 is connected to the anode and the fourth N + implant region 231 is connected to the cathode. The third P + implantation region 221 and the fourth N + implantation region 231 are both annularly disposed.
A parasitic SCR structure is formed between the third P + implant region 221, the third nwell region 220, the P-well region 230, and the fourth N + implant region 231. The SCR structure can be viewed as a PNPN four-layer three-terminal device, with a total of three PN junctions. As shown in fig. 2, it can also be regarded as a composite tube composed of a PNP transistor (Q1) and an NPN transistor (Q2).
A first diode is formed between the third P + implantation region 221 and the third N + implantation region 222, wherein the third P + implantation region 221 is an anode and the third N + implantation region 222 is a cathode. A second diode is formed between the fourth P + implantation region 232 and the fourth N + implantation region 231, wherein the fourth P + implantation region 232 is an anode and the fourth N + implantation region 231 is a cathode. A resistor is connected between the third N + injection region 222 and the fourth P + injection region 232, and the parasitic SCR structure can be triggered more effectively by the resistor. Therefore, the first diode and the second diode are connected in series through the resistor, and the conduction path of the diode after the series connection is parallel to the current leakage path of the SCR structure.
The third N + injection regions 222 of the four cascaded diode units are all connected through a conducting wire, and the fourth N + injection regions 231 of the four cascaded diode units are all connected through a conducting wire. Each first diode formed by the four cascaded diode units is connected in parallel, and each second diode formed by the four cascaded diode units is also connected in parallel. In this embodiment, there is only one resistor connected between the third N + implantation region 222 and the fourth P + implantation region 232.
The specific implementation process is as follows:
when the I/O pad is subjected to ESD stress, the two diodes in series will first turn on rapidly to drain the ESD current. As the current increases, the voltage between the anode and cathode increases, triggering the parasitic SCR structure and creating positive feedback between transistor Q1 and transistor Q2 in the SCR structure, creating another ESD current path to bleed the ESD current. Also the on-resistance of the SCR path is much smaller than the on-resistance of the diode path, so that the SCR will drain the ESD current more strongly, which will dominate the ESD current. The ESD device of this scheme is different from a DTSCR (diode-triggered silicon controlled rectifier) which injects the conduction current of a diode into a substrate to trigger an SCR, and the ESD device of this scheme relies on a voltage drop between an anode and a cathode to trigger a parasitic SCR structure.
Therefore, compared with the existing ESD device with the cascade diode structure, the ESD device has the advantages that the discharge path of the ESD current path is increased, and the discharge capacity of the ESD current is enhanced, so that the current processing capacity of the ESD device under the ESD stress is improved. And the on-resistance of the ESD device can be reduced, so that the clamp voltage of the ESD current path in the entire ESD device can be reduced.
In order to study the ESD current discharging capability and the clamping voltage of the ESD device of the present embodiment and the existing ESD device having the cascade diode structure, two tests were performed. The first is the testing of ESD current bleed capability using pulses with a rise time of 10ns and a width of 100 ns. The current-voltage plot (I-V plot) of the TLP measurement is shown in FIG. 5, where DS is typ Refers to an existing ESD device with a cascaded diode structure, DS new Refers to the ESD device of this scheme. As can be seen from fig. 5, although the turn-on voltage (Vt) is almost the same and about 0.7V, the ESD device of the present scheme has the secondary trigger and snapback characteristics, and when the input voltage is 0.7V-5V, the two diodes connected in series will first turn on rapidly to discharge the ESD current. And when the input voltage reaches 5V, the parasitic SCR structure is conducted to form secondary triggering, and the conduction resistance of the SCR structure is far smaller than the sum of the self resistance of the two series diodes and the resistance of the series diodes due to the fact that the SCR structure has smaller conduction resistance. The characteristics of the parallel circuit are feasible, the voltages at two ends of the parallel device are equal, and if the resistance is smaller, the current flowing through the parallel device is larger. Therefore, when the SCR structure is conducted, the flowing current is larger, and the ESD current discharge capacity is higher than that of the series connection of the SCR structureThe pole conduits and resistance are stronger and will dominate the discharge of ESD current. In addition, the thermal failure current It2 of the ESD device is 4.5A and is larger than the thermal failure current It2 (3.5A) of the existing ESD structure, which means that the device can achieve an HBM ESD protection level of more than 6 KV.
The clamp voltage test was followed using a TLP pulse (vf-TLP) with a rise time of 0.2ns and a width of 5ns, which mimics the ESD stress of CDM (charged device model). FIG. 6 shows two transient response waveforms at a 30V vf-TLP impact. The on-time, labeled Ton in fig. 6, is defined as the time range from 90% of the peak voltage to 110% of the average voltage. It can be seen that the ESD device of the present scheme has almost the same turn-on speed as the existing ESD device. The clamp voltage is labeled Vclamp in fig. 6 and is defined as the average value of the 90% to 70% interval of the average voltage. It can be seen that although the overshoot voltage of the ESD device of the present scheme is higher than that of the existing ESD device, the clamp voltage Vclamp of the ESD device of the present scheme is about 4.2V, and the clamp voltage Vclamp of the existing ESD device is about 4.8V. It can be seen that the present scheme has a smaller clamping voltage.
Because the cascade diode unit of the ESD device adopts a distributed layout structure, as shown in figure 4, after the single cascade diode unit is divided into four cascade diode units, the current processing capacity of the ESD device under ESD stress can be ensured, and the cascade diode units are distributed and arranged in parallel and at equal intervals, so that each cascade diode unit is dispersed, the heat generated by each cascade diode unit is more dispersed and is not easy to concentrate relative to the heat generated by the single cascade diode unit, therefore, on the same area, the heat dissipation effect of the dispersedly arranged cascade diode units is better, the single cascade diode unit can be more effectively prevented from being overheated to cause the failure of the ESD device due to the heat concentration on one point, and the robustness of the ESD device is further improved.
Transient injection of a certain amount of charge will result in a rapid increase in the local temperature of the semiconductor device, which will lead to unrecoverable failure of the integrated circuit. The temperature change of the device caused by the ESD current can be calculated by the following formula:
Q＝C S MΔT＝C S VρΔT
where Q is the total heat, cs is the specific heat capacity of silicon, M is the mass, ρ is the density, V is the volume, and Δ T is the time difference. Theoretically, the total effective area is the same and bears the same ESD stress, as shown in fig. 3 and fig. 4, the temperature rise of the diode formed by the four cascaded diode units of the ESD device according to the present embodiment is the same as the temperature rise of a single large-area diode in the existing ESD device. Since the peak temperature is located in the center of the contact between the electrode and the semiconductor. Although there is thermal interaction between adjacent cascaded diode units (P-well regions 230 or N-well regions) in the distributed layout structure, due to the design of the distributed layout, the heat generation points are more dispersed rather than concentrated at one point, so that the heat dissipation effect is better.
In summary, the ESD device according to the present disclosure has better current handling capability, better heat dissipation effect, and smaller clamping voltage compared to the existing ESD device with the cascade diode structure, so that the robustness is greatly enhanced.
The foregoing is merely an example of the present invention, and common general knowledge in the field of known specific structures and characteristics is not described herein in any greater extent than that known in the art at the filing date or prior to the priority date of the application, so that those skilled in the art can now appreciate that all of the above-described techniques in this field and have the ability to apply routine experimentation before this date can be combined with one or more of the present teachings to complete and implement the present invention, and that certain typical known structures or known methods do not pose any impediments to the implementation of the present invention by those skilled in the art. It should be noted that, for those skilled in the art, without departing from the structure of the present invention, several changes and modifications can be made, which should also be regarded as the protection scope of the present invention, and these will not affect the effect of the implementation of the present invention and the practicability of the patent. The scope of the claims of the present application shall be defined by the claims, and the description of the embodiments and the like in the specification shall be used to explain the contents of the claims.
Claims (5)
1. A distributed ESD device embedded in an SCR structure comprising a substrate, characterized in that: the substrate comprises a deep N well region and a cascade diode unit arranged on the deep N well region, the cascade diode unit comprises a third N well region and a P well region which are arranged adjacently, a third P + injection region is arranged in the third N well region, and a third N + injection region is arranged in the third P + injection region in an isolated mode; a fourth N + injection region is arranged in the P well region, and a fourth P + injection region is arranged in the fourth N + injection region in an isolated manner; the third P + injection region is connected with the anode, the third N + injection region is connected with the fourth P + injection region, and the fourth N + injection region is connected with the cathode;
the deep N well region is provided with a plurality of cascade diode units which are arranged in parallel at equal intervals in a distributed mode, third N + injection regions of the cascade diode units are connected through a wire, fourth P + injection regions of the cascade diode units are connected through a wire, and the sum of the areas of the cascade diode units on the surface of the substrate is the area of the single cascade diode unit on the surface of the substrate.
2. The distributed ESD device embedded in an SCR structure of claim 1, wherein: and a resistor is externally connected between the third N + injection region and the fourth P + injection region of the cascade diode unit.
3. A distributed ESD device embedded in an SCR structure according to claim 1, wherein: the number of the cascade diode units is more than or equal to two.
4. The distributed ESD device embedded in an SCR structure of claim 1, wherein: the N + injection region and the P + injection region arranged on the substrate are isolated by arranging an STI structure.
5. The distributed ESD device embedded in an SCR structure of claim 1, wherein: and the third P + injection region and the fourth N + injection region are both annularly arranged.
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| KR20080061004A (en) * | 2006-12-27 | 2008-07-02 | 주식회사 하이닉스반도체 | Electrostatic discharge protection circuit and the method of layout thereof |
| CN103972233A (en) * | 2014-05-30 | 2014-08-06 | 电子科技大学 | SCR (Semiconductor Control Rectifier) shut-off device with latching resistant capability |
| CN108899317A (en) * | 2018-07-09 | 2018-11-27 | 江南大学 | A kind of bidirectional transient voltage suppressor of diode string auxiliary triggering SCR |
| CN211507641U (en) * | 2020-02-21 | 2020-09-15 | 上海维安半导体有限公司 | Novel silicon controlled rectifier device with low-clamping embedded capacitor-reducing diode |
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| US8586423B2 (en) * | 2011-06-24 | 2013-11-19 | International Business Machines Corporation | Silicon controlled rectifier with stress-enhanced adjustable trigger voltage |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20080061004A (en) * | 2006-12-27 | 2008-07-02 | 주식회사 하이닉스반도체 | Electrostatic discharge protection circuit and the method of layout thereof |
| CN103972233A (en) * | 2014-05-30 | 2014-08-06 | 电子科技大学 | SCR (Semiconductor Control Rectifier) shut-off device with latching resistant capability |
| CN108899317A (en) * | 2018-07-09 | 2018-11-27 | 江南大学 | A kind of bidirectional transient voltage suppressor of diode string auxiliary triggering SCR |
| CN211507641U (en) * | 2020-02-21 | 2020-09-15 | 上海维安半导体有限公司 | Novel silicon controlled rectifier device with low-clamping embedded capacitor-reducing diode |
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