CN110379850A - Groove-type power transistor manufacture method - Google Patents
Groove-type power transistor manufacture method Download PDFInfo
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- CN110379850A CN110379850A CN201810329443.3A CN201810329443A CN110379850A CN 110379850 A CN110379850 A CN 110379850A CN 201810329443 A CN201810329443 A CN 201810329443A CN 110379850 A CN110379850 A CN 110379850A
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- 238000000034 method Methods 0.000 title claims abstract description 34
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 26
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- 239000000463 material Substances 0.000 claims abstract description 9
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 5
- 238000002347 injection Methods 0.000 claims description 27
- 239000007924 injection Substances 0.000 claims description 27
- 239000011159 matrix material Substances 0.000 claims description 14
- 238000005192 partition Methods 0.000 claims description 10
- 229910052751 metal Inorganic materials 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 5
- 238000000137 annealing Methods 0.000 claims description 3
- 239000004020 conductor Substances 0.000 claims description 3
- 239000007943 implant Substances 0.000 claims description 3
- 210000001364 upper extremity Anatomy 0.000 claims description 2
- 238000001039 wet etching Methods 0.000 claims description 2
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The present invention is a kind of groove-type power transistor manufacture method, after carrying out development etching to a formation reserved layer on base material using general light shield technique, the position of the reserved layer is in the position for determining the gate trench in conductive post channel (contact) and substrate, multiple position, which not will receive later fabrication steps, to be influenced and generates offset problem, and the position for being precisely controlled conductive column and grid is reached；Using non-high-end board, highdensity element arrangements are realized with the production process of low cost, also can ensure that the yields and stability of power transistor.
Description
Technical field
The present invention is a kind of power crystal regulation law, espespecially a kind of groove-type power crystal with good contraposition precision
Regulation law.
Background technique
Groove-type power transistor (Trench power transistors) mainly includes MOS field
Transistor (MOSFETs) and two class component of insulated gate bipolar transistor (IGBTs) are imitated, currently in order to promoting groove-type power crystal
The output electric current of pipe, can try the width for reducing structure cell spacing (cell pitch) in process, when structure cell spacing is smaller, represent
The groove (trench) that greater number can be produced in unit area, enables groove-type power transistor that can export higher electricity
Stream.
Majority manufacturer is mainly still with 6 inch, 8 inch wafer manufacturing groove-type power transistors at present.Even if being using DUV
The ability of the high-end photoetching equipment of technology (Deep UV), the minimum structure cell spacing (cell pitch) that can be produced is about 0.8
μm, it is difficult to it further reduces again.And multiple tracks step of exposure can be related in photoetching process, it is easy to produce cumulative contraposition deviation,
Cause position generation offset or the area size of internal element (such as electrode zone) inconsistent, then the electric characteristics of product will become
Problem unstable and that generation yields is relatively low, as shown in figure 16, structure cell spacing (cellpitch) is indicated with P, grid spacing
(mesas) indicate that the width of adjacent source regions is respectively A, B with M, it can be seen that the position of conductive column is offset, therefore electric current I without
Method is evenly distributed in source area.
Furthermore high-end photoetching equipment also needs the light shield for arranging in pairs or groups fine to use, therefore cost of manufacture inevitably improves.
Summary of the invention
The main object of the present invention is to provide a kind of " groove-type power transistor manufacture method ", is being without the use of the high-end light of DUV
Under the premise of carving board, it can effectively reduce grid spacing (mesas) and be lower than 0.8 μm hereinafter, simultaneously holding element is with respect between
Align precision.
" groove-type power transistor manufacture method " of the invention mainly includes the following steps:
A. prepare a substrate, form a reserved layer in the top surface of the substrate；
B. it forms a hard mask layer and reserves the top surface of layer in this；
C. multiple first openings are defined and are formed in the hard mask layer, which is divided by multiple first opening
Multiple mask blocks；
D. the reserved layer that etching removal is not covered by multiple mask block；
E. a partition wall being formed in each side of multiple mask block, the width of multiple partition wall is mutually the same, and adjacent two
There is an interval between a partition wall；
F. a gate trench is formed in the position at the respectively interval, respectively the gate trench is from the top surface of the substrate to downward
It stretches, the spacing of two neighboring gate trench is less than 1 micron；
G. a conductive layer is inserted inside the gate trench and in each first opening；
H. grid bus area (gate bus region) and source implant (source are defined in the conductive layer
Implanted region), and partial electroconductive layer is removed to form multiple grid row of openings and injection region opening, wherein the note
The width for entering area's opening is greater than the width of the grid row of openings；
I. to formation plurality of source regions inside the substrate for being exposed to injection region opening；
J. an insulating layer is covered comprehensively, and etches a part of insulating layer of removal, to form multiple conductive column upper grooves,
The center of each conductive column upper groove is aligned the center of the reserved layer；
K. the respectively reserved layer and substrate below are removed, to form multiple conductive column lower channels, each conductive column lower part
Groove is connected with corresponding conductive column upper groove and forms conductive post channel；
L. conductive material being inserted in each conductive column trench interiors and forming multiple conductive columns, each conductive column is with the insulating layer
It is coplanar.
The present invention is the position for determining conductive post channel Yu door gate trench at the initial stage of technique using reserved layer position,
Ensuring position not will receive later fabrication steps influence and generates offset problem, reach the position for being precisely controlled conductive column and grid
It sets.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only
Some embodiments of the present invention, for those of ordinary skill in the art, without any creative labor, also
Other drawings may be obtained according to these drawings without any creative labor.
Fig. 1 is schematic diagram of the present invention in one reserved layer of the surface of silicon substrate formation.
Fig. 2, which is the present invention, to be reserved and forms the schematic diagram of a hard mask layer on layer at this.
Fig. 3 is the schematic diagram that the present invention etches the hard mask layer.
Fig. 4 is the schematic diagram of the present invention etching reserved layer.
Fig. 5 is the schematic diagram that the present invention forms the first clearance wall.
Fig. 6 A~Fig. 6 B is the schematic diagram that the present invention forms the second clearance wall.
Fig. 7 is the schematic diagram that the present invention forms gate trench.
Fig. 8 is the schematic diagram that the present invention forms grid oxic horizon.
Fig. 9 is the schematic diagram that the present invention inserts conductive layer in gate trench.
Figure 10 is the schematic diagram that the present invention makes source area with first embodiment.
Figure 11 is the schematic diagram that the present invention makes source area with second embodiment.
Figure 12 is the schematic diagram that the present invention forms conductive column upper groove.
Figure 13 is the schematic diagram that the present invention forms complete conductive post channel.
Figure 14 is the schematic diagram that the present invention forms complete conductive column.
Figure 15 is the present invention for making the schematic diagram of IGBT.
Figure 16 is its conductive column positional shift schematic diagram of normal power transistor.
Drawing reference numeral:
300 reserved 303 first insulating layer of layer
306 second insulating layer, 309 third insulating layer
Region is docked in 310 conductive column upper groove, 313 autoregistration
316 conductive column lower channel, 319 oxide layer
600 conductive layer, 603 grid oxic horizon
606 first clearance wall, 609 ' oxide layer
609 second clearance wall, 610 corner
619 insulating layers 723 first opening
729 mask blocks 753 interval
726 grid row of openings, 756 injection region opening
900 substrate, 903 matrix area
906 source area, 909 contact zone
910 gate trench, 913 conductive column
The doping of 916 surface metal-layer 919P types
M grid spacing P structure cell spacing
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.Based on this
Embodiment in invention, relevant technical staff in the field's every other reality obtained without making creative work
Example is applied, the range of protection of the invention is belonged to.
It please refers to shown in Fig. 1, the present invention prepares a substrate 900 first, which by taking N+ silicon substrate as an example, is herein
The high voltage bearing power component of production, on the surface of the substrate 900 would generally be formed with an epitaxial layer (N epi)；In the substrate
900 surface is initially formed a reserved layer 300, which is semi-conductor layer, production method including but not limited to:
Polysilicon deposition (poly deposition), monocrystalline silicon epitaxy (epitaxy), doping (implantation) etc..
It please refers to shown in Fig. 2, forms a hard mask layer (hard mask layer) on the surface for reserving layer 300, this is hard
Screening layer be lamination layer structure, it is possible to provide higher etch resistant ability, in this embodiment, the hard mask layer include from lower to upper according to
Sequence deposits one first insulating layer (silicon oxide), 303, one second insulating layer (nitride layer) 306 and one to be formed
Third insulating layer (silicon oxide) 309.Wherein, the depth according to the gate trench to be made (with reference to shown in Fig. 7), can
The appropriate thickness for determining abovementioned layers, for example, gate trench: reserved 300: the first insulating layer 303 of layer: second insulating layer
306: the opposite thickness proportion of third insulating layer 309 can be 4.4:1.6:0.1:0.7:1.6.
It please refers to shown in Fig. 3, carries out first of photoetching process on the hard mask layer, using one first light shield in the hard screening
Cap layer defines the position of the first opening 723, and the hard mask layer of 723 position of the first opening is removed in the way of etching and is exposed
The reserved layer 300；Meanwhile the hard mask layer not etched is configured to multiple mask blocks 729, each width of the mask block 729
It determines the width for the conductive column (contact) being electrically connected with electrode, while also determining grid ditch mortise (trench) indirectly
Width, this part can be in subsequent further explanation.In this step, the width of mask block 729 can between 0.3 μm~
Between 0.4 μm, because the width of the first opening 723 is larger, therefore special high-end groove light shield and high-end photoetching need not be used
Board can save cost of manufacture.
Referring to FIG. 4, carrying out anisotropic etching (anisotropic to the reserved layer 300 for being exposed to the first opening 723
Etching) to manifest the substrate 900.Each reserved layer 300 being retained on substrate 900 will define conduction in this step
The position of column lower channel (contact silicon trench), therefore determine without using photoetching process in the subsequent process
The position of the fixed conductive column lower channel can avoid traditional multiple tracks photoetching process and lead to the problem of contraposition offset, the present invention
It thus can the more accurate position for grasping the conductive column lower channel.
Fig. 5, Fig. 6 A, Fig. 6 B illustrate how to form partition wall in the side of reserved layer 300 and mask block 729.Such as Fig. 5 institute
Show, carries out anisotropic etching after each region first covers a layer insulating comprehensively, which is phase with second insulating layer 306
Same material, the insulating layer for being attached to 309 side wall of third insulating layer can be removed when carrying out anisotropic etching, and retain
Insulating layer will constitute one first clearance wall (nitride spacer) 606 and only be covered on reserved layer 300, the first insulating layer 303
And the side wall surface of the second insulating layer 306.When the position highest for controlling first clearance wall 606 is only covered on and second insulating layer
306 etc. it is high when, and be not covered on the side wall of third insulating layer 309, can avoid subsequent technique when removing the third insulating layer 309
Afterwards, remaining insulating layer (nitride) is led to the problem of in the surface of the second insulating layer 306 and influence product quality.This is between first
The major function of gap wall 606 is to prevent from generating oxygen in the subsequent process to protect the reserved layer 300 and the first insulating layer 303
Change.
As shown in Figure 6A, one oxide layer 609 ' of covering is first then deposited in each region, then carries out Vertical Square as shown in Figure 6B
To anisotropic etching, be etched down to expose substrate 900, make the oxide layer 609 ' constitute one second clearance wall 609,
In, which is the sedimentary with high step coverage rate, uniform thickness or can equidistantly be covered on region surface.Such as Fig. 6 B
Shown, generated second clearance wall 609 is covered on the side wall of third insulating layer 309 and the first clearance wall 606 after etching, makes
A partition wall is collectively formed in first clearance wall 606 and second clearance wall 609, and the width of each partition wall is first clearance wall 606
And the width summation of second clearance wall 609.It is to expose between one between two adjacent second clearance walls 609 on 900 surface of substrate
Every 753, the width at the interval 753 is the width of gate trench, and in other words, the width of required gate trench can be opened by first
The width of mouth 723 and the thickness of clearance wall 609 codetermine, before not needing using high-end photoetching process and DUV light shield
0.18 μm of even smaller gate trench width can precisely be reached by putting.If passing through and when front-end process deviates
The deposition thickness for controlling the clearance wall 609, which also can be corrected suitably, obtains required gate trench width.
As shown in fig. 7, dry etching is carried out downwards to substrate 900 at interval 753 and forms a gate trench 910, it should
Gate trench 910 has a curved bottom.Then one of wet etching is carried out to the clearance wall 609 again, to expose outside the grid
The corner 610 of 910 upper limb of groove.The purpose for exposing the corner 610 is in order to be trimmed to arc edge in the subsequent process, to keep away
Exempt from the stress or electric discharge problem of angular shape generation.
As shown in figure 8, in each region surface one sacrificial oxide layer of growth, then the sacrificial oxide layer is removed immediately, while
The third insulating layer 309 and clearance wall 609 of same material can be removed, and removes the surface defect inside gate trench 910.It is moving
After sacrificial oxide layer, then at the surface of the gate trench 910 and exposed 900 surface of substrate with high-temperature oxydation (thermal
Oxidation) or depositional mode grow up a grid oxic horizon (gate oxide) 603.Wherein, no matter is first clearance wall 606
It is that the offer protective effect of layer 300 all is reserved to this and prevents its oxygen during making sacrificial oxide layer or grid oxic horizon
Change, prevents the width of the reserved layer 300 from generating variation.Because the position highest of first clearance wall 606 is only covered on and second
Insulating layer 306 is contour, after removing the third insulating layer 309, will not generate residue on the surface of the second insulating layer 306
Problem.
As shown in figure 9, a conductive layer 600 is covered to be preliminary in 910 inside of gate trench and 603 surface of grid oxic horizon,
The conductive layer 600 is polysilicon layer, and the height of the conductive layer 600 tentatively covered can first be slightly above the top of the second insulating layer 306
Face.The conductive layer 600 is etched followed by a photoresist auxiliary etch method (resist-assisted etch back), until
Until the top surface of conductive layer 600 and the top surface of the second insulating layer 306 are contour.In another embodiment, chemical machine can also be used
Tool polishing (CMP) removes conductive layer 600, it is made to be located at equal height with the second insulating layer 306.In this way, can obtain
Be conducive to carry out subsequent technique to a flat surfaces.
As shown in Figure 10, multiple grid row of openings 726 are etched on conductive layer 600 using the second light shield and injection region is opened
Mouth 756, to define grid bus area (gate bus region) and source implant (source implanted simultaneously
Region), wherein the grid row of openings 726 of drawing left is opened between the conductive layer 600 and reserved layer 300 not etched
Mouth width degree is smaller, and injection region is open 756 between adjacent reserved layer 300, and opening width is larger.Then remove again this
One clearance wall 606, and matrix injection and thermal annealing are carried out to the substrate of exposing 900 and form matrix area 903.In the present embodiment
In, slanting ion implanting mode can be used, source electrode injection is carried out to matrix area 903, to form source area 906；On the other hand,
In grid bus area because the width of grid row of openings 726 is small, the ion (such as dotted arrow expression) of oblique injection will receive and lead
Electric layer 600 and reserved layer 300 stop, and ion will not enter matrix area 903.
As shown in figure 11, in another embodiment for forming source area 906, layer of oxide layer can also be first covered comprehensively
319, because the width of grid row of openings 726 is smaller, therefore grid row of openings 726 can first fill up the oxide layer 319, and injection region is opened
Mouth 756 can only cover the layer of oxide layer 319 of condition of equivalent thickness because its width is big.The oxide layer 319 is carried out etc. to etching again
Afterwards, the oxide layer in injection region opening 756 can be only removed, but the oxide layer 319 of grid row of openings 726 only can surface portion shifting
It removes, still substantially remaines in grid row of openings 726 and as injection mask.In the present embodiment, can be used vertically downward from
Sub- injection mode (such as dotted arrow expression) carries out source electrode injection to the matrix area 903 of injection region opening 756, to form source area
906；On the other hand, ion is injected because grid row of openings 726 has oxide layer 319 as injection mask in grid bus area
It will receive blocking, matrix area 903 will not be entered.
As shown in figure 12, second insulating layer 306 is removed first, fills up another insulating layer 619 then at all openings, equally
One photoresist auxiliary etch method (resist-assisted etch back) or chemical machine are utilized to the top surface of the insulating layer 619
Tool polishing (CMP), and obtain the insulating layer 619 with flat surfaces.Then recycle a third light shield to the insulating layer 619
Etching removes insulating layer 619 in the top of corresponding reserved layer 300 and forms conductive column upper groove 310, the insulating layer not removed
619 are used as internal dielectric layer.Wherein, the opening width of the conductive column upper groove 310 is greater than the width of the reserved layer 300, with
Expose the reserved layer 300 and ensures that subsequent step can remove completely the reserved layer 300.Because the material of the reserved layer 300 is not
It is same as the insulating layer 619, and its position defines already, therefore it is inclined to generate contraposition when carrying out the etching operation of third light shield
It moves.
As shown in figure 13, the etching completely of layer 300 is reserved when the formation conductive column upper groove 310 and then to this, and again
Persistently extend downwardly the matrix area 903 that etching enters substrate 900.One is formed after reserved 300 position of layer of original is etched from right
Quasi- docking region 313, and matrix area 903 forms the conductive column lower part ditch being connected with autoregistration docking region 313 after etching
Slot 316.Contraposition forms different conductivity type inside the substrate 900 below the conductive column lower channel 316 in a manner of injection again
The contact zone 909 of state, herein by taking the injection of P+ material as an example, the contact zone 909 is to reduce metal and 900 two kinds of heterogeneous materials of substrate
Contact impedance when material docking.
As shown in figure 14, groove 310, autoregistration docking region 313 and conductive column lower channel 316 are to connect on the conductive column
It is logical that a conductive post channel (contact trench) is collectively formed, it deposits conductive material (such as tungsten) afterwards inside it and is returned
Etching forms a conductive column 913 (contact), and the height of the conductive column 913 is equal with the height of insulating layer 619, finally again
One surface metal-layer 916 is formed to be electrically connected the conductive column with depositional mode with the top surface of insulating layer 619 in the conductive column 913
913, the metal layer 916 is provided as source contact in Figure 14.The conductive column 913 can be identical with the material of surface metal-layer 916
Or it is different.In the example shown in Figure 14, surface metal-layer 916 is the active region of electrical connecting element, that is, passes through conductive column
It is electrically connected source area 906, matrix area 903 and contact zone 909.Grid spacing (mesas) between adjacent gate trenches is with M table
Show, the present invention can be less than 0.8 micron hereinafter, reaching time micron (sub-micrometer) grade.
If then will form the other conductive columns for being correspondingly connected with conductive layer 600 in grid bus area, other led by this
Electric column is electrically connected its corresponding surface metal-layer 916, which is used as gate contact.
The framework according to shown in Figure 14, if carrying out surface grinding, back-metal layer and shape to the bottom surface of the substrate 900 again
At drain electrode, the production of MOSFET can be completed, it will not go into details for the event of this part non-present invention feature.
Similarly, as shown in figure 15, if first first carrying out surface grinding and p-type doping 919 to the bottom surface of the substrate 900,
It finally deposits back-metal layer and forms collector, the production of IGBT can be completed.
Above-described specific embodiment has carried out further the purpose of the present invention, technical scheme and beneficial effects
It is described in detail, it should be understood that being not intended to limit the present invention the foregoing is merely a specific embodiment of the invention
Protection scope, all within the spirits and principles of the present invention, any modification, equivalent substitution, improvement and etc. done should all include
Within protection scope of the present invention.
Claims (11)
1. a kind of groove-type power transistor manufacture method, it is characterised in that:
A. prepare a substrate, form a reserved layer in the top surface of the substrate；
B. it forms a hard mask layer and reserves the top surface of layer in this；
C. multiple first openings are defined and are formed in the hard mask layer, which is divided into multiple by multiple first opening
Mask block；
D. the reserved layer that etching removal is not covered by multiple mask block；
E. in multiple mask block each side formed a partition wall, the width of multiple partition wall is mutually the same, it is two neighboring every
There is an interval between wall；
F. a gate trench is formed in the position at the respectively interval, respectively the gate trench is extended downwardly from the top surface of the substrate, phase
The spacing of adjacent two gate trench is less than 1 micron；
G. a conductive layer is inserted inside the gate trench and in each first opening；
H. grid bus area and source implant are defined in the conductive layer, and removes the conductive layer of part to form multiple grids
Row of openings and injection region opening, wherein the width of injection region opening is greater than the width of the grid row of openings；
I. to formation plurality of source regions inside the substrate for being exposed to injection region opening；
J. an insulating layer is covered comprehensively, and etches the removal part insulating layer, to form multiple conductive column upper grooves, each conduction
The center of column upper groove is aligned the center of the reserved layer；
K. the respectively reserved layer and substrate below are removed, to form multiple conductive column lower channels, each conductive column lower channel
It is connected with corresponding conductive column upper groove and forms conductive post channel；
L. conductive material being inserted in each conductive column trench interiors and forming multiple conductive columns, each conductive column and the insulating layer are flat altogether
Face.
2. groove-type power transistor manufacture method as described in claim 1, which is characterized in that in stepb, include:
One first insulating layer, a second insulating layer and a third insulating layer are sequentially formed from lower to upper in the top surface for reserving layer,
Wherein, which includes first insulating layer, the second insulating layer and the third insulating layer.
3. groove-type power transistor manufacture method as claimed in claim 2, which is characterized in that in step e, include:
In this reserve layer, first insulating layer and the second insulating layer side wall surface formed one first clearance wall, wherein this first
Clearance wall is identical material with second insulating layer；And
Form one second clearance wall in the respectively side of the third insulating layer and first clearance wall, make first clearance wall and this
Two clearance walls form the partition wall, and the width of the partition wall is first clearance wall and the overall width of second clearance wall.
4. groove-type power transistor manufacture method as claimed in claim 3, which is characterized in that in step f, further include:
After forming the gate trench, a wet etching is carried out, to expose outside the corner of the gate trench upper limb；
Remove second clearance wall and the third insulating layer；
A grid oxic horizon is formed in the gate trench interior surface.
5. groove-type power transistor manufacture method as claimed in claim 4, which is characterized in that in step g, the conductive layer with should
Second insulating layer is coplanar.
6. groove-type power transistor manufacture method as claimed in claim 5, which is characterized in that in step i, include:
Remove first clearance wall；
Matrix injection and thermal annealing are carried out to substrate and form matrix area；
Oblique ion implanting is carried out to the substrate being open in injection region is exposed, to form multiple source area.
7. groove-type power transistor manufacture method as claimed in claim 5, which is characterized in that in step i, include:
Remove first clearance wall；
Matrix injection and thermal annealing are carried out to substrate and form matrix area；
An oxide layer is deposited to be open in the respectively grid row of openings and injection region；
First-class tropism etching is carried out to remove the oxide layer in the opening of injection region to the oxide layer；
The injection of vertical direction is carried out to form multiple source area to the substrate in the opening of injection region.
8. groove-type power transistor manufacture method as claimed in claims 6 or 7, which is characterized in that in step j, each conductive column
The width of upper groove is greater than the width of reserved layer.
9. groove-type power transistor manufacture method as claimed in claim 8, which is characterized in that in step k, each conductive column lower part
The width of groove and the reserved layer equal in width；A contact zone is formed inside the substrate below the conductive column lower channel.
10. groove-type power transistor manufacture method as claimed in claim 9, which is characterized in that in step l, include: leading at this
A front metal layer is formed on the surface of electric column and insulating layer.
11. groove-type power transistor manufacture method as claimed in claim 10, which is characterized in that after step l, further wrap
Contain: forming a doping surfaces in the bottom surface of the substrate.
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090272982A1 (en) * | 2008-03-03 | 2009-11-05 | Fuji Electric Device Technology Co., Ltd. | Trench gate type semiconductor device and method of producing the same |
| CN102544100A (en) * | 2010-12-14 | 2012-07-04 | 万国半导体股份有限公司 | Self aligned trench MOSFET with integrated diode |
| CN105470307A (en) * | 2015-12-22 | 2016-04-06 | 上海华虹宏力半导体制造有限公司 | Trench gate power transistor and manufacturing method therefor |
| US9391167B1 (en) * | 2015-09-02 | 2016-07-12 | Hyundai Motor Company | Method for manufacturing semiconductor device |
| CN106057895A (en) * | 2015-04-08 | 2016-10-26 | 万国半导体股份有限公司 | Self-aligned contact for trench power MOSFET |
| US20180097078A1 (en) * | 2016-09-30 | 2018-04-05 | Alpha And Omega Semiconductor Incorporated | Composite masking self-aligned trench mosfet |
-
2018
- 2018-04-13 CN CN201810329443.3A patent/CN110379850B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090272982A1 (en) * | 2008-03-03 | 2009-11-05 | Fuji Electric Device Technology Co., Ltd. | Trench gate type semiconductor device and method of producing the same |
| CN102544100A (en) * | 2010-12-14 | 2012-07-04 | 万国半导体股份有限公司 | Self aligned trench MOSFET with integrated diode |
| CN106057895A (en) * | 2015-04-08 | 2016-10-26 | 万国半导体股份有限公司 | Self-aligned contact for trench power MOSFET |
| US9391167B1 (en) * | 2015-09-02 | 2016-07-12 | Hyundai Motor Company | Method for manufacturing semiconductor device |
| CN105470307A (en) * | 2015-12-22 | 2016-04-06 | 上海华虹宏力半导体制造有限公司 | Trench gate power transistor and manufacturing method therefor |
| US20180097078A1 (en) * | 2016-09-30 | 2018-04-05 | Alpha And Omega Semiconductor Incorporated | Composite masking self-aligned trench mosfet |
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