CN208674129U - A kind of transistor - Google Patents

Abstract

The utility model relates to technical field of semiconductors, and in particular to a kind of novel semi-conductor transistor, the transistor include: substrate, and the substrate is equipped with the channel region of a source region, a drain region and the connection source-drain area；One gate structure, the gate structure is vertical structure, when transistor is opened, the electronics of source electrode, it is flowed along two sides of internal vertical polycrystalline Si-gate to drain electrode, to realize that its trenched side-wall becomes the purpose of a plurality of conducting channel, the utility model has lower conducting resistance, higher current driving ability compared to more traditional planar ransistor structure.

Description

A kind of transistor

Technical field

The utility model relates to technical field of semiconductors, and in particular to a kind of novel semi-conductor transistor.

Background technique

Metal (metal)-oxide (oxide)-semiconductor (semiconductor) field effect transistor (metal-oxide-semiconductor) is A kind of field-effect transistor that can be widely used in analog circuit and digital circuit, wherein according to its ' channel ' work carrier Polarity is different, can be divided into " N-type " and " p-type " two types.Its working principle (is enhanced with N-channel enhancement mode MOSFET For type N-MOS pipe) be controlled using grid voltage " charge inducing " number, with change formed by these " charge inducings " Conducting channel situation, then achieve the purpose that control drain current.When grid voltage changes, the charge of induction in channel Amount also changes, and the width of conducting channel also becomes therewith, thus drain current changes, traditional work with the variation of grid voltage The silicon face of skill only has single layer channel, and transistor carrier flowing is limited to silicon face, thus the conductive capability quilt of transistor Structure is limited.

Utility model content

In view of the above circumstances, the utility model to be solved its technical problem the following technical solution is employed to realize.

The utility model embodiment also provides a kind of transistor, including, semiconductor substrate；Well region is formed in and described partly leads In body substrate；Silicon oxide layer is formed in the semiconductor substrate and well region upper surface；Several bar ditch being formed in the well region Slot；Gate oxide is formed in the trench wall；Gate structure, by being filled with polysilicon in the groove to be formed；Source Area and drain region are respectively formed in the two sides of the groove.

Further, silica is formed by low-pressure chemical vapor phase deposition in the semiconductor substrate and well region upper surface Layer, the silicon oxide layer cover the upper semiconductor.

Further, for the groove vertical in the upper semiconductor, the figure of the groove is strip, several institutes Groove is stated in parallel stripe-arrangement.

Further, it is formed in after several grooves in the well region, portion forms sacrificial oxide layer simultaneously in the trench Sacrificial oxide layer is removed, for eliminating the etching injury of trenched side-wall.

Further, the gate oxide is formed by dry-oxygen oxidation in the trench bottom surfaces and side wall.

Further, it forms the gate oxide to specifically include later, ion implantation technology is carried out to the trenched side-wall Adjusting threshold voltage.

Further, the gate structure specifically includes: being filled polycrystalline to the groove of adjusted threshold voltage Silicon；Filled polysilicon is carried out to carry out dry back quarter by barrier layer of silicon oxide layer, for retaining the polycrystalline of trench interiors The polysilicon upper surface of silicon, the gate structure is concordant with silicon oxide layer, and shape is mutually all strip with groove shape.

Further, the source region and drain region especially by photoetching is carried out to silicon oxide layer and pass through ion implantation technology shape At N+ layers of heavy doping, and it is formed in the well region close to the upper surface of gate structure.

Further, the transistor further includes body area, and the body area is formed in the well region by the upper of source area side Surface.

The technical solution of the utility model embodiment has the advantage that the base in the silicon face single layer channel of traditional handicraft On plinth, by changing the channel and grid structure of transistor, gate structure side forms conducting channel so that source and drain it Between form all-directional conductive structure, the significant increase conductive capability of transistor reduces the conducting resistance of transistor, great property Valence compares advantage.

Detailed description of the invention

The attached drawing for constituting a part of the utility model is used to provide a further understanding of the present invention, this is practical new The illustrative embodiments and their description of type are not constituteed improper limits to the present invention for explaining the utility model.

In the accompanying drawings:

Fig. 1 is substrate and well region structural schematic diagram described in the utility model embodiment；

Fig. 2 is silicon oxide layer structural schematic diagram described in the utility model embodiment；

Fig. 3 A is groove top view described in the utility model embodiment；

Fig. 3 B is the sectional view splitted along the A-A ' line of Fig. 3 A；

Fig. 4 is the structural schematic diagram of gate oxide described in the utility model embodiment；

Fig. 5 is the structural schematic diagram of ion implanting described in the utility model embodiment；

Fig. 6 is the structural schematic diagram of the filling of polysilicon described in the utility model embodiment；

Fig. 7 is the structural schematic diagram of removal polysilicon after the filling of polysilicon described in the utility model embodiment；

Fig. 8 A is source region and drain region plot structure schematic diagram described in the utility model embodiment；

Fig. 8 B is the sectional view splitted along the A-A ' line of Fig. 8 A；

Fig. 8 C is the sectional view splitted along the B-B ' line of Fig. 8 A；

Fig. 9 A is body plot structure schematic diagram described in the utility model embodiment；

Fig. 9 B is the sectional view splitted along the A-A ' line of Fig. 9 A；

Fig. 9 C is the sectional view splitted along the B-B ' line of Fig. 9 A；

Specific embodiment

It is clear in order to be more clear the purpose of this utility model, technical solution and advantageous effects, below in conjunction with Attached drawing in the utility model embodiment, the technical scheme in the utility model embodiment is clearly and completely described, shows So, the described embodiments are only a part of the embodiments of the utility model, instead of all the embodiments.It is practical new based on this Embodiment in type, every other implementation obtained by those of ordinary skill in the art without making creative efforts Example, fall within the protection scope of the utility model.

It is in the description of the present invention, it should be noted that term " center ", "upper", "lower", "left", "right", " perpendicular Directly ", the orientation or positional relationship of the instructions such as "horizontal", "inner", "outside" be based on the orientation or positional relationship shown in the drawings, or The utility model product using when the orientation or positional relationship usually put, be merely for convenience of description the utility model and letter Change description, rather than the device or element of indication or suggestion meaning must have a particular orientation, with specific orientation construct and Operation, therefore should not be understood as limiting the present invention.In addition, term " first ", " second ", " third " etc. are only used for area Divide description, is not understood to indicate or imply relative importance.

Usually using two complicated manufacture craft manufacturing semiconductor devices: front end manufacture and back-end manufacturing.Front end manufacture It include that multiple small pieces are formed on the surface of semiconductor wafer.Each small pieces include active and passive electronic member on the wafer Part, described active and passive electronic components are electrically connected to form functional circuitry, active electron component, such as transistor and two poles Pipe has the ability of control electric current flowing.Passive electronic components, such as capacitor, inductor, resistor and transformer.It generates Relationship between voltage and current necessary to execution circuit function.

By a series of processing step, passive and active element, the processing step are formed on the surface of semiconductor Including doping, deposition, photoetching, etching and planarization.Doping passes through the technology of such as ion implanting or thermal diffusion, adds impurities to In semiconductor material.Doping process changes the conductivity of the semiconductor material in active device, and semiconductor material is converted to absolutely Edge body, conductor, or dynamically change in response to electric field or base current the conductivity of semiconductor material.

Active and passive element is formed by the layer of the material with different electrical properties.It can be by partly by deposited material A variety of deposition techniques that the type of material is determined form these layers.For example, film deposition may include chemical vapor deposition, physics Vapor deposition, electrolysis plating and plated by electroless plating technique.Usually pattern each layer with formed active component, passive element or The part of electrical connection between element.

Below in conjunction with Fig. 1-Fig. 9 C, the production method for providing a kind of transistor to the utility model embodiment is carried out specifically It is bright, this method comprises:

S01: semiconductor substrate 10 is provided；

S02: well region 20 is formed in the semiconductor substrate 10；

S03: silicon oxide layer is formed in the semiconductor substrate and well region upper surface；

S04: several grooves 30 are formed in the well region 20；

S05: wall forms gate oxide in the groove；

S06: polysilicon is carried out in the groove and fills to form the gate structure；

S07: source region and the drain region for being located at the well region are formed in the groove two sides.

Channel and gate structure of the technical solution of the utility model embodiment by change transistor, gate structure side Face forms conducting channel, so that all-directional conductive structure is formed between source and drain, the significant increase conductive capability of transistor, Reduce the conducting resistance of transistor, great superiority of effectiveness.

With reference to the accompanying drawings, the specific method of the above-mentioned formation transistor is elaborated.

As shown in Figure 1, step S01: semiconductor substrate 10 is provided, specifically, substrate can be the following material being previously mentioned At least one of: silicon, germanium, GaAs, indium phosphide or silicon carbide etc., in addition, can be defined in semiconductor substrate active Area.To put it more simply, semiconductor substrate is only indicated with a blank herein, carrier of the substrate as the transistor, mainly Play the role of structural support, in the present embodiment, the material of the substrate is preferably silicon substrate, and silicon is most common, cheap And the semiconductor material that performance is stable.

As shown in Figure 1, step S02: well region 20 is formed in the semiconductor substrate 10, specifically, the semiconductor serves as a contrast Photoresist is covered in primary coat, ion implantation technology is carried out to the semiconductor using photoresist as masking film, by injecting N-type impurity shape At N well region.In some embodiments, semiconductor substrate by thermal oxidation technology formed silicon oxide film, using silicon oxide film as It shelters film and ion implantation technology or diffusion technique is carried out to the semiconductor, N well region is diffuseed to form by N-type impurity, lead to Cross the p-well region that diffuses to form of p type impurity, the well region is horizontally formed under the surface of substrate, the p type impurity be boron, aluminium, Gallium, indium etc., the N-type impurity are phosphorus, arsenic, antimony, bismuth etc..It in other embodiments, can not also be by way of exposure mask, directly It connects and well region is formed to the ion implanting mode that the semiconductor substrate being lightly doped is focused.

As shown in Fig. 2, step S03: forming silicon oxide layer 30 in the semiconductor substrate 10 and 20 upper surface of well region, specifically , surface forms silicon oxide film layer by film deposition art on the semiconductor, and thin-film deposition refers to any in silicon chip substrate On physically or chemically deposit the technique of a tunic, belong to a kind of technique of thin film fabrication, the film deposited can be conductor, absolutely Edge material or semiconductor material, such as silica, silica, polysilicon and metal.The technique deposited has chemical gas The mutually method of deposit, plating, physical vapor deposition, evaporation and spin coating.In the present embodiment, pass through low-pressure chemical vapor phase deposition Method forms layer of silicon dioxide film layer, for the hard exposure mask as subsequent silicon groove etching.More specifically, the thickness of silica coating Degree is usually between 2000A (Angstrom, angstrom) -8000A (Angstrom, angstrom).

As shown in figs.3 a and 3b, step S04: several grooves 40 are formed in the well region 20, specifically, in silica Layer upper 30 carries out coating photoresist then chemical wet etching, and etch areas is the region of subsequent trench, and lithographic method is plasma Dry etching, the gas of etching are fluorine base gas；Then using silicon oxide layer as hard exposure mask is carried out to the substrate of lower section dry method quarter Erosion forms groove, it is possible to understand that, by using photoetching, the pattern needed to form is transferred on photoresist from photomask, is made With the part through light of solvent removal photoetching agent pattern, the part to be patterned of exposure cutting optimal removes photoresist Residue leaves patterned layer.In the present embodiment, the depth of groove is less than well region junction depth, and groove width is permitted for technique Perhaps minimum feature, the width for being spaced about twice of groove between several grooves.

It specifically includes, form sacrificial oxide layer inside groove 40 and goes before executing step S05 and forming gate oxide Except sacrificial oxide layer, for eliminating the etching injury of trenched side-wall；It is appreciated that passing through after above step in the groove Wall forms gate oxide 50.

Wherein, sacrificial oxide layer is formed inside groove 40 and removes sacrificial oxide layer, after silica is formed, can be used The method of wet etching or dry etching removes the silica as sacrificial layer, and present embodiment is preferably removed by wet etching The silica of sacrificial layer.More specifically, between 850 DEG C -1000 DEG C, the thickness of sacrificial layer exists usual sacrificial layer oxidizing temperature Between 100A-1000A, the method for sacrificial layer removal is hydrofluoric acid wet etching, strips all surface silicon oxide layer.Pass through to be formed Sacrificial oxide layer simultaneously removes the etching injury that sacrificial oxide layer eliminates trench interiors, makes trench interiors flat-satin, is effectively promoted The q&r of subsequent gate oxide.

As shown in figure 4, step S05: gate oxide 50 is formed in 40 bottom surface of groove and side wall, specifically, half-and-half leading After body removal photoresist and gate oxide formed by dry-oxygen oxidation, wherein method for oxidation include dry-oxygen oxidation, wet-oxygen oxidation, Steam oxidation mixes oxychloride, Oxidation Process By Hydrogen Oxygen Synthesis etc., in the present embodiment preferred dry-oxygen oxidation, and oxidizing temperature is 800 DEG C- 1000 DEG C in oxidation process, are passed directly into oxygen and are aoxidized, the gate oxide compact structure generated by dry-oxygen oxidation, Even property and reproducible, it is strong to impurity screening ability, it is good with the adhesion of photoresist the advantages that.The thickness of gate oxide depends on The threshold voltage and grid pressure resistance demand of transistor, it is preferable that can be between 50A-500A.

As shown in figure 5, further including being infused to the trenched side-wall by ion after executing step S05 and forming gate oxide Enter process adjustments threshold voltage, specifically, the semiconductor substrate coats photoresist, using photoresist as masking film to described half Conductor carries out ion implantation technology, and the ion of injection is usually boron ion, and the energy of injection uses between 10Kev-50Kev The mode of inclination angle injection more specifically makes upper semiconductor and injects the angle β that ion beam is in 60 ° -80 ° or so, carry out four The injection of secondary boron element, and every injection is completed primary, 90 ° of rotation is carried out to the same direction to semiconductor, so that groove is every One face side wall has all carried out primary ions injection, for adjusting the threshold voltage of trenched side-wall.

As shown in Figure 6 and Figure 7, step S06: polysilicon filling 60 is carried out in the groove 40 and forms the gate structure 61, specifically, groove 40 be filled up completely by polysilicon after again using silicon surface oxidation silicon layer 30 as barrier layer, remove other regions Polysilicon only retain the polysilicons of trench interiors as gate structure 61, specifically, its filling mode includes normal pressure chemical gas Phase sedimentation, Low Pressure Chemical Vapor Deposition, plasma auxiliary chemical vapor deposition method etc., in the present embodiment, preferably Ground is Low Pressure Chemical Vapor Deposition, the polysilicon purity is high of doping, and uniformity is strong.More specifically, the thickness of polysilicon is big The width for being equal to groove is caused, after polycrystalline silicon growth, groove is completely filled, then using upper surface of substrate silicon oxide layer as blocking Layer carries out chemically mechanical polishing to polysilicon or dry back is carved, retains the polysilicon of trench interiors, remove the more of other regions Crystal silicon.

As shown in figures 8 a-8 c, source region 70 and the drain region for being located at the well region step S07: are formed in 40 two sides of groove 71, specifically, semiconductor carries out coating photoresist, the photoresist of corresponding source region and drain region is removed by etching technics, to source region It is heavily doped with the n-type semiconductor of arsenic, with the part injection in drain region to form 70 region of source electrode N+ floor and drain electrode 71st area of N+ floor Domain.Last two N+ layers have slight overlapping in the direction AA ' and groove, overlap size between 0.05-0.2um, two N+ layers Outermost ditch trough rim need to be exceeded perpendicular to the direction AA ', the width of gate oxide is approximately equal to beyond distance.

It as shown in Figure 9A-9C, further include in 20 side shape of well region after executing step S07 and forming source region 70 and drain region 71 Adult area 80, the body area 80 are located at the same side of the groove 40 with the source region 70, specifically, passing through Si-gate certainly in well region Technique of alignment carries out the photoetching and injection of body area P+ floor, and more specifically, carrying out coating photoresist to substrate, then chemical wet etching goes out Body area, for body area etching in the side of source region, the area Zai Duiti carries out ion implantation technology, and the impurity of injection is boron element, injects energy Amount is between 15-60Kev, and implantation dosage is between 1E15-1E16/CM2, it is preferable that body section length is consistent with source region length, wide Degree can be between 0.2-1um, and body area P+ floor forms body area in well region side, for avoiding latch-up.

Further, to semiconductor carry out source and drain heat treatment, specifically, heat treatment temperature usually 850 ° -1050 ° it Between, the time usually within a hour, for activating the impurity of source and drain and body area.Subsequent step is consistent with common process, Thin-film deposition, chemical wet etching contact hole grow metal, chemical wet etching, metal interconnection, element manufacturing completion.

The utility model embodiment provides a kind of transistor, including, semiconductor substrate；Well region is formed in the semiconductor On substrate；Silicon oxide layer is formed in the semiconductor substrate and well region upper surface；Several bar ditch being formed in the well region Slot；Gate oxide is formed in the trench wall；Gate structure, by being filled with polysilicon in the groove to be formed；Source Area and drain region are respectively formed in the two sides of the groove.

Planar gate structure is changed into vertical structure by the gate structure of change transistor by the utility model embodiment, So that the side of vertical gate structure forms conducting channel in transistor body, so that forming all-directional conductive knot between source and drain Structure.

Further, as shown in Figure 1, semiconductor substrate 10, including base semiconductor material, such as silicon, germanium, GaAs, Indium phosphide or silicon carbide are used for structural support.For N-MOS device, substrate initial dopant has p-type semiconductor material, such as Boron, aluminium or gallium impurity, to form well region under substrate surface, with the dosage of 1E13-1E14/CM2 with the ion of hundreds of Kev Injection, depositing p-type dopant.Other injections can be deposited with dosage appropriate and energy level.Ion implanting is not needed Exposure mask.Well region can reduce punchthrough effect, drain for clamper to the breakdown voltage of source electrode, reduce reverse recovery time, and It can be generally improved the robustness of transistor.

Further, as shown in Figure 1, being formed with well region 20 in semiconductor substrate 10, transistor can be n-channel field-effect (N-MOS) or p-channel field-effect tube (P-MOS) are managed, wherein " p " indicates that positive carrier type (hole) and " n " indicates load It flows subtype (electronics).Although the present embodiment can be used for forming P- with the description of N-MOS device, the semiconductor material of opposite types MOS device.For example, n-type substrate is initially adulterated with n-type semiconductor, such as phosphorus, antimony or arsenic impurities, to form n-well region Domain.

Further, as shown in Fig. 2, forming silicon oxide layer 30 in the semiconductor substrate 10 and 20 upper surface of well region, Upper semiconductor forms silicon oxide film layer, table on the silicon oxide film layer covering semiconductor by film deposition art Face forms layer of silicon dioxide film layer by low-pressure chemical vapor phase deposition method, for the hard exposure mask as subsequent silicon groove etching, institute The thickness of silicon oxide film layer is stated between 2000A-8000A.

Further, as shown in figs 3 a and 3b, several grooves 40 in well region 20,30 are coated on silicon oxide layer Then chemical wet etching, etch areas are the region of subsequent trench to photoresist, and lithographic method is plasma dry etch, etching Gas is fluorine base gas；Then dry etching is carried out to the substrate of lower section using silicon oxide layer as hard exposure mask and forms groove, it can be with Understand, by using photoetching, the pattern needed to form is transferred on photoresist from photomask, removes photoresist using solvent The part through light of pattern, the part to be patterned of exposure cutting optimal, removes the residue of photoresist, leaves patterning Layer.In the present embodiment, the figure of groove is strip, and several grooves are in parallel stripe-arrangement, the depth of the groove Degree is less than well region junction depth, and the groove width is the minimum feature that technique allows, being spaced about between several grooves The width of twice of groove.

Further, sacrificial oxide layer is formed by thermal oxide to inside groove 40, and removes sacrificial oxide layer, at one In embodiment, thermal oxidation process is dry-oxygen oxidation, and between 800 DEG C -1000 DEG C, the thickness of sacrificial layer exists sacrificial layer oxidizing temperature Between 100A-1000A, the method for sacrificial layer removal is HF wet etching, strips all surface oxide layer.The mesh of sacrificial layer processing Mainly eliminate trench interiors etching injury, make trench interiors flat-satin, can effectively promote subsequent gate oxide Q&r.

Further, as shown in figure 4, forming gate oxide 50 in 40 inner wall of groove, insulation or dielectric layer are formed On the upper surface and trench wall of substrate, as grid oxic horizon.The thickness control threshold voltage of gate oxide level, heat carry The injection of stream and grid-source voltage rated value, usually between 50A-500A, using dry-oxygen oxidation, oxidizing temperature is 800 Between DEG C -1000 DEG C, the gate oxide is formed in trenched side-wall and channel bottom.

Further, described as shown in figure 5, to 40 side wall of groove by ion implantation technology adjusting threshold voltage The threshold voltage of groove is when semiconductor is connected, so that grid voltage control semiconductor work is more accurate, the semiconductor lining Photoresist is covered in primary coat, carries out ion implantation technology to the semiconductor using photoresist as masking film, the ion of injection is usually Boron ion, the energy of injection by the way of the injection of inclination angle, more specifically, make upper semiconductor between 10Kev-50Kev It is in 70 ° -83 ° or so of angle β with injection ion beam, carries out the injection of four boron elements, and every injection is completed once, half-and-half to lead Body carries out 90 ° of rotation to the same direction, so that each surface side wall of groove has all carried out primary ions injection, for adjusting ditch The threshold voltage of groove sidewall.

Further, as shown in fig. 6, filled with polysilicon 60 to form gate structure 61, polycrystalline in the groove 40 The resistance of silicon layer can be lowered and being heavily doped with n-type semiconductor, such as arsenic.In this embodiment, it is preferred that filling out Filling mode is low-pressure chemical vapor deposition.

Further, as shown in fig. 7, after the completion of filling, using upper surface of substrate silicon oxide layer 30 as barrier layer, to polycrystalline Silicon carries out chemically mechanical polishing or dry back is carved, and removes the polysilicon in other regions, retains the polysilicon conduct of trench interiors The polysilicon upper surface of gate structure, the gate structure is concordant with silicon oxide layer, and shape is mutually all strip with groove shape, The gate structure its well region side wall formation conducting channel close to gate structure sidewall when semiconductor is connected.

Further, as shown in figures 8 a-8 c, source region 70 and drain region 71 are formed in 40 two sides of groove, semiconductor is coated Photoresist removes the photoresist of corresponding source region and drain region by etching technics, is heavily doped with to the part injection of source region and drain region The n-type semiconductor of arsenic, to form 70 region of source electrode N+ layer and drain electrode 71 region of N+ layer.Last two N+ layers in the direction AA ' Have with groove and slightly overlap, overlaps size between 0.05-0.2um, two N+ layers need to exceed outermost perpendicular to the direction AA ' Ditch trough rim, the width of gate oxide is approximately equal to beyond distance.

Further, as shown in Figure 9A-9C, body area 80 is formed in well region side, passes through Si gate self alignment technology in well region The photoetching and injection of body area P+ floor are carried out, more specifically, the coating photoresist then area chemical wet etching Chu Ti, body area are carried out to substrate Etching is in the side of source region, and the area Zai Duiti carries out ion implantation technology, and the impurity of injection is boron element, and Implantation Energy is in 15- Between 60Kev, implantation dosage is between 1E15-1E16/CM2, it is preferable that body section length is consistent with source region length, and width can be with Between 0.2-1um, body area P+ floor forms body area in well region side, for avoiding latch-up.

Planar gate structure is changed into vertical junction by the conducting channel and grid structure of change transistor by the utility model Structure, grid structure side form conducting channel, so that all-directional conductive structure is formed between source and drain, significant increase crystal The conductive capability of pipe reduces the conducting resistance of transistor.

The above is only the preferred embodiment of the utility model only, is not intended to limit the utility model, all at this Within the spirit and principle of utility model, any modification, equivalent substitution, improvement and etc. done should be included in the utility model Within the scope of protection.

Claims (9)

1. a kind of transistor characterized by comprising

Semiconductor substrate；

Well region is formed in the semiconductor substrate；

Silicon oxide layer is formed in the semiconductor substrate and well region upper surface；

Several grooves being formed in the well region；

Gate oxide is formed in the trench wall；

Gate structure, by being filled with polysilicon in the groove to be formed；

Source region and drain region are respectively formed in the two sides of the groove.

2. transistor according to claim 1, which is characterized in that pass through in the semiconductor substrate and well region upper surface low Chemical vapor deposition is pressed to form silicon oxide layer, the silicon oxide layer covers the upper semiconductor.

3. transistor according to claim 1, which is characterized in that the groove vertical is in the upper semiconductor, institute The figure for stating groove is strip, and several grooves are in parallel stripe-arrangement.

4. transistor according to claim 1, which is characterized in that it is formed in after several grooves in the well region, Portion forms sacrificial oxide layer and removes sacrificial oxide layer in the trench, for eliminating the etching injury of trenched side-wall.

5. transistor according to claim 1, which is characterized in that pass through dry-oxygen oxidation shape in the trench bottom surfaces and side wall At the gate oxide.

6. transistor according to claim 1, which is characterized in that form the gate oxide and specifically include later, to institute It states trenched side-wall and carries out ion implantation technology adjusting threshold voltage.

7. transistor according to claim 1, which is characterized in that the gate structure specifically includes:

Polysilicon is filled to the groove of adjusted threshold voltage；

Filled polysilicon is carried out to carry out dry back quarter by barrier layer of silicon oxide layer, for retaining the polycrystalline of trench interiors The polysilicon upper surface of silicon, the gate structure is concordant with silicon oxide layer, and shape is mutually all strip with groove shape.

8. transistor according to claim 1, which is characterized in that the source region and drain region especially by silicon oxide layer into Row photoetching and heavy doping N+ layers is formed by ion implantation technology, and it is formed in upper table of the well region close to gate structure Face.

9. transistor according to claim 1, which is characterized in that the transistor further includes body area, and the body area is formed The upper surface of source area side is leaned in the well region.