CN110379775B - Substrate stacking packaging structure and packaging method thereof - Google Patents

Substrate stacking packaging structure and packaging method thereof Download PDF

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Publication number
CN110379775B
CN110379775B CN201910667830.2A CN201910667830A CN110379775B CN 110379775 B CN110379775 B CN 110379775B CN 201910667830 A CN201910667830 A CN 201910667830A CN 110379775 B CN110379775 B CN 110379775B
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substrate
top surface
bonding pad
elastic
pad
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CN110379775A (en
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秦玲
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Shanghai Tongcheng Electronic Materials Co., Ltd
Red Avenue New Materials Group Co Ltd
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Shanghai Tongcheng Electronic Materials Co Ltd
Red Avenue New Materials Group Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Combinations Of Printed Boards (AREA)
  • Coupling Device And Connection With Printed Circuit (AREA)

Abstract

The invention provides a substrate stacking and packaging structure and a packaging method thereof, wherein the substrate stacking and packaging structure comprises a first substrate and a second substrate, wherein the first substrate is provided with a first Z-shaped step, and the second substrate is provided with a second Z-shaped step; the first Z-shaped step is matched with the second Z-shaped step in shape, the first bottom surface of the first substrate is in contact with the second top surface of the second substrate, the second bottom surface of the first substrate is in contact with the third top surface of the second substrate, and the first pad of the first substrate is electrically connected with the second pad of the second substrate through a conductive adhesive layer.

Description

Substrate stacking packaging structure and packaging method thereof
Technical Field
The invention relates to the field of semiconductor integrated circuit packaging, belongs to the H01L23/00 classification number, and particularly relates to a substrate stacking packaging structure and a packaging method thereof.
Background
Integrated circuit packaging is advancing with the development of integrated circuits. With the continuous development of various industries such as aerospace, aviation, machinery, light industry, chemical industry and the like, the whole machine also changes towards multifunction and miniaturization. Thus, the integrated circuit is required to have higher integration and more complex functions. Accordingly, the packaging density of the integrated circuit is required to be higher and higher, the number of leads is required to be higher and higher, the size is smaller and smaller, the weight is lighter and lighter, the updating is faster and faster, and the rationality and the scientificity of the packaging structure directly influence the quality of the integrated circuit. Thus, manufacturers and users of integrated circuits have a systematic understanding and appreciation of the physical dimensions, tolerances, structural features, and packaging materials of various packages of integrated circuits, in addition to mastering performance parameters and identifying lead arrangements of the various integrated circuits. So that the integrated circuit manufacturer does not choose to improperly package the integrated circuit to degrade its performance; and when the integrated circuit is used for collection design and assembly, an integrated circuit user can reasonably carry out plane layout and space occupation, and the purposes of proper type selection and reasonable application are achieved.
The integrated circuit package not only plays a role in electrically connecting the bonding point in the integrated circuit chip with the outside, but also provides a stable and reliable working environment for the integrated circuit chip, and plays a role in mechanical or environmental protection for the integrated circuit chip, so that the integrated circuit chip can play a normal function and is ensured to have high stability and reliability. In a word, the quality of the integrated circuit package is high, and the overall performance of the integrated circuit is greatly related. Therefore, the package should have strong mechanical properties, good electrical properties, heat dissipation and chemical stability.
Disclosure of Invention
The invention provides a substrate stacking and packaging structure, comprising:
the first substrate comprises a first bottom surface, a second bottom surface, a first top surface and a first connecting surface, wherein the first top surface is opposite to the first bottom surface and the second bottom surface, the first connecting surface is connected with the first bottom surface and the second bottom surface, the first bottom surface and the second bottom surface have height difference, the first bottom surface, the second bottom surface and the first connecting surface form a first Z-shaped step, and a first bonding pad is arranged on the first connecting surface;
the second substrate comprises a second top surface, a third bottom surface opposite to the second top surface and the third top surface, and a second connecting surface for connecting the second top surface and the third top surface, wherein the second top surface and the third top surface have height difference, the second top surface, the third top surface and the second connecting surface form a second Z-shaped step, and a second bonding pad is arranged on the second connecting surface;
the method is characterized in that: the first Z-shaped step is matched with the second Z-shaped step in shape, the first bottom surface is in contact with the second top surface, the second bottom surface is in contact with the third top surface, and the first bonding pad is electrically connected with the second bonding pad through a conductive bonding layer.
According to an embodiment of the present invention, the first top surface of the first substrate has a third pad, the second top surface of the second substrate has an elastic connector, the elastic connector includes a fixing portion inserted into the through hole of the second substrate and an elastic portion connected to the fixing portion, the elastic portion includes a first end, a second end and a connecting portion connecting the first end and the second end, the first end is fixed to the fixing portion, and the second end is press-fitted onto the third pad.
According to an embodiment of the present invention, the third pad is electrically connected to the second substrate through the elastic connection member.
According to an embodiment of the present invention, the third pad is a dummy pad which does not perform a conductive function.
According to an embodiment of the present invention, a groove is disposed on the second bottom surface, the groove penetrates through the first connection surface and the first side surface of the first substrate, a first chip is disposed in the groove, and the first chip is electrically connected to the first substrate.
According to an embodiment of the present invention, a second chip is disposed on the second top surface of the second substrate, and at least a portion of the elastic connection member crosses the second chip.
According to an embodiment of the present invention, further comprising a sealing layer sealing portions of the first top surface of the first substrate, the second top surface and the third top surface of the second substrate, the elastic connection member, the groove, the first and second chips.
According to an embodiment of the invention, an array of external connection terminals is provided on the third top surface, the array of external connection terminals being exposed from the sealing layer.
The invention also provides a substrate stacking and packaging method, which comprises the following steps:
providing a first substrate, wherein the first substrate comprises a first bottom surface, a second bottom surface, a first top surface opposite to the first bottom surface and the second bottom surface, and a first connecting surface connecting the first bottom surface and the second bottom surface, the first bottom surface and the second bottom surface have height difference, the first bottom surface, the second bottom surface and the first connecting surface form a first zigzag step, and a first bonding pad is arranged on the first connecting surface;
providing a second substrate, wherein the second substrate comprises a second top surface, a third bottom surface opposite to the second top surface and the third top surface, and a second connecting surface for connecting the second top surface and the third top surface, the second top surface and the third top surface have height difference, the second top surface, the third top surface and the second connecting surface form a second Z-shaped step, and a second bonding pad is arranged on the second connecting surface; wherein the first zigzag step matches the second zigzag step in shape;
and stacking the first substrate and the second substrate such that the first bottom surface is in contact with the second top surface, the second bottom surface is in contact with the third top surface, and the first pad is electrically connected to the second pad through a conductive adhesive layer.
According to an embodiment of the present invention, the first top surface of the first substrate has a third pad thereon, and the second top surface of the second substrate has an elastic connector thereon, the method further includes pressing the first substrate using the elastic connector, the elastic connector includes a fixing portion inserted into the through hole of the second substrate and an elastic portion connecting the fixing portion, the elastic portion includes a first end, a second end, and a connecting portion connecting the first end and the second end, the first end is fixed to the fixing portion, and the second end is pressed on the third pad.
The invention has the following advantages: the double-layer substrate overlapping structure can realize that multiple chips are integrated on a packaging substrate through the first substrate, and the elastic connecting piece is utilized for pressing or electrically connecting so as to realize the binding force between the substrates and increase the electric connection mode of the double substrates. In addition, the pads at the steps are electrically interconnected, so that the package size is reduced, and the pads can be protected.
Drawings
FIG. 1 is a cross-sectional view of a substrate stack package structure according to the present invention;
FIG. 2 is a top view of a substrate stack package structure according to the present invention;
FIG. 3 is a side view of a first substrate;
FIG. 4 is a side view of a second substrate;
FIGS. 5-8 are schematic diagrams of a substrate stack packaging method of the present invention;
fig. 9 is a cross-sectional view of a substrate stack package structure according to another embodiment.
Detailed Description
The invention aims to provide a packaging structure and a packaging method which are simple in packaging process, small in thickness and high in integration level.
Referring to fig. 1-4, the through-hole substrate-stacked package structure of the present invention includes a first substrate 2 and a second substrate 1, wherein the first substrate 2 is an additional substrate, and the second substrate 1 is a package substrate or a system board, both of which may be a PCB board or a ceramic substrate. Wherein the first substrate 2 includes a first bottom surface 22 and a second bottom surface 23, a first top surface opposite to the first and second bottom surfaces, and a first connection surface 24 connecting the first and second bottom surfaces, the first bottom surface and the second bottom surface have a height difference, the first bottom surface 22, the second bottom surface 23, and the first connection surface 24 form a first zigzag step, and a first pad 25 is disposed on the first connection surface 24; the second substrate 1 comprises a second top surface 13, a third top surface 12, a third bottom surface 11 opposite to the second top surface and the third top surface, and a second connection surface 14 connecting the second top surface and the third top surface, wherein the second top surface and the third top surface have a height difference, the second top surface 13, the third top surface 12 and the second connection surface 14 form a second zigzag step, and a second pad 26 is arranged on the second connection surface 14;
in the present invention, the first zigzag step matches the second zigzag step in shape, the first bottom surface 22 contacts the second top surface 13, the second bottom surface 23 contacts the third top surface 12, and the first pad 25 is electrically connected to the second pad 26 through a conductive adhesive layer 27. The conductive adhesive layer 27 may be selected from conductive pastes, which are conductive pastes. As can be seen from the top view of fig. 2, the first substrate 2 has a smaller area than the first substrate 1, and the third pads 31 on the first substrate 2 are exposed.
Referring to fig. 1-2, in order to ensure the bonding force between the first substrate 2 and the second substrate 1, the second top surface 22 of the second substrate 2 has an elastic connector, the elastic connector includes a fixing portion 17 inserted into the through hole 16 of the second substrate 1 and an elastic portion connected to the fixing portion 17, the elastic portion includes a first end 18, a second end 20 and a connecting portion 19 connecting the first end 18 and the second end 20, the first end 18 is fixed to the fixing portion 17, and the second end 20 is pressed on the third pad 31. The third pad 31 can be electrically connected to the second substrate 1 through the elastic connector, and the fixing portion 17 is a conductive plug electrically connected to the circuit of the second substrate 1. Preferably, the third pads 31 are dummy pads which do not function as electric conduction, and the first substrate 2 and the second substrate 1 are electrically interconnected only by the first pads 25 and the second pads 26.
Referring to fig. 1 and 3, a recess 30 is disposed on the second bottom surface 23, the recess 30 penetrates through the first connecting surface 24 and the first side surface of the first substrate 2, a first chip 3 is disposed in the recess 30, and the first chip 3 is electrically connected to the first substrate 2.
Referring to fig. 1 and 4, a second chip 21 is disposed on the second top surface 13 of the second substrate 1, and at least a portion of the elastic connection member crosses the second chip 21 (see the top view of fig. 2).
Further comprising a sealing layer 28, said sealing layer 28 sealing portions of said first top surface of said first substrate 2, said second top surface 13 and said third top surface 12 of said second substrate 1, said resilient connectors, said recesses 30, said first and second chips 3, 21. An external connection terminal array 15 is provided on the third top surface 12, and the external connection terminal array 15 is exposed from the sealing layer 28.
Referring to fig. 5 to 8, the present invention further provides a method for manufacturing the above substrate stack package structure, including:
referring to fig. 5, providing a first substrate, wherein the first substrate includes a first bottom surface and a second bottom surface, a first top surface opposite to the first and second bottom surfaces, and a first connection surface connecting the first and second bottom surfaces, the first bottom surface and the second bottom surface have a height difference, the first bottom surface, the second bottom surface, and the first connection surface form a first zigzag step, and a first pad is disposed on the first connection surface; providing a second substrate, wherein the second substrate comprises a second top surface, a third bottom surface opposite to the second top surface and the third top surface, and a second connecting surface for connecting the second top surface and the third top surface, the second top surface and the third top surface have height difference, the second top surface, the third top surface and the second connecting surface form a second Z-shaped step, and a second bonding pad is arranged on the second connecting surface; wherein the first zigzag step matches the second zigzag step in shape;
referring to fig. 6, the first substrate and the second substrate are stacked, wherein a conductive adhesive layer is disposed on the first pad such that the first bottom surface is in contact with the second top surface and the second bottom surface is in contact with the third top surface, and then the first pad and the second pad are moved toward each other until the first pad is electrically connected to the second pad through the conductive adhesive layer.
Referring to fig. 7, a second chip is soldered to the second top surface of the second substrate, the second chip being located at the other side surface of the first substrate.
Referring to fig. 8, the first top surface of the first substrate has a third pad thereon, and the second top surface of the second substrate has an elastic connector thereon, the method further includes laminating the first substrate using the elastic connector, the elastic connector including a fixing portion inserted into a through hole of the second substrate and an elastic portion connecting the fixing portion, the elastic portion including a first end, a second end, and a connecting portion connecting the first end and the second end, the first end being fixed to the fixing portion, and the second end being laminated on the third pad. Then, a sealing layer is injection molded, the sealing layer sealing the first top surface of the first substrate, portions of the second top surface and the third top surface of the second substrate, the elastic connection member, the groove, the first and second chips. An array of external connection terminals is provided on the third top surface 12, which array of external connection terminals is exposed from the sealing layer.
Referring to fig. 9, as another embodiment, another substrate and a third substrate are disposed on the other side of the second substrate, the third substrate is formed identically to the first substrate, and has the same structure, the third bottom surface of the second substrate has a zigzag step, the shape of the zigzag step is identical to that of the second zigzag step, and the end of the second substrate may be a socket.
Finally, it should be noted that: it should be understood that the above examples are only for clearly illustrating the present invention and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of the invention may be made without departing from the scope of the invention.

Claims (8)

1. A substrate stack package structure comprising:
the first substrate comprises a first bottom surface, a second bottom surface, a first top surface and a first connecting surface, wherein the first top surface is opposite to the first bottom surface and the second bottom surface, the first connecting surface is connected with the first bottom surface and the second bottom surface, the first bottom surface and the second bottom surface have height difference, the first bottom surface, the second bottom surface and the first connecting surface form a first Z-shaped step, and a first bonding pad is arranged on the first connecting surface;
the second substrate comprises a second top surface, a third bottom surface opposite to the second top surface and the third top surface, and a second connecting surface for connecting the second top surface and the third top surface, wherein the second top surface and the third top surface have height difference, the second top surface, the third top surface and the second connecting surface form a second Z-shaped step, and a second bonding pad is arranged on the second connecting surface;
the method is characterized in that: the first Z-shaped step is matched with the second Z-shaped step in shape, the first bottom surface is contacted with the second top surface, the second bottom surface is contacted with the third top surface, and the first bonding pad is electrically connected with the second bonding pad through a conductive bonding layer;
the first substrate is provided with a first bonding pad on the first top surface, the second substrate is provided with an elastic connecting piece on the second top surface, the elastic connecting piece comprises a fixing part inserted into the through hole of the second substrate and an elastic part connected with the fixing part, the elastic part comprises a first end, a second end and a connecting part connected with the first end and the second end, the first end is fixed on the fixing part, and the second end is pressed on the first bonding pad.
2. The substrate stack package structure of claim 1, wherein: the third pad is electrically connected to the second substrate through the elastic connection member.
3. The substrate stack package structure of claim 1, wherein: the third bonding pad is a dummy bonding pad which does not play a role in electric conduction.
4. The substrate stack package structure of claim 1, wherein: the second bottom surface is provided with a groove, the groove penetrates through the first connecting surface and the first side surface of the first substrate, a first chip is arranged in the groove, and the first chip is electrically connected with the first substrate.
5. The substrate stack package structure of claim 4, wherein: a second chip is disposed on the second top surface of the second substrate, and at least a portion of the elastic connection member spans the second chip.
6. The substrate stack package structure of claim 5, wherein: the sealing layer seals the first top surface of the first substrate, portions of the second top surface and the third top surface of the second substrate, the elastic connection member, the groove, and the first and second chips.
7. The substrate stack package structure of claim 6, wherein: an array of external connection terminals is disposed on the third top surface, the array of external connection terminals being exposed from the encapsulant layer.
8. A substrate stack packaging method, comprising:
providing a first substrate, wherein the first substrate comprises a first bottom surface, a second bottom surface, a first top surface opposite to the first bottom surface and the second bottom surface, and a first connecting surface connecting the first bottom surface and the second bottom surface, the first bottom surface and the second bottom surface have height difference, the first bottom surface, the second bottom surface and the first connecting surface form a first zigzag step, and a first bonding pad is arranged on the first connecting surface;
providing a second substrate, wherein the second substrate comprises a second top surface, a third bottom surface opposite to the second top surface and the third top surface, and a second connecting surface for connecting the second top surface and the third top surface, the second top surface and the third top surface have height difference, the second top surface, the third top surface and the second connecting surface form a second Z-shaped step, and a second bonding pad is arranged on the second connecting surface; wherein the first zigzag step matches the second zigzag step in shape;
stacking the first substrate and the second substrate such that the first bottom surface is in contact with the second top surface, the second bottom surface is in contact with the third top surface, and the first pad is electrically connected to the second pad through a conductive adhesive layer;
the method comprises the steps of pressing the first substrate by using an elastic connecting piece, wherein the first top surface of the first substrate is provided with a third bonding pad, the second top surface of the second substrate is provided with an elastic connecting piece, the elastic connecting piece comprises a fixing part inserted into a through hole of the second substrate and an elastic part connected with the fixing part, the elastic part comprises a first end, a second end and a connecting part connected with the first end and the second end, the first end is fixed on the fixing part, and the second end is pressed on the third bonding pad.
CN201910667830.2A 2019-07-23 2019-07-23 Substrate stacking packaging structure and packaging method thereof Active CN110379775B (en)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0794670A (en) * 1993-09-22 1995-04-07 Toyota Autom Loom Works Ltd Hybrid integrated circuit device
JPH09127536A (en) * 1995-10-27 1997-05-16 Citizen Watch Co Ltd Liquid crystal display device
CN1742525A (en) * 2003-01-22 2006-03-01 日本电气株式会社 Method of attachment between circuit board device and circuit board
CN1767724A (en) * 2004-10-15 2006-05-03 李敏宰 Method of coupling PCB substrate
WO2018101051A1 (en) * 2016-12-01 2018-06-07 株式会社村田製作所 Multilayer substrate connecting body and transmission line device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0794670A (en) * 1993-09-22 1995-04-07 Toyota Autom Loom Works Ltd Hybrid integrated circuit device
JPH09127536A (en) * 1995-10-27 1997-05-16 Citizen Watch Co Ltd Liquid crystal display device
CN1742525A (en) * 2003-01-22 2006-03-01 日本电气株式会社 Method of attachment between circuit board device and circuit board
CN1767724A (en) * 2004-10-15 2006-05-03 李敏宰 Method of coupling PCB substrate
WO2018101051A1 (en) * 2016-12-01 2018-06-07 株式会社村田製作所 Multilayer substrate connecting body and transmission line device

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