CN110379715A - Transfer substrate - Google Patents
Transfer substrate Download PDFInfo
- Publication number
- CN110379715A CN110379715A CN201910554294.5A CN201910554294A CN110379715A CN 110379715 A CN110379715 A CN 110379715A CN 201910554294 A CN201910554294 A CN 201910554294A CN 110379715 A CN110379715 A CN 110379715A
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- CN
- China
- Prior art keywords
- substrate
- layer
- conductive layer
- aforementioned
- lamination
- Prior art date
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- Pending
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- 239000000758 substrate Substances 0.000 title claims abstract description 501
- 238000012546 transfer Methods 0.000 title claims abstract description 76
- 239000010410 layer Substances 0.000 claims abstract description 634
- 238000003475 lamination Methods 0.000 claims abstract description 199
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 59
- 239000002346 layers by function Substances 0.000 claims abstract description 58
- 239000004065 semiconductor Substances 0.000 claims description 100
- 238000000034 method Methods 0.000 claims description 94
- 230000008569 process Effects 0.000 claims description 76
- 239000000463 material Substances 0.000 claims description 49
- 239000010949 copper Substances 0.000 claims description 35
- 239000004020 conductor Substances 0.000 claims description 33
- 229910052802 copper Inorganic materials 0.000 claims description 22
- 239000000203 mixture Substances 0.000 claims description 21
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 18
- 239000007769 metal material Substances 0.000 claims description 14
- 239000002585 base Substances 0.000 claims description 11
- 239000003513 alkali Substances 0.000 claims description 10
- 239000011810 insulating material Substances 0.000 claims description 10
- 238000007740 vapor deposition Methods 0.000 claims description 8
- 235000007164 Oryza sativa Nutrition 0.000 claims description 5
- 238000000059 patterning Methods 0.000 claims description 5
- 235000009566 rice Nutrition 0.000 claims description 5
- 240000007594 Oryza sativa Species 0.000 claims 1
- 239000003245 coal Substances 0.000 claims 1
- 239000003989 dielectric material Substances 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 64
- 239000010408 film Substances 0.000 description 152
- 229920002120 photoresistant polymer Polymers 0.000 description 62
- 238000005530 etching Methods 0.000 description 60
- 239000011888 foil Substances 0.000 description 26
- 239000007787 solid Substances 0.000 description 25
- 238000010438 heat treatment Methods 0.000 description 24
- 238000002788 crimping Methods 0.000 description 22
- 239000007788 liquid Substances 0.000 description 21
- 238000004140 cleaning Methods 0.000 description 17
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 16
- 230000006870 function Effects 0.000 description 16
- 238000009825 accumulation Methods 0.000 description 13
- 239000011248 coating agent Substances 0.000 description 13
- 238000000576 coating method Methods 0.000 description 13
- 229910052751 metal Inorganic materials 0.000 description 13
- 239000002184 metal Substances 0.000 description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 12
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 12
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 12
- 230000035508 accumulation Effects 0.000 description 12
- 229910052782 aluminium Inorganic materials 0.000 description 12
- 239000011521 glass Substances 0.000 description 12
- 238000005229 chemical vapour deposition Methods 0.000 description 10
- 238000010276 construction Methods 0.000 description 10
- 230000005611 electricity Effects 0.000 description 10
- 238000004064 recycling Methods 0.000 description 10
- 239000011347 resin Substances 0.000 description 10
- 229920005989 resin Polymers 0.000 description 10
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 9
- 229910052742 iron Inorganic materials 0.000 description 8
- 238000012545 processing Methods 0.000 description 8
- 239000010409 thin film Substances 0.000 description 8
- 239000003990 capacitor Substances 0.000 description 7
- 239000010931 gold Substances 0.000 description 7
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 7
- 238000004544 sputter deposition Methods 0.000 description 7
- 230000008859 change Effects 0.000 description 6
- 239000011889 copper foil Substances 0.000 description 6
- 229910052593 corundum Inorganic materials 0.000 description 6
- 229910052738 indium Inorganic materials 0.000 description 6
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 6
- 238000001459 lithography Methods 0.000 description 6
- 239000012528 membrane Substances 0.000 description 6
- 229910052750 molybdenum Inorganic materials 0.000 description 6
- 238000001259 photo etching Methods 0.000 description 6
- 239000000047 product Substances 0.000 description 6
- 239000002994 raw material Substances 0.000 description 6
- 229910001845 yogo sapphire Inorganic materials 0.000 description 6
- 239000011787 zinc oxide Substances 0.000 description 6
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 5
- 238000007607 die coating method Methods 0.000 description 5
- 239000004744 fabric Substances 0.000 description 5
- 229910052733 gallium Inorganic materials 0.000 description 5
- 238000000227 grinding Methods 0.000 description 5
- 229920000139 polyethylene terephthalate Polymers 0.000 description 5
- 239000005020 polyethylene terephthalate Substances 0.000 description 5
- 239000007921 spray Substances 0.000 description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- 241000209094 Oryza Species 0.000 description 4
- 239000004698 Polyethylene Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- XTXRWKRVRITETP-UHFFFAOYSA-N Vinyl acetate Chemical compound CC(=O)OC=C XTXRWKRVRITETP-UHFFFAOYSA-N 0.000 description 4
- 238000013459 approach Methods 0.000 description 4
- 238000007772 electroless plating Methods 0.000 description 4
- 229910000040 hydrogen fluoride Inorganic materials 0.000 description 4
- 229920000573 polyethylene Polymers 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 239000010935 stainless steel Substances 0.000 description 4
- 229910001220 stainless steel Inorganic materials 0.000 description 4
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 3
- 238000000137 annealing Methods 0.000 description 3
- 238000000889 atomisation Methods 0.000 description 3
- 238000011161 development Methods 0.000 description 3
- 238000009820 dry lamination Methods 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 238000002161 passivation Methods 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- -1 polyethylene terephthalate Polymers 0.000 description 3
- 229920001721 polyimide Polymers 0.000 description 3
- 239000009719 polyimide resin Substances 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 229910052725 zinc Inorganic materials 0.000 description 3
- 239000011701 zinc Substances 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 239000005030 aluminium foil Substances 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 238000003490 calendering Methods 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 229920006026 co-polymeric resin Polymers 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000002305 electric material Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000011737 fluorine Substances 0.000 description 2
- 229910052731 fluorine Inorganic materials 0.000 description 2
- 238000009499 grossing Methods 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 239000011256 inorganic filler Substances 0.000 description 2
- 229910003475 inorganic filler Inorganic materials 0.000 description 2
- 238000009434 installation Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000013067 intermediate product Substances 0.000 description 2
- JEIPFZHSYJVQDO-UHFFFAOYSA-N iron(III) oxide Inorganic materials O=[Fe]O[Fe]=O JEIPFZHSYJVQDO-UHFFFAOYSA-N 0.000 description 2
- 239000003595 mist Substances 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229920000915 polyvinyl chloride Polymers 0.000 description 2
- 239000000565 sealant Substances 0.000 description 2
- 238000009751 slip forming Methods 0.000 description 2
- 239000002904 solvent Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000009489 vacuum treatment Methods 0.000 description 2
- 238000005406 washing Methods 0.000 description 2
- QTBSBXVTEAMEQO-UHFFFAOYSA-M Acetate Chemical compound CC([O-])=O QTBSBXVTEAMEQO-UHFFFAOYSA-M 0.000 description 1
- 239000004925 Acrylic resin Substances 0.000 description 1
- 229920000178 Acrylic resin Polymers 0.000 description 1
- 208000019901 Anxiety disease Diseases 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 239000005977 Ethylene Substances 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 239000004952 Polyamide Substances 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 208000029152 Small face Diseases 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 238000004026 adhesive bonding Methods 0.000 description 1
- 239000004840 adhesive resin Substances 0.000 description 1
- 229920006223 adhesive resin Polymers 0.000 description 1
- 230000036506 anxiety Effects 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 239000002041 carbon nanotube Substances 0.000 description 1
- 125000003178 carboxy group Chemical group [H]OC(*)=O 0.000 description 1
- 235000013339 cereals Nutrition 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- QNDQILQPPKQROV-UHFFFAOYSA-N dizinc Chemical compound [Zn]=[Zn] QNDQILQPPKQROV-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005868 electrolysis reaction Methods 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 230000001804 emulsifying effect Effects 0.000 description 1
- HDERJYVLTPVNRI-UHFFFAOYSA-N ethene;ethenyl acetate Chemical compound C=C.CC(=O)OC=C HDERJYVLTPVNRI-UHFFFAOYSA-N 0.000 description 1
- 239000005357 flat glass Substances 0.000 description 1
- 238000007667 floating Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 230000009477 glass transition Effects 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 230000002427 irreversible effect Effects 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 229910021404 metallic carbon Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 239000002105 nanoparticle Substances 0.000 description 1
- KYTZHLUVELPASH-UHFFFAOYSA-N naphthalene-1,2-dicarboxylic acid Chemical compound C1=CC=CC2=C(C(O)=O)C(C(=O)O)=CC=C21 KYTZHLUVELPASH-UHFFFAOYSA-N 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- SLIUAWYAILUBJU-UHFFFAOYSA-N pentacene Chemical compound C1=CC=CC2=CC3=CC4=CC5=CC=CC=C5C=C4C=C3C=C21 SLIUAWYAILUBJU-UHFFFAOYSA-N 0.000 description 1
- JQQSUOJIMKJQHS-UHFFFAOYSA-N pentaphene Chemical compound C1=CC=C2C=C3C4=CC5=CC=CC=C5C=C4C=CC3=CC2=C1 JQQSUOJIMKJQHS-UHFFFAOYSA-N 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229920003023 plastic Polymers 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920002647 polyamide Polymers 0.000 description 1
- 229920005668 polycarbonate resin Polymers 0.000 description 1
- 239000004431 polycarbonate resin Substances 0.000 description 1
- 229920001225 polyester resin Polymers 0.000 description 1
- 239000004645 polyester resin Substances 0.000 description 1
- 229920005990 polystyrene resin Polymers 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 238000010020 roller printing Methods 0.000 description 1
- 239000002195 soluble material Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
- 229920003002 synthetic resin Polymers 0.000 description 1
- 239000000057 synthetic resin Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- JBQYATWDVHIOAR-UHFFFAOYSA-N tellanylidenegermanium Chemical compound [Te]=[Ge] JBQYATWDVHIOAR-UHFFFAOYSA-N 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
- 238000010023 transfer printing Methods 0.000 description 1
- 230000032258 transport Effects 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
- 229920002554 vinyl polymer Polymers 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
- 230000037303 wrinkles Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
- H01L21/0275—Photolithographic processes using lasers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
- H05B33/00—Electroluminescent light sources
- H05B33/10—Apparatus or processes specially adapted to the manufacture of electroluminescent light sources
Abstract
The burden of electronic components fabrication dealer can be mitigated, and manufacture high precision electro subcomponent.After at least part lamination tectosome for constituting electronic component is formed on transfer substrate i.e. the 1st substrate, lamination tectosome (52) is transferred to the manufacturing method on the 2nd substrate (P2), have: step 1 is rapid, by in the 1st conductive layer (52a) of formation on the 1st substrate (P1), in forming functional layer (52b) on the 1st conductive layer (52a), in forming the 2nd conductive layer (52c) on functional layer (52b), to form lamination tectosome (52)；And second step, it is close to the 1st substrate (P1) temporarily with the 2nd substrate (P2) in such a way that the 2nd conductive layer (52c) is located at the 2nd side substrate (P2), lamination tectosome (52) is transferred to the 2nd substrate (P2).
Description
The application be the applying date be on August 24th, 2015, application No. is 201580045821.X, entitled " element
The divisional application of the patent application of manufacturing method and transfer substrate ".
Technical field
The present invention relates to be formed with constitute electronic component at least part of lamination tectosome transfer substrate, with by
It is transferred to by the lamination tectosome that will be formed on the transfer substrate and is transferred substrate to manufacture the element manufacturer of electronic component
Method.
Background technique
The forming method for having a kind of organic EL layer is disclosed in Japanese Unexamined Patent Publication 2006-302814 bulletin.Briefly describe it,
It is to form hole transporting layer in the 1st endless strap by rubbing method (spray regime etc.) first, by rubbing method (spray regime
Deng) in the 2nd endless strap formation luminescent layer, electron supplying layer is formed in the 3rd endless strap by rubbing method (spray regime etc.).
Then, it will be formed thereafter in the hole transporting layer that the plate shape substrates transfer supplied from supply side reel is formed in the 1st endless strap
It is transferred on hole transporting layer in the luminescent layer of the 2nd endless strap, then, will be formed in the electron supplying layer of the 3rd endless strap
It is transferred on luminescent layer, forms organic EL layer whereby.
Summary of the invention
However, the occasion of the electronic component such as manufacturing thin film transistor (TFT) comprising semiconductor element, in order to promote half
The performance or yield of conductor element make stability of characteristics, preferably form a film being easy to control the vacuum spaces such as film thickness, pass through
The transfer modes of the technology as recorded in Japanese Unexamined Patent Publication 2006-302814 bulletin are to be difficult to manufacture high-precision electronic component.
On the other hand, though being generally to be carried out on glass substrate to manufacture electronic component mostly, and by the electronic component of completion
The gimmick of other final substrates (such as flexible resin film or plastic plate) is transferred to from glass substrate, but under this situation, electronics member
The manufacturer of part is to form a film in vacuum space and the layer for constituting electronic component is formed in glass substrate, or according to electricity
The lamination construction of subcomponent is repeated development treatment, etching process, the CVD processing that photoetching is utilized, sputter processing etc. and makees
Final substrate is transferred to after electronic component, then by the electronic component of completion.Therefore, the manufacturer of electronic component, in addition to flower
Expense using the equipment of most manufacturing process that form a film to implement to be formed in the layer of electronic component construction on glass substrate come by
The fabrication of electronic components of completion is other than the manufacturing cost on glass substrate, it is necessary to spend the electronic component on glass substrate
Transfer the manufacturing cost (equipment) in (switching) to final substrate.Therefore be difficult to force down final electronic component (LCD mode or
Display panel, the touch panel etc. of organic EL mode) product price, it is very big to the burden of the manufacturer of electronic component.
1st aspect of the invention is a kind of manufacturing method, and at least part lamination for constituting electronic component is constructed
After body is formed on the 1st substrate, aforementioned lamination tectosome is transferred on the 2nd substrate, have: step 1 is rapid, by aforementioned
Conductive material is formed on 1 substrate and is formed by the 1st conductive layer, and insulating properties and semiconductor are formed on the 1st conductive layer of Yu Qianshu
An at least material is formed by functional layer, forms conductive material in Yu Qianshu functional layer and is formed by the 2nd conductive layer, to be formed
Aforementioned lamination tectosome；And second step, make aforementioned 1st base in such a way that aforementioned 2nd conductive layer is located at aforementioned 2nd substrate-side
Plate temporarily approaches or is close to aforementioned 2nd substrate, and aforementioned lamination tectosome is transferred to aforementioned 2nd substrate.
2nd aspect of the invention is a kind of transfer substrate, is to be transferred substrate transfer composition electronic component extremely
Few a part of lamination tectosome: it is formed with aforementioned lamination tectosome in the surface of preceding transfer substrate, aforementioned lamination tectosome is
With use conductive material to be formed on preceding transfer substrate the 1st conductive layer, use at least material of insulating properties and semiconductor
The 2nd conduction expecting the functional layer being formed on aforementioned 1st conductive layer and being formed in using conductive material in aforementioned functional layer
Layer is constituted.
3rd aspect of the invention is a kind of transfer substrate, is to include the electronic component of semiconductor element in formation
Transfer constitutes at least part lamination tectosome of aforementioned electronic element and supports aforementioned lamination tectosome on product substrate: aforementioned
Lamination tectosome, be from the surface side of aforementioned transfer substrate with use conductive material similarly or be formed selectively the 1st
Conductive layer, using insulating material or show the material of characteristic of semiconductor similarly or the functional layer that is formed selectively and
Similarly or the sequential lamination of the 2nd conductive layer that is formed selectively using conductive material.
4th aspect of the invention is a kind of manufacturing method, will be formed at least part product for constituting electronic component
1st substrate of layer tectosome is transferred on the 2nd substrate, and have: step 1 is rapid, is prepared aforementioned 1st substrate and is used as with conductive material
The 1st conductive layer formed forms the function of being formed with an at least material for insulating properties and semiconductor on the 1st conductive layer of Yu Qianshu
Layer, the 2nd conductive layer formed with conductive material is formed in Yu Qianshu functional layer, to form aforementioned lamination tectosome；And the 2nd
Step approaches aforementioned 1st substrate temporarily with aforementioned 2nd substrate in such a way that aforementioned 2nd conductive layer is located at aforementioned 2nd substrate-side
Or be close to, it will include that the aforementioned lamination tectosome of aforementioned 1st substrate is transferred to aforementioned 2nd substrate.
5th aspect of the invention is a kind of transfer substrate, is to be transferred substrate transfer composition electronic component extremely
Few a part of lamination tectosome, has: conductive foil, and the 1st conductive layer function is played using conductive material；Functional layer uses
An at least material for insulating properties and semiconductor is formed on aforementioned 1st conductive layer；And the 2nd conductive layer, use conductive material
It is formed in aforementioned functional layer.
Detailed description of the invention
Fig. 1 is the figure for showing the composition of the film formation device in substrate formation film of the 1st implementation form.
Fig. 2 is to show that the laminate will be formed in the 1st substrate of the 1st implementation form constructs to be transferred to the 2nd substrate
The figure of the composition of laminater.
Fig. 3 is the flow chart for showing step an example of bottom contact-type TFT manufacturing method.
Fig. 4 is the flow chart for showing step an example of bottom contact-type TFT manufacturing method.
Fig. 5 A~Fig. 5 F is to show the sectional view manufactured with the TFT of the manufacture of step shown in Fig. 3 and Fig. 4 Jing Guo state.
Fig. 6 A~Fig. 6 D is to show the sectional view manufactured with the TFT of the manufacture of step shown in Fig. 3 and Fig. 4 Jing Guo state.
Fig. 7 is the flow chart for showing step an example of top contact type TFT manufacturing method.
Fig. 8 is the flow chart for showing step an example of top contact type TFT manufacturing method.
Fig. 9 A~Fig. 9 D is to show the sectional view manufactured with the TFT of the manufacture of step shown in Fig. 7 and Fig. 8 Jing Guo state.
Figure 10 A~Figure 10 C is to show the sectional view manufactured with the TFT of the manufacture of step shown in Fig. 7 and Fig. 8 Jing Guo state.
Figure 11 is the process of step an example of the top contact type TFT manufacturing method for the variation 1 for showing the 1st implementation form
Figure.
Figure 12 is the process of step an example of the top contact type TFT manufacturing method for the variation 1 for showing the 1st implementation form
Figure.
Figure 13 A~Figure 13 F is to show the sectional view manufactured with the TFT of the manufacture of step shown in Figure 11 and Figure 12 Jing Guo state.
Figure 14 A~Figure 14 F is to show the sectional view manufactured with the TFT of the manufacture of step shown in Figure 11 and Figure 12 Jing Guo state.
Figure 15 is the sectional view in the variation 3 for show the 1st implementation form when the 2nd conductive layer is formed with alignment mark.
Figure 16 is the sectional view in the variation 3 for show the 1st implementation form when the 1st conductive layer is formed with window portion.
Figure 17 is the figure for showing the laminater in the variation 4 of the 1st implementation form and constituting.
Figure 18 is the figure for showing the laminater in the variation 5 of the 1st implementation form and constituting.
Figure 19 is the figure for showing pixel circuit an example of the organic el display in the 2nd implementation form.
Figure 20 is the figure for showing the specific configuration of pixel circuit shown in Figure 19.
Figure 21 is the flow chart of the step an example for the manufacturing method for showing pixel circuit shown in Figure 20.
Figure 22 is the flow chart of the step an example for the manufacturing method for showing pixel circuit shown in Figure 20.
The step of Figure 23 is step S101~step S105 with Figure 21 and be formed in the lamination tectosome on the 1st substrate
Sectional view.
The step of Figure 24 is step S106~step S111 with Figure 21 processes cuing open for the lamination tectosome of the 2nd conductive layer
Face figure.
Figure 25 is the top view of lamination tectosome shown in Figure 24.
Figure 26 is cuing open when the lamination tectosome for being formed in the 1st substrate with the step S113 of Figure 21 is transferred to 2 substrate
Face figure.
The step of Figure 27 is step S114~step S118 with Figure 22 processes cuing open for the lamination tectosome of the 1st conductive layer
Face figure.
Figure 28 is the top view of lamination tectosome shown in Figure 27.
The step of Figure 29 is step S119~step S122 with Figure 22 etches the function that bore portion is contacted shown in Figure 27
Sectional view when ergosphere.
Figure 30 is the step S123 with Figure 22 and the contact bore portion shown in Figure 29 when being formed with electroless plating contact
Sectional view.
Figure 31 is the figure for showing the variation of film formation device shown in FIG. 1.
Figure 32 is other configuration examples for showing the lamination tectosome of top contact type TFT and its transfer example of lamination tectosome
Figure.
Figure 33 is shown in the figure that the state of planarization film has been used when transferring shown in Figure 32.
Figure 34 A~Figure 34 D is the lamination shown when improveing the lamination tectosome of electronic component shown in Figure 23~Figure 30
The figure of the manufacturing process of tectosome.
Figure 35 is the figure for showing the vertical view configuration of lamination tectosome shown in Figure 34 D being formed on the 1st substrate and constituting.
Figure 36 A is to show that lamination tectosome shown in Figure 34 D that will be formed on the 1st substrate with transfer step is transferred to
The figure of the apperance at a moment after 2 substrates, Figure 36 B are displayed at the 1st conductive layer shown in Figure 36 A and are formed with gate electrode and drain electrode electricity
The extremely figure of equal apperance.
Figure 37 is the figure of an example for showing that the vertical view configuration of the TFT of Figure 36 B is constituted.
Symbol description:
10 film formation devices
12 supply side reels
14 recycling reels
16 process chambers
18 vacuum pumps
20 substrates
22 film forming use rotor
30 laminaters
32,34 supply side reel
36 crimping heating rollers
38,40 recycling reel
GR1, GR2, GR3, GR5, GR6 guide roll
50 peeling layers
52 lamination tectosomes
The 1st conductive layer of 52a
52b functional layer
The 2nd conductive layer of 52c
54 following layers
56 gold medals
58 semiconductor layers
The 1st substrate of P1
The 2nd substrate of P2
Specific embodiment
For the manufacturing method and transfer substrate of aspect of the invention, disclose preferable implementation form, referring to attached drawing in
It is described further below.In addition, aspect of the invention is not limited to these implementation forms, also comprising applying multiplicity change or improvement
Person.
[the 1st implementation form]
Fig. 1 is displayed at the figure of the composition of the film formation device 10 of substrate (hereinafter referred to as the 1st substrate) P1 formation film.1st
Substrate P 1 is the substrate (plate shape substrates) of the sheet of flexible (Flexible), and film formation device 10, which has to send out from by the 1st substrate, (to be turned
Print substrate, support substrate) P1 be rolled into reel supply side reel 12 supply the 1st substrate P 1, the 1st substrate P 1 of submitting is imposed
It is batched after film process by recycling reel 14 that is, the construction of so-called roll-to-roll mode.This 1st substrate P 1 has the 1st base
The belt like shape that the moving direction of plate P1 is longitudinal direction (strip), width direction is short side direction (short side).Film formation device 10
Be further equipped with: process chamber 16 attracts the air in process chamber 16 and makes in process chamber 16 as the vacuum pump 18 of vacuum, conduct
Substrate 20, guide roll GR1~GR3 and the film forming rotor 22 of film forming raw material (film raw material).
It is equipped with motor (not shown) in supply side reel 12 and recycling reel 14, by the motor rotation, from supply side reel 12
The 1st substrate P 1 is moved out, and batches the 1st substrate P 1 being sent by recycling reel 14.Also, film forming rotor 22, is one
Side rotation transports the 1st substrate P 1 on one side, and supports the part to form a film with periphery.Whereby, the 1st substrate P 1 is along film forming
With the outer peripheral surface (periphery) of rotor 22, back reel 14 is transported.Guide roll GR1~GR3 is transported to guide
The path of 1st substrate P 1.In addition, being equipped with motor (not shown) in film forming rotor 22, by the motor rotation, film forming is used
Rotor 22 rotates.
Film formation device 10, by vapor deposition or sputter in formation film (layer) in the 1st substrate P 1.By vapor deposition carry out at
The occasion of film is made to be gasified or be distilled with the methods of resistance heating, electron beam, high-frequency induction or laser heated substrate 20
Film forming raw material is attached to the 1st substrate P 1 to form film.Also, being the argon for making ionization in the occasion to form a film by sputter
Gas is collided in substrate 20 so that the molecule of substrate 20 is free, this free molecule is made to be attached to the 1st substrate P 1 to form film.It is
With recycling reel 14, which is batched, is formed with the 1st substrate P 1 of film (layer) in its surface.In addition, film formation device 10 also can be by
CVD (Chemical Vapor Deposition) forms film.Also, as film formation device 10, such as also can be using international
The device of No. 2013/176222 revealed misted deposition method of specification (atomization CVD method) is disclosed.
Such film formation device 10 can be used in the film of the continuous lamination number layer of the 1st substrate P 1.Also that is, by that will batch in table
Face is formed with the recycling reel 14 of the 1st layer of the 1st substrate P 1, uses as the supply side reel 12 of another film formation device 10, i.e.,
By aforementioned another film formation device 10 by new layer (the 2nd layer) on the 1st layer.Also, making in lamination by changing
For film forming raw material substrate 20 and also can lamination unlike material film.It, can be by thin film transistor (TFT) (TFT by this film of lamination；
Thin Film Transistor) etc. constitute at least part lamination tectosome of electronic component of semiconductor element and be formed in work
In the 1st substrate P 1 to support substrate.
For example, being by film formation device 10 in the 1st substrate P 1 in the occasion for forming bottom contact-type TFT (thin film transistor (TFT))
Surface sequentially film (the 1st conductive layer), the insulating materials (SiO of lamination metal based material (Cu, Al, Mo etc.) or ITO2、Al2O3
Deng) film (insulating layer), metal based material (Cu, Al, Mo etc.) film (the 2nd conductive layer), at least one of TFT will be constituted
Lamination tectosome is divided to be formed in the 1st substrate P 1.Also, in the occasion for forming top contact type TFT, then sequentially by film formation device 10
Film (the 1st conductive layer), the oxide semiconductor (IGZO, ZnO etc.), silicon (α-of lamination metal based material (Cu, Al, M o etc.)
) or the film (semiconductor layer) of organic semiconductor (pentacene) etc., insulating materials (SiO Si2、Al2O3Deng) film (insulation
Layer), the film (the 2nd conductive layer) of metal based material (Cu, Al, Mo etc.) or ITO, can will constitute the lamination tectosome of TFT whereby
It is formed in the 1st substrate P 1.
Be formed with the 1st substrate P 1 of lamination tectosome in the above described manner, be by rear detailed description photoetching (photo-patterning),
The non-real empty set processing unit of etching etc. is processed, and is processed into electrode layer, insulating layer, wiring with semiconductor element
The pattern form of layer or semiconductor layer etc..The lamination tectosome for being processed to the 1st substrate P 1 of such pattern form is transferred to
Substrate (hereinafter referred to as the 2nd substrate) P2.Fig. 2 is display will form and (support) the lamination tectosome transfer in the 1st substrate P 1
To the figure of the composition of the laminater 30 of the 2nd substrate P 2 (product substrate).This laminater 30 is, for example, below low with 100 degree
The lamination tectosome that temperature will be formed in the 1st substrate P 1 is transferred to the device of the low temperature thermal transfer mode of the 2nd substrate P 2.Laminater
30 have supply side reel 32,34, crimping heating roller 36, recycling reel 38,40 and guide roll GR5, GR6.
Supply side reel 32 is that the 1st substrate P 1 for being formed with lamination tectosome in surface is rolled into scroll-like person, by the 1st base
Back reel 38 moves out plate P1.Supply side reel 34 is will to transfer the 2nd substrate P 2 of lamination tectosome to be rolled into scroll-like person, by
Back reel 40 moves out 2 substrate Ps 2.In addition, the 2nd substrate P 2 is also the substrate of sheet flexible in the same manner as the 1st substrate P 1
(plate shape substrates are transferred substrate), the moving direction with the 2nd substrate P 2 are longitudinal direction (strip), and width direction is short side
The belt like shape in direction (billet).
Crimping heating roller 36 is to clamp the 1st substrate P 1 supplied from supply side reel 32 from two sides to supply with from supply side reel 34
The 2nd substrate P 2, both temporarily make to be close to crimp to carry out and also heated simultaneously.Whereby, the 1st substrate can be will be formed in
Lamination tectosome on P1 is transferred to the 2nd substrate P 2.Also that is, by (such as 100 degree or less of heating by crimping heating roller 36
Low temperature) and soften the lamination tectosome that is formed in the 1st substrate P 1, and will be soft by the crimping by crimping heating roller 36
The lamination tectosome in the 1st substrate P 1 changed is transferred to the 2nd substrate P 2.The surface of this crimping heating roller 36 is preferably using elasticity
Body arbitrarily sets the temperature and crimp force (plus-pressure) of crimping heating roller 36 depending on transfer materials.
Reel 38 is recycled, by what will be stripped by the 1st substrate P 1 that is, lamination tectosome for crimping heating roller 36
1st substrate P 1 is batched and is recycled.Recycle reel 40 by will pass through crimping heating roller 36 the 2nd substrate P 2 that is, transfer
There is the 2nd substrate P 2 (being formed with the 2nd substrate P 2 of lamination tectosome in surface) of lamination tectosome to batch and recycled.Guiding
Roller GR5, the 1st substrate P 1 supplied from supply side reel 32 is directed to crimping heating roller 36, guide roll GR6, to will be from
The 2nd substrate P 2 that supply side reel 34 is supplied is directed to crimping heating roller 36.
Herein, the 1st substrate P 1 and the 2nd substrate P 2 can be used and constituted such as the metal or alloy by resin film, stainless steel
Foil (foil) etc..As the material of resin film, such as polyvinyl resin, acrylic resin, polyester resin, ethylene-can be used
Vinyl acetate copolymer resin, Corvic, celluosic resin, polyamide, polyimide resin, polycarbonate resin
It include at least more than one person in rouge, polystyrene resin and vinyl acetate resin.Also, the 1st substrate P 1 and the 2nd substrate
The thickness or rigidity (yang type modulus) of P2, as long as will not be generated in the 1st substrate P 1 and the 2nd substrate P 2 because bending is led in conveying
The range of the folding line of cause or irreversible wrinkle.As the base material of the 1st substrate P 1 and the 2nd substrate P 2, thickness 25 μm~200
The films such as the PET (polyethylene terephthalate) and PEN (poly- naphthalenedicarboxylic acid) of μm degree are the typical case of preferable plate shape substrates.
1st substrate P 1 and the 2nd substrate P 2, due to being had in the processing to the 1st substrate P 1 and the application of the 2nd substrate P 2 sometimes
Heated situation, therefore the substrate of the preferably selected unobvious big material of thermal expansion coefficient.For example, can be by by inorganic filler
Resin film is mixed in inhibit thermal expansion coefficient.Inorganic filler can be such as titanium oxide, zinc oxide, aluminium oxide or silica.
Also, the 1st substrate P 1 and the 2nd substrate P 2, but with the individual layers of the very thin glass of 100 μm of degree of the thickness of the manufactures such as floating method,
But also there is the laminate of above-mentioned resin film, foil etc. in this very thin glass gluing.
In addition, as Fig. 1 film formation device 10, due to sometimes film forming when by the 1st substrate P 1 be heated to such as 100 DEG C~
300 DEG C of degree, therefore the base material of the 1st substrate P 1 is preferably the particularly good polyimide resin of heat resistance, very thin foliated glass or pole
Thin metal foil (copper foil, stainless steel foil, the aluminium foil that are rolled into ten several μm~hundreds of μm of thickness) etc..Furthermore the 1st substrate
P1, be not necessarily intended to be can coil into scroll-like strip plate shape substrates, but be also cut into cooperation electronic component to be manufactured (or
Its circuit substrate) size size monolithic plate shape substrates or glass substrate, metal plate.
Secondly, illustrating the manufacturing method of TFT.The construction of TFT, though bottom gate polar form construction and top-gated polar form structure can be divided into greatly
It makes, but in this 1st implementation form, is the manufacturing step for illustrating the TFT of bottom-gate construction, omits the TFT's of top gate configuration
The explanation of manufacturing step.Also, the TFT of bottom-gate construction is to say first due to being categorized into bottom contact-type and top contact type
After the manufacturing method of bright bottom contact-type TFT, besides the manufacturing method of bright top contact type TFT.
(manufacturing method of bottom contact-type TFT)
Fig. 3 and Fig. 4 is the process for showing step an example of manufacturing method of bottom contact-type TFT, Fig. 5 A~Fig. 5 F and Fig. 6 A
~Fig. 6 D is the sectional view shown by the manufacture of the TFT of the manufacture of step shown in Fig. 3 and Fig. 4 Jing Guo state.Firstly, Fig. 3's
Step S1, as shown in Figure 5A, in formation peeling layer 50 in the 1st substrate P 1.For example, can also be freed by by fluorine system material or alkali soluble
Film (being soluble material to alkali) is coated on the surface of the 1st substrate P 1 to form peeling layer 50, or photosensitive by that will be formed with
The desciccator diaphragm resist (DFR) of property alkali dissolving film forms peeling layer 50 laminated on the 1st substrate P 1.Film is freed as alkali soluble,
The mixture etc. of adhesive resin and carboxyl can be enumerated.This peeling layer 50 is lamination tectosome to be easy from the 1st substrate P 1
The layer of removing.
Then, as shown in Figure 5 B, in formation lamination tectosome 52 in the 1st substrate P 1 (step 1 is rapid).This lamination tectosome
52, it is that (Cu, Al, Mo, Au's etc. leads by the metal based material that is piled up in the 1st substrate P 1 (on peeling layer 50) with given thickness
Electric material) or ITO (conductive material) film (the 1st conductive layer) 52a, be piled up on the 1st conductive layer 52a with given thickness
Insulating materials (SiO2、Al2O3Deng insulating material) film (functional layer) 52b, functional layer is piled up in given thickness
(the 2nd is conductive for the film of metal based material (conductive material of Cu, Al, Mo, Au etc.) or ITO (conductive material) on 52b
Layer) 52c constituted.In addition, in the 1st conductive layer 52a and the 2nd conductive layer using copper (Cu) as composition lamination tectosome 52
When the material of 52c, the material of the 1st substrate P 1 also uses copper (Cu), so that coefficient of thermal expansion is consistent.
Therefore first in step S2, in formation (accumulation) the 1st conductive layer 52a in the 1st substrate P 1 (peeling layer 50).Then,
In step S3, in forming (accumulation) insulating layer that is, functional layer 52b on the 1st conductive layer 52a, (accumulation) the is re-formed in step S4
2 conductive layer 52c.Whereby, in formation lamination tectosome 52 in the 1st substrate P 1.This 1st conductive layer 52a, functional layer 52b and the 2nd
Conductive layer 52c is continuously formed by the film formation device 10 such as above-mentioned Fig. 1 is used in the 1st substrate P 1.In addition, the 1st leads
Electric layer 52a is matching as the electrode layer of source electrode and drain electrode and source electrode and the incidental wiring of drain electrode
Line layer and function.Also, the 2nd conductive layer 52c, is the electrode layer and the incidental wiring of gate electrode as gate electrode
Wiring layer and function.Herein, in order to keep the electrical characteristic (degree of excursion, ON/OFF ratio, leakage current etc.) as TFT good
It is good, the 1st conductive layer 52a and the interface of functional layer 52b or the interface of functional layer 52b and the 2nd conductive layer 52c, preferably with ultra micro
Rice grade below is flattened.Therefore, the surface of 50 side of peeling layer of the 1st substrate P 1 is also preferably below etc. with ultra micro rice
Grade is flattened.
Thereafter, it to the 1st substrate P 1 for being formed with lamination tectosome 52, imposes and photolithographic etching process is utilized, and such as
Shown in Fig. 5 C, form gate electrode and its incidental wiring in the 2nd conductive layer 52c (step 1 is rapid).In addition, only table in Fig. 5 C
Show gate electrode.
It is known techniques since this photolithographic etching process is utilized, it is briefly described, in step S5, in the 2nd
Photoresist layer is formed on conductive layer 52c.The formation of photoresist layer, be by by liquid resist in a manner of roller printing, spin coating mode, spray
The progress such as mode is blown, or the photoresist layer of desciccator diaphragm resist (DFR) can simply be implemented on the 2nd conductive layer 52c.
Then, in step S6, ultraviolet exposure predetermined pattern (gate electrode and its incidental wiring are used to photoresist layer is formed by
Deng pattern), developed in step S7 and (the 1st substrate P 1 made to be dipped in the developer solution of TMAH etc.), removed whereby by ultraviolet light
The photoresist layer of the part of exposure.Whereby, predetermined pattern (resist picture) is formed in photoresist layer.Secondly, washing in the 1st substrate P 1
Only, the step S8 after dry is dipped in corrosive liquid (such as oxidation two by the 1st substrate P 1 that will be formed with lamination tectosome 52
Iron), etching process of the photoresist layer as exposure mask that will be formed with predetermined pattern is imposed, and grid electricity is formed in the 2nd conductive layer 52c
Pole and its incidental wiring etc..Then, in step S9, removing is located at the photoresist layer on the 2nd conductive layer 52c, carries out the 1st substrate
P1's cleans.Whereby, lamination tectosome 52 as shown in Figure 5 C is made.In addition, cleaning for the 1st substrate P 1, also can be used NaOH
Alkali cleanings net liquid is waited to clean.
Then, in step S10, as shown in Figure 5 D, by the surface side for the 1st substrate P 1 for being formed with lamination tectosome 52
(52 side of lamination tectosome) is coated with solid and forms following layer 54.This following layer 54 is to make to be formed in the 1st substrate P 1
Lamination tectosome 52 be easy transfer (then) in the 2nd substrate P.As this solid, such as dry lamination also can be used to use
Solid, can luminous energy quantitative response to ultraviolet light and harden solid from the UV (ultraviolet light) that liquid variation is solid or heat is hard
Change solid.It is using dry lamination solid in the 1st implementation form.
Then, in the occasion of dry lamination solid, be in such a way that the 2nd conductive layer 52c is located at 2 side of the 2nd substrate P,
So that the 1st substrate P 1 is temporarily approached or is close to the 2nd substrate P 2, and will be formed in 52 turns of lamination tectosome in the 1st substrate P 1
It prints to the 2nd substrate P 2 (second step).This transfer, is transferred by the laminater 30 of such as above-mentioned Fig. 2.Also that is, peeling layer
50, lamination tectosome 52 and following layer 54, by by the 1st substrate P 1 from 1 surface side of the 1st substrate P according to aforementioned sequence lamination
The supply side reel 32 that scroll-like person is rolled into as laminater 30 uses, and can will be formed in the lamination tectosome of the 1st substrate P 1
52 are transferred to the 2nd substrate P 2.At this point, peeling layer 50 is not transferred to 2 side of the 2nd substrate P and still remains on 1 side of the 1st substrate P.
It is described in detail, first as shown in fig. 5e, makes the following layer 54 being formed on lamination tectosome 52 then in the 2nd base
Lamination tectosome 52 is removed into (step from the 1st substrate P 1 by peeling layer 50 as illustrated in figure 5f in the surface (step S11) of plate P2
S12).Whereby, the lamination tectosome 52 in the 1st substrate P 1 is transferred to the 2nd substrate P 2.By this transfer, lamination tectosome 52
It is formed in the 2nd substrate P 2 with the state of reversion.Also that is, constitute the 2nd conductive layer 52c of lamination tectosome 52, functional layer 52b,
And the 1st conductive layer 52a from the surface side of the 2nd substrate P 2 according to aforementioned sequence in the 2nd substrate P 2, the 1st conductive layer 52a dew
Out.Reel 40 is recovered transferred with the 2nd substrate P 2 of lamination tectosome 52 and is batched by laminater 30.In addition, removing
Layer 50 has been stripped and has been transferred to the occasion of 2 side of the 2nd substrate P from the 1st substrate P 1, is to remove peeling layer 50 and carry out the 2nd substrate
P2's cleans.Cleaning for 2nd substrate P 2, also the alkali cleanings such as NaOH net liquid can be used to clean.Peeling layer 50 due to be it is soluble, because
This can come to remove from the 1st conductive layer 52a by solvent.
Then, recycling reel 40 is used as feed rolls, the 2nd substrate P 2 moved out from this feed rolls is imposed and is utilized
Photolithographic etching process, and it is as shown in Figure 6A, source electrode and drain electrode and source electrode are formed in the 1st conductive layer 52a
And the incidental wiring of drain electrode (step 4 is rapid).In addition, only indicating source electrode and drain electrode in Fig. 6 A.
Simple declaration is by being utilized the formation of source electrode that photolithographic etching process carries out etc., firstly, Fig. 4's
Step S13 forms photoresist layer in the surface side (the 1st side conductive layer 52a) of the 2nd substrate P 2.Photoresist layer as with illustrated by step S5,
It is to be formed by the transfer of desciccator diaphragm resist (DFR) or the coating etc. of liquid resist.Then, in step S14, purple is used
Outside line exposes predetermined pattern (pattern of source electrode and drain electrode and source electrode and the incidental wiring of drain electrode etc.)
Light develops in being formed by photoresist layer in step S15.Whereby, predetermined pattern is formed in photoresist layer.Secondly, in step
S16 is impregnated in corrosive liquid (such as aoxidize two iron etc.) by the 2nd substrate P 2 that will be formed with lamination tectosome 52, will be formed with
The photoresist layer of predetermined pattern imposes etching process as exposure mask, to form source electrode and drain electrode in the 1st conductive layer 52a
Deng.Then, in step S17, removing is located at the photoresist layer on the 1st conductive layer 52a, carries out cleaning for the 2nd substrate P 2.Whereby, it makes
Obtain the lamination tectosome 52 such as Fig. 6 A.
Source electrode and drain electrode, it is necessary to the grid further below of functional layer (insulating layer) 52b of pole below nearby
Pole electrode (the 2nd conductive layer 52c) is critically aligned (overlapping).Therefore being exposed used in the step of exposure of step S14
Device (drawing apparatus) has in the forming step such as the gate electrode of step S5~S9 in Fig. 3, by gate electrode with by
The alignment mark that the 2nd conductive layer 52c in 1st substrate P 1 is formed passes through functional layer (insulating layer) 52b or directly optical detection
Alignment sensor with according to the detection position of the label critically adjust and stay in step S14 expose predetermined pattern (source electrode
The pattern of electrode, drain electrode and incidental wiring etc.) corresponding ultraviolet light and the 2nd substrate P 2 relative positional relationship
Function.
Then, in step S18, as shown in Figure 6B, source electrode and drain electrode to the 1st conductive layer 52a carry out Au and set
Change plating processing (step 4 is rapid).The Au (gold) 56 being coated with by this displacement plating processing, is to reduce source electrode and leakage
The impedance (improving electronics degree of excursion) of the contact interface of pole electrode and aftermentioned semiconductor layer.
Thereafter, in step S19, as shown in Figure 6 C, semiconductor is formed (on the 1st conductive layer 52a) on the 2nd substrate P 2
The film (semiconductor layer) 58 (step 4 is rapid) of (IGZO, ZnO etc.).Then, it imposes and photolithographic etching process is utilized, such as scheme
Shown in 6D, process semiconductor layer 5 (step 4 is rapid).Also that is, in step S20, in forming photoresist layer on semiconductor layer 58, in step
Predetermined pattern is formed in using ultraviolet light and is formed by photoresist layer by S21, is developed in step S22.When exposing herein,
Alignment mark is detected by alignment sensor, to answer remaining part critically across drain electrode and source electrode electricity in semiconductor layer 58
Ultraviolet irradiation position is precisely oriented by the mode between pole.
Whereby, predetermined pattern is formed in photoresist layer.Secondly, being impregnated in corrosive liquid by by the 2nd substrate P 2 in step S23
The photoresist layer for being formed with predetermined pattern is imposed etching process as exposure mask by (such as hydrogen fluoride etc.), to process semiconductor layer 58.
Whereby, as shown in Figure 6 D, residual is located at least in semiconductor layer 58 between source electrode and drain electrode, and can except removal this with
Outer unwanted semiconductor layer 58.Thereafter, in step S24, removing is located at the photoresist layer on semiconductor layer 58, carries out the 2nd base
Plate P2's cleans.By via such step, in forming bottom contact-type TFT as shown in Figure 6 D in the 2nd substrate P 2.In addition, half
Conductor layer 58 also can be organic semiconductor or oxide semiconductor.Under this situation, it can be also patterned in advance by resist,
The fluent material of semiconductor is selectively coated on comprising making behind the region of (channel part) between source electrode and drain electrode
Semiconductor layer 58 is formed between source electrode and drain electrode with stripping method.
In step described above, also at least step of Fig. 3 S1~step can be carried out by the supply dealer of the 1st substrate P 1
The step of S4 (Fig. 5 A and Fig. 5 B), the step after supplying the step of dealer carries out then are carried out by the manufacturer of electronic component.
For example, can be by supplying the step of dealer carries out step S1~step S4 of Fig. 3, manufacturer carries out step S5~Fig. 4's of Fig. 3
The step of step S24 (Fig. 5 C~Fig. 6 D).In this implementation form, via Fig. 3 step S1~step S4 the step of it is manufactured
1st substrate P 1 (the supporting substrate of lamination tectosome 52) is to be rolled into scroll-like state as intermediate products or with both
The state of measured length cutting slabbing is supplied to the manufacturer of electronic component.
As above, for example, the step of carrying out step S1~step S4 of Fig. 3 by the supply dealer of the 1st substrate P 1 is (required
The step of using vacuum treatment installation), and the step of step S5~Fig. 4 of Fig. 3 is carried out by the manufacturer of TFT (electronic component)
The step of S24 (the step of not needing vacuum treatment installation), can mitigate manufacturer's burden of electronic component whereby, can be simply
Manufacture high-precision electronic component.Also that is, in order to manufacture high-precision electronic component, though it must will constitute electronic component at least
A part of lamination tectosome 52 is formed a film in vacuum space, but since the manufacturer of electronic component is not required to carry out in vacuum
The film forming in space, therefore can reduce the burden of the manufacturer of electronic component.Also, as long as the manufacturer due to electronic component makes
Electronic component is formed with the 1st substrate P 1 for being formed with lamination tectosome 52, therefore can arbitrarily determine electronic component
Number and configuration constitute the configuration of thin film transistor (TFT) of electronic component etc. or setting for wiring, bus bar etc. to manufacture electronic component
The freedom degree of meter is promoted.Even also, not possessing majority vacuum evaporation necessary to all layers of film forming for constituting electronic component
The manufacturer of device or apparatus for coating or sputtering unit etc., can also be easily manufactured high performance electronic component.
(manufacturing method of top contact type TFT)
Fig. 7 and Fig. 8 is the process for showing step an example of manufacturing method of top contact type TFT, Fig. 9 A~Fig. 9 D and Figure 10 A
~Figure 10 C is the sectional view shown by the manufacture of the TFT of the manufacture of step shown in Fig. 7 and Fig. 8 Jing Guo state.Firstly, Fig. 7's
Step S31, as shown in Figure 9 A, in formation peeling layer 70 in the 1st substrate P 1.This step is identical as the step S1 of Fig. 3.
Then, as shown in Figure 9 B, in formation lamination tectosome 72 in the 1st substrate P 1 (step 1 is rapid).This lamination tectosome
72, it is that (Cu, Al, Mo, Au's etc. leads by the metal based material that is piled up in the 1st substrate P 1 (on peeling layer 70) with given thickness
Electric material) or ITO (conductive material) film (the 1st conductive layer) 72a, be piled up on the 1st conductive layer 72a with given thickness
The semiconductor material of characteristic of semiconductor (IGZO, ZnO, silicon, thick pentaphene etc. show) film (semiconductor layer) 72b1, with set
Thickness is piled up in the insulating materials (SiO on semiconductor layer 72b12、Al2O3Deng insulating material) film (insulating layer)
72b2, the metal based material (conductive material of Cu, Al, Mo, Au etc.) being piled up in given thickness on insulating layer 72b2 or ITO
Film (the 2nd conductive layer) 72c of (conductive material) is constituted.Semiconductor layer 72b1 and insulating layer 72b2 constitutes functional layer 72b.This
Outside, herein also similarly, the heating (100~300 DEG C) when film forming is contemplated in the base material of the 1st substrate P 1, and preferably heat resistance is good
Polyimide resin, very thin sheet glass or very thin metal foil (be rolled into ten several μm~hundreds of μm of thickness copper foil,
Stainless steel foil, aluminium foil) etc..Also, peeling layer 70 can be used with peeling layer 50 illustrated by previous Fig. 3 to Fig. 6 A~Fig. 6 D equally
Ground fluorine system material or alkali soluble free film, using inorganic material as the remover of substrate, silicon remover etc..
Therefore first in step S32, in formation (accumulation) the 1st conductive layer 72a in the 1st substrate P 1 (peeling layer 70).It connects
, in step S33, in forming (accumulation) semiconductor layer 72b1 on the 1st conductive layer 72a, in step S34, it is exhausted to re-form (accumulation)
Edge layer 72b2 forms functional layer 72b whereby.Thereafter, in step S35, in formation (accumulation) the 2nd conductive layer on functional layer 72b
72c.Whereby, in formation lamination tectosome 72 in the 1st substrate P 1.This 1st conductive layer 72a, semiconductor layer 72b1, insulating layer
72b2 and the 2nd conductive layer 72c is consecutively formed in the 1st substrate P 1 by above-mentioned film formation device 10 is used.In addition, the
1 conductive layer 72a is as the electrode layer of source electrode and drain electrode and source electrode and the incidental wiring of drain electrode
Wiring layer and function.Also, the 2nd conductive layer 72c, is the electrode layer and the incidental wiring of gate electrode as gate electrode
Wiring layer and function.In above composition, the 1st substrate P 1 or the 1st conductive layer 72a using metal based material (such as
Cu occasion), when forming semiconductor layer 72b1 on the 1st conductive layer 72a, due to that can be heated to much higher than resin films such as PET
The temperature (such as 200 DEG C or more) of glass transition temperature, therefore organic semiconducting materials or oxide semiconductor material etc. are determined
It can carry out to (crystallization), be promoted while electrical characteristic (such as degree of excursion) great-jump-forward of TFT can be made well.In turn, first near
The interface of few 1st conductive layer 72a and semiconductor layer 72b1 and the interface of insulating layer 72b2 and the 2nd conductive layer 72c are respectively with ultra micro
Rice grade below is planarized, and the promotion of the electrical characteristic of TFT is so also facilitated.
Thereafter, it to the 1st substrate P 1 for being formed with lamination tectosome 72, imposes and photolithographic etching process is utilized, and such as
Shown in Fig. 9 C, form gate electrode and its incidental wiring in the 2nd conductive layer 72c (step 1 is rapid).In addition, only being shown in Fig. 9 C
Show gate electrode.
This photolithographic etching process is utilized in simple declaration, first in step S36, in forming light on the 2nd conductive layer 72c
Resistance layer.Photoresist layer, as illustrated by the step S5 with Fig. 3, by the transfer of desciccator diaphragm resist or the coating etc. of resist liquid and
It is formed.Then, it in step S37, (gate electrode and its is attached to photoresist layer is formed by using ultraviolet exposure predetermined pattern
Wiring etc. pattern), developed in step S38 and (the 1st substrate P 1 made to be dipped in the developer solution of TMAH etc.).Whereby in photoresist layer
Form predetermined pattern.Secondly, being dipped in corrosive liquid (example by the 1st substrate P 1 that will be formed with lamination tectosome 72 in step S39
Such as aoxidize two iron), etching process of the photoresist layer as exposure mask that will be formed with predetermined pattern is imposed, and in the 2nd conductive layer 72c shape
At gate electrode etc..Then, in step S40, removing is located at the photoresist layer on the 2nd conductive layer 72c, carries out washing for the 1st substrate P 1
Only.Whereby, lamination tectosome 72 as shown in Figure 9 C is made.In addition, cleaning for the 1st substrate P 1, also can be used the alkali cleanings such as NaOH
Net liquid is cleaned.
Then, in the step S41 of Fig. 8, by the surface side (lamination for the 1st substrate P 1 for being formed with lamination tectosome 72
72 side of tectosome) it is coated with solid and forms following layer 54.
Secondly, making the 1st substrate P 1 and the 2nd substrate P 2 temporarily in such a way that the 2nd conductive layer 72c is located at 2 side of the 2nd substrate P
Close or abutting, and the lamination tectosome 72 that will be formed in the 1st substrate P 1 is transferred to the 2nd substrate P 2 (second step).This turn
Print, is transferred by such as above-mentioned laminater 30.It also that is, will be from 1 surface side of the 1st substrate P according to peeling layer 70, lamination structure
The 1st substrate P 1 of the sequential lamination of body 72 and following layer 74 is made to be rolled into the confession that scroll-like state is set to laminater 30
Answer reel 32.By laminater 30, the lamination tectosome 72 that can will be formed in the 1st substrate P 1 is transferred to the 2nd substrate P 2.This
When, to make lamination tectosome 72 easily not be transferred to 2 side of the 2nd substrate P from the peeling layer 70 that the 1st substrate P 1 strips and still residual
It stays in 1 side of the 1st substrate P.
First as shown in Figure 10 A, make the following layer 74 being formed on lamination tectosome 72 then in the surface of the 2nd substrate P 2
Lamination tectosome 72 is removed (step S43) from the 1st substrate P 1 by peeling layer 70 as shown in Figure 10 B by (step S42).By
This, the lamination tectosome 72 in the 1st substrate P 1 is transferred to the 2nd substrate P 2.By this transfer, lamination tectosome 72 is with reversion
State is formed in the 2nd substrate P 2.Also that is, constituting the 2nd conductive layer 72c, the functional layer 72b and the 1st conduction of lamination tectosome 72
Layer 72a from the surface side of the 2nd substrate P 2 according to aforementioned sequence in the 2nd substrate P 2, the 1st conductive layer 72a exposes.By lamination
Device 30 and be recovered reel 40 transferred with the 2nd substrate P 2 of lamination tectosome 72 and batch.In addition, in peeling layer 70 from the 1st
Substrate P 1 is stripped and is transferred to the occasion of 2 side of the 2nd substrate P, is to remove peeling layer 70 and carry out cleaning for the 2nd substrate P 2.Stripping
Absciss layer 70 can come to remove from the 1st conductive layer 72a by solvent due to being solubility.
Then, recycling reel 40 is used as feed rolls, the 2nd substrate P 2 moved out from this feed rolls is imposed and is utilized
Photolithographic etching process, and as illustrated in figure 10 c, source electrode and drain electrode and source electrode are formed in the 1st conductive layer 72a
And the incidental wiring of drain electrode (step 4 is rapid).In addition, only indicating source electrode and drain electrode in Figure 10 C.
Simple declaration is by being utilized the formation of source electrode that photolithographic etching process carries out etc., firstly, in step
S44 forms photoresist layer in the surface side (the 1st side conductive layer 72a) of the 2nd substrate P 2.Photoresist layer is as described in the step S5 with Fig. 3
It is bright, it is to be formed by desciccator diaphragm resist or coating etc..Then, in step S45, using ultraviolet light by predetermined pattern (source electrode
The pattern of electrode and drain electrode and source electrode and the incidental wiring of drain electrode etc.) it is exposed to and is formed by photoresist layer,
Develop in step S46.Whereby, predetermined pattern is formed in photoresist layer.Secondly, in step S47, by lamination structure will be formed with
The 2nd substrate P 2 for making body 72 is impregnated in corrosive liquid (such as aoxidize two iron etc.), using the photoresist layer for being formed with predetermined pattern as covering
Film imposes etching process, to form source electrode and drain electrode etc. in the 1st conductive layer 72a.Then, in step S48, position is removed
Photoresist layer on the 1st conductive layer 72a carries out cleaning for the 2nd substrate P 2.By via such step, in shape in the 2nd substrate P 2
At top contact type TFT as illustrated in figure 10 c.In addition, cleaning for the 2nd substrate P 2, also the alkali cleanings such as NaOH net liquid can be used to clean.
In step described above, also at least step of Fig. 7 S31~step can be carried out by the supply dealer of the 1st substrate P 1
The step of rapid S35 (Fig. 9 A and Fig. 9 B), supply dealer carry out the step of after step then by the manufacturer of electronic component into
Row.For example, can be by supplying the step of dealer carries out step S31~step S35 of Fig. 7, manufacturer carries out the step S36 of Fig. 7
The step of step S48 of~Fig. 8 (Fig. 9 C~Figure 10 C).
As above, for example, the step of carrying out step S31~step S35 of Fig. 7 by the supply dealer of the 1st substrate P 1, and
The step of carrying out the step S48 of step S36~Fig. 8 of Fig. 7 by the manufacturer of TFT (electronic component), can mitigate electronics whereby
The manufacturer of element bears, and can simply manufacture high-precision electronic component.Also that is, in order to manufacture high-precision electronics member
Part, though at least part lamination tectosome 72 for constituting electronic component must be formed a film in vacuum space, due to electricity
The manufacturer of subcomponent is not required to carry out the film forming in vacuum space, therefore can reduce the burden of the manufacturer of electronic component.
Also, as long as the manufacturer due to electronic component forms electronic component using the 1st substrate P 1 for being formed with lamination tectosome 72
, therefore can determine number and the configuration of electronic component arbitrarily to manufacture electronic component, the film for constituting electronic component is brilliant
The freedom degree of the design of the configuration or wiring of body pipe etc., bus bar etc. is promoted.Even also, not possessing the institute for constituting electronic component
There is the manufacturer of majority vacuum deposition apparatus or apparatus for coating or sputtering unit necessary to the film forming of layer etc., can also be easy
Ground manufactures high performance electronic component.In this implementation form also similarly, via the step S31 of Fig. 7~step S35 the step of institute
1st substrate P 1 (the supporting substrate of lamination tectosome 72) of manufacture, is to be rolled into scroll-like state as intermediate products
Or the manufacturer of electronic component is supplied to the state of certain length cutting slabbing.
[variation of the 1st implementation form]
Above-mentioned 1st implementation form also can be variation below.
(variation 1)
In variation 1, about the manufacture of top contact type TFT, be on one side impose be utilized photolithographic etching process, while
Form lamination tectosome.Figure 11 and Figure 12 is the stream for showing step an example of the manufacturing method of top contact type TFT of this variation 1
Cheng Tu, Figure 13 A~Figure 13 F and Figure 14 A~Figure 14 F are the manufactures for showing the TFT by the manufacture of step shown in Figure 11 and Figure 12
By the sectional view of state.Firstly, in the step S61 of Figure 11, as shown in FIG. 13A, in formation peeling layer 80 in the 1st substrate P 1.
The forming step of this peeling layer 80 is identical as the step S1 of Fig. 3.
Secondly, in step S62, as shown in Figure 13 B, in being formed in the 1st substrate P 1 (on peeling layer 80) with given thickness
Insulating materials (the SiO of accumulation2、Al2O3Deng) film (insulating layer) 82.This insulating layer 82, by using above-mentioned film formation device
10 and be formed in the 1st substrate P 1.This insulating layer 82 has the function as passivation (passivation), can also have conduct concurrently
The function of etch stop part.
Then, in step S63, as shown in fig. 13 c, in the 1st substrate P 1 (on insulating layer 82) formed with given thickness
Film (the 1st conductive layer) 84a of the metal based material (conductive material of Cu, Al, Mo etc.) of accumulation (step 1 is rapid).This 1st leads
Electric layer 84a is matching as the electrode layer of source electrode and drain electrode and source electrode and the incidental wiring of drain electrode
Line layer and function.This 1st conductive layer 84a is formed in the 1st substrate P 1 by above-mentioned film formation device 10 is used.
Thereafter, it imposes and photolithographic etching process is utilized, and as illustrated in figure 13d, source electrode is formed in the 1st conductive layer 84a
Electrode and drain electrode and source electrode and the incidental wiring of drain electrode (step 1 is rapid).At this point, by also as etching gear
The insulating layer 82 that stop member functions, prevents the etching of peeling layer 80.In addition, only indicating source electrode and drain electrode electricity in Figure 13 D
Pole.
Simple declaration is by being utilized the formation of source electrode that photolithographic etching process carries out etc., firstly, in step
S64, in forming photoresist layer on the 1st conductive layer 84a.Photoresist layer is by desciccator diaphragm resist as illustrated by the step S5 with Fig. 3
Or coating etc. and formed.Then, in step S65, using ultraviolet light, by predetermined pattern, (source electrode and drain electrode and source electrode are electric
The pattern of pole and the incidental wiring of drain electrode etc.) it is exposed to and is formed by photoresist layer, develop in step S66.Whereby,
Predetermined pattern is formed in photoresist layer.Secondly, being impregnated in step S67 by the 1st substrate P 1 that will be formed with the 1st conductive layer 84a
Corrosive liquid (such as aoxidize two iron etc.), the photoresist layer for being formed with predetermined pattern is imposed into etching process as exposure mask, to lead in the 1st
Electric layer 84a forms source electrode and drain electrode etc..Then, in step S68, removing is located at the photoresist on the 1st conductive layer 84a
Layer carries out cleaning for the 1st substrate P 1.
Then, it in step S69, as shown in figure 13e, is formed on the 1st substrate P 1 (on the 1st conductive layer 84a) with both
Determine film (semiconductor layer) 84b1 of the semiconductor (IGZO, ZnO etc.) of thickness accumulation (step 1 is rapid).This semiconductor layer 84b1, by
It is formed in the 1st substrate P 1 by using above-mentioned film formation device 10.Photolithographic etching process is utilized secondly, imposing, such as
Shown in Figure 13 F, process semiconductor layer 84b1 (step 1 is rapid).Also that is, in step S70, in forming photoresist on semiconductor layer 84b1
Layer.Photoresist layer as illustrated by the step S5 with Fig. 3, is formed by desciccator diaphragm resist or coating etc..Then, in step
Predetermined pattern is exposed to using ultraviolet light and is formed by photoresist layer by S71, is developed in step S72.Whereby, in photoresist layer
Form predetermined pattern.Secondly, being impregnated in corrosive liquid (such as hydrogen fluoride etc.) in step S73 by by the 1st substrate P 1, being formed
There is the photoresist layer of predetermined pattern to impose etching process as exposure mask, to process semiconductor layer 84b1.Whereby, as shown in Figure 13 F, residual
The semiconductor layer 84b1 being located at least between source electrode and drain electrode is stayed, and can remove in addition to this unwanted partly leads
Body layer 84b1.Then, in step S74, stripping resistance layer carries out cleaning for the 1st substrate P 1.
Thereafter, in the step S75 of Figure 12, as shown in Figure 14 A, in the surface side (side semiconductor layer 84b1) of the 1st substrate P 1
Form the insulating materials (SiO accumulated with given thickness2、Al2O3Deng) film (insulating layer) 84b2 (step 1 is rapid).This insulating layer
84b2 is formed in the 1st substrate P 1 by above-mentioned film formation device 10 is used.This semiconductor layer 84b1 and insulating layer 84b2
Constitute functional layer 84b.
Then, in step S76, as shown in Figure 14B, in the 1st substrate P 1 (on insulating layer 84b2) formed with set thickness
Spend film (the 2nd conductive layer) 84c of the metal based material (conductive material of Cu, Al, Mo etc.) of accumulation.This 2nd conductive layer 84c
It is to be formed in the 1st substrate P 1 by above-mentioned film formation device 10 is used.2nd conductive layer 84c is the electricity as gate electrode
Pole layer and the wiring layer of the incidental wiring of gate electrode and function.With this 1st conductive layer 84a, functional layer 84b and the 2nd
Conductive layer 84c constitutes lamination tectosome 84.
Photolithographic etching process is utilized secondly, imposing, as shown in Figure 14 C, forms grid electricity in the 2nd conductive layer 84c
Pole and its incidental wiring (step 1 is rapid).In addition, only indicating gate electrode in Figure 14 C.The step shown in Figure 14 C is
The 1st substrate P 1 for being formed with the 2nd conductive layer 84c is imposed, light is utilized to form gate electrode and its incidental wiring
The etching process of lithography.Whereby, in forming TFT in the 1st substrate P 1.
Simple declaration is by being utilized the formation of gate electrode that photolithographic etching process carries out etc., firstly, in step
S77, in forming photoresist layer on the 2nd conductive layer 84c.Photoresist layer is by desciccator diaphragm resist as illustrated by the step S5 with Fig. 3
Or coating etc. and formed.Then, in step S78, using ultraviolet light by predetermined pattern (gate electrode and its incidental wiring etc.
Pattern) be exposed to and be formed by photoresist layer, develop in step S79.Whereby, predetermined pattern is formed in photoresist layer.Secondly,
In step S80, it is impregnated in corrosive liquid (such as aoxidize two iron etc.) by by the 1st substrate P 1, predetermined pattern will be formed with by imposing
Etching process of the photoresist layer as exposure mask, to form gate electrode and its incidental wiring etc. in the 2nd conductive layer 84c.Then,
In step S81, removing is located at the photoresist layer on the 2nd conductive layer 84c, carries out cleaning for the 1st substrate P 1.By the step via Figure 11
The step of step S81 of rapid S63~Figure 12, in formation lamination tectosome 84 in the 1st substrate P 1.
Then, in step S82, as shown in fig. 14d, by the 1st substrate P 1 for be formed with lamination tectosome 84 that is,
Solid is coated on 2nd conductive layer 84c and forms following layer 86.This following layer 86 is to make to be formed in the 1st substrate P 1
Lamination tectosome 84 easily transfers (then) in the 2nd substrate P.Such as UV hardening resin can be used as this solid.This
It is that ultraviolet light is irradiated in following layer 86 after forming following layer 86 under situation.
Secondly, in such a way that the 2nd conductive layer 84c is located at 2 side of the 2nd substrate P, making the 1st substrate P 1 and the 2nd base in step S83
Plate P2 is temporarily approached or is close to, and the lamination tectosome 84 that will be formed in the 1st substrate P 1 as shown in fig. 14e is transferred to the 2nd
Substrate P 2 (second step).This transfer, is transferred by above-mentioned laminater 30.It also that is, will be from 1 surface side of the 1st substrate P
It is rolled into according to the 1st substrate P 1 of the sequential lamination of peeling layer 80, insulating layer 82, lamination tectosome 84 and following layer 86 scroll-like
Person uses as the supply side reel 32 of laminater 30, and the lamination tectosome 84 that can will be formed in the 1st substrate P 1 whereby transfers
To the 2nd substrate P 2.Whereby, lamination tectosome 84 is formed in the 2nd substrate P 2 with the state of reversion.Also that is, constituting lamination construction
2nd conductive layer 84c of body 84, functional layer 84b, the 1st conductive layer 84a from the surface side of the 2nd substrate P 2 according to aforementioned sequence laminated on
In 2nd substrate P 2.At this point, peeling layer 80 is not transferred to 2 side of the 2nd substrate P and still remains on 1 side of the 1st substrate P.It is filled by lamination
30 are set transferred with the 2nd substrate P 2 of lamination tectosome 84, is to be recovered reel 40 to batch.By via such step, and in
Top contact type TFT as shown in fig. 14e is formed in 2nd substrate P 2.
In addition, can also be after transferring lamination tectosome 84 that is, TFT in the 2nd substrate P 2, photoetching is utilized by imposing
The etching process of method, and process insulating layer 82 as shown in fig. 14f (step 4 is rapid).By step shown in this Figure 14 F, and remain
The insulating layer 82 being located at least between source electrode and drain electrode, and remove in addition to this do not need insulating layer 82.
In step described above, also at least step of Figure 11 S61~figure can be carried out by the supply dealer of the 1st substrate P 1
The step of 12 step S81 (Figure 13 A~Figure 14 C), the step after supplying the step of dealer carries out is then by the system of electronic component
Make dealer's progress.For example, the step of can also supplying the step S82 for step S61~Figure 12 that dealer carries out Figure 11, manufacturer into
The step of step S83 of row Figure 12 (Figure 14 E).
As above, for example, carrying out the step S82's of step S61~Figure 12 of Figure 11 by the supply dealer of the 1st substrate P 1
Step, and the step of carrying out the step S83 of at least Figure 12 by the manufacturer of electronic component, can mitigate the system of electronic component whereby
Dealer's burden is made, high-precision electronic component can be manufactured.
(variation 2)
In above-mentioned variation 1, though insulating layer 82 is formed between peeling layer 80 and the 1st conductive layer 84a, in variation
Insulating layer 82 is not formed in 2.Also that is, in this variation 2, the step of step S62 without Figure 11.Therefore via
The step of step S63 is carried out after the step of step S61 of Figure 11.For example, passivation layer can be also not provided with, in no 80 quilt of peeling layer
Insulating layer 82 can not be also set between peeling layer 80 and the 1st conductive layer 84a by the occasion of the anxiety of etching.In addition, under this situation,
Due to not forming insulating layer 82 originally, photolithographic etching also is utilized without imposing as shown in fig. 14f to insulating layer 82
It handles to process necessity of insulating layer 82.
(variation 3)
Also, the 1st substrate P 1 for being formed with alignment mark Ks can be also supplied to manufacturing industry by the supply dealer of the 1st substrate P 1
Person.This alignment mark Ks, be to the exposure area W that will be exposed on substrate predetermined pattern be relatively aligned with substrate it is (right
It is quasi-) reference mark.This alignment mark Ks is detected optically by have microscopical camera, and can be detected
The position (position of the longitudinal direction of substrate, the position of short side direction, heeling condition) or abnormal in the face of substrate of substrate out
Change state.This alignment mark Ks, for example, in substrate Kuan degree Fang Xiang both end sides along substrate longitudinal direction (strip direction) with one
Fixed interval is formed.
For example, the supply dealer of the 1st substrate P 1, also can form lamination as Fig. 5 B or Fig. 9 B are shown in the 1st substrate P 1
It after tectosome 52 (72), i.e., imposes as shown in figure 15 and photolithographic etching process is utilized, in the 2nd conductive layer 52c (72c) formation
Alignment mark Ks (third step).Then, the 1st substrate P 1 for being formed with alignment mark Ks, Lai Jinhang Fig. 5 C (Fig. 9 C) also can be used
Later step.Under this situation, due to by transfer and the 1st conductive layer 52a (72a) become the 2nd substrate P 2 surface side, the 2nd
Conductive layer 52c (72c) becomes the deep side of the 2nd substrate P 2, therefore being formed by alignment mark Ks can be because of the 1st conductive layer 52a
(72a) and hide.Therefore also can be after transfer (such as form source electrode and when drain electrode), by photoetching process is utilized
Etching process, and it is as shown in figure 16, by removing the 1st conductive layer 52a (72a) with the region of alignment mark Ks opposite direction to set
Set window portion 90.Also, also can be by not in forming the 1st conductive layer 52a (72a) with the region of alignment mark Ks opposite direction window portion is arranged
90.Whereby, the step of removing the 1st conductive layer 52a (72a) with the region of alignment mark Ks opposite direction can be saved.In addition, functional layer
52b (72b), due to be to be constituted with radioparent material, though can with the optical mode of microscope etc. be aligned be shooting
Alignment mark Ks, but when functional layer 52b (72b) is constituted with non-transmissive material, preferably also in functional layer 52b (72b)
Window portion 90 is set.In addition, so-called window portion 90, is the opening portion formed to shoot alignment mark Ks.Also, also can will be to fiducial mark
Note Ks is formed in the 1st conductive layer 52a (72a), and window portion 90 is formed in the 2nd conductive layer 52c (72c).
It is using photolithographic etching process is utilized, in the 1st conduction also, when having formed the 1st conductive layer 52a (72a)
Layer 52a (72a) forms alignment mark Ks or window portion 90, is using photoetching is utilized when having formed the 2nd conductive layer 52c (72c)
The etching process of method forms window portion 90 or alignment mark Ks in the 2nd conductive layer 52c (72c).In particular, in above-mentioned variation 1 and
In 2, due to be on one side impose be utilized photolithographic etching process, while gradually form lamination tectosome 84, also can be
Also alignment mark Ks and window portion 90 are formed together in the formation of lamination tectosome 84.
Also, the supply dealer in the 1st substrate P 1 has grasped on electronic component circuit substrate matching in element area in advance
The field of line pattern (for example, handwork of shape, configuration, the size of larger pattern such as ground connection bus bar, power supply bus bar etc.)
It closes, also can be the 1st conductive layer 52a (72a) or the 2nd conductive layer 52c (72c) shape by photolithographic etching process is utilized
While at alignment mark Ks or window portion 90, the Wiring pattern of the grade is formed.In turn, pre- in the supply dealer of the 1st substrate P 1
The occasion for forming the region (or the region for not forming TFT completely) of Wiring pattern and semiconductor element (TFT) is first grasped, it also can be in
Accumulate the semiconductor layer as functional layer 52b (72b) with forming the regioselectivity of TFT, and in the region for not forming TFT completely
Selectively insulating layer of the accumulation as functional layer 52b (72b).Under this situation, in order to make the thickness of functional layer 52b (72b) entirety
Degree is uniform as much as possible, and semiconductor layer and insulating layer are also adjustable into roughly the same thickness.
(variation 4)
Figure 17 is the figure for showing the composition of the laminater 30a in variation 4.In addition, in variation 4, for it is upper
The identical composition of the 1st implementation form is stated, is to confer to the same symbol and the description thereof will be omitted.It is to replace guide roll in variation 4
GR6, and it is equipped with the radius guide roll GR6a big compared with guide roll GR6.In laminater 30a, equipped with to being wound in guide roll GR6a
The die coating leftover of bolt of cloth (the die coater head) DCH of thermmohardening solid that can be hardened by heat of the 2nd substrate P 2 coating.Also that is,
In variation 4, not to 1 side of the 1st substrate P but solid is coated with to 2 side of the 2nd substrate P, forms following layer 54 whereby
(74).Therefore being not provided with following layer 54 (74) in the 1st substrate P 1.Thermmohardening solid is coated with by die coating leftover of bolt of cloth DCH
Region in 2nd substrate P 2 is the periphery support for being directed to roller GR6a.This die coating leftover of bolt of cloth DCH is by thermmohardening solid pair
2nd substrate P 2 haves a wide reach and is similarly coated with.Whereby, the product in the 1st substrate P 1 can be will be formed in by crimping heating roller 36
Layer tectosome 52 (72) is transferred to the 2nd substrate P 2.
In detail, crimp heating roller 36, be located at lamination tectosome 52 (72) 2 side of the 2nd substrate P and be coated on the 2nd
The mode of thermmohardening solid contact in substrate P 2, clamps the 1st substrate P 1 and the 2nd substrate P 2 from two sides and is allowed to be close to simultaneously
It is heated.Since by this heating, thermmohardening solid is hardened, therefore forms following layer 54 (or 74), lamination tectosome
52 (72) are transferred to the 2nd by the lamination tectosome 52 (72) then, being formed in the 1st substrate P 1 securely with the 2nd substrate P 2
Substrate P 2.In addition, being separated from each other by the 1st substrate P 1 of crimping heating roller 36 with the 2nd substrate P 2.
(variation 5)
Figure 18 is the figure for showing the composition of the laminater 30b in variation 5.In addition, in variation 5, to the above-mentioned 1st
The identical composition of implementation form assigns the same symbol, and the description thereof will be omitted.It is to replace crimping heating roller 36, and be arranged in variation 5
Without heating the crimping roller 36b only crimped, and replaces guide roll GR6 and the radius guiding big compared with guide roll GR6 is set
Roller GR6b.Cylinder DRS this crimping roller 36b big compared with roller R with roller R and radius.Therefore being clamped with cylinder DRS and be close to by roller R
The 1st substrate P 1 and the 2nd substrate P 2, be that the state to overlap each other is transported along the periphery of cylinder DRS, thereafter, by
Guide roll GR7, GR8 and be separated from each other.1st substrate P 1 is to be recovered the guiding of reel 38 by guide roll GR7, the 2nd substrate
P2 is to be recovered the guiding of reel 40 by guide roll GR8.
In laminater 30b, equipped with the UV that can be hardened by UV light to the 2nd substrate P 2 coating for being wound in guide roll GR6b
Harden the die coating leftover of bolt of cloth DCH1 of solid.Also that is, in variation 5, not to 1 side of the 1st substrate P but to 2 side of the 2nd substrate P
It is coated with solid, forms following layer 54 (74) whereby.Therefore being not provided with following layer 54 (74) in the 1st substrate P 1.By die coating cloth
Head DCH1 and be coated with UV hardening solid the 2nd substrate P 2 on region, be directed to roller GR6b periphery support.This mould
Coating head DCH1 is that UV hardening solid haves a wide reach to the 2nd substrate P 2 and is similarly coated with.Also, being set in laminater 30b
There is irradiation unit UVS, irradiation unit UVS divides in the 1st substrate P 1 for being crimped roller 36b crimping with the 2nd substrate P 2 with multiple
From the preceding ultraviolet light irradiation source 94 to UV hardening solid irradiation UV (ultraviolet light) light.Whereby, it can will be formed by crimping roller 36b
The 2nd substrate P 2 is transferred in the lamination tectosome 52 (72) in the 1st substrate P 1.
In detail, the roller R and cylinder DRS of crimping roller 36b, be located at lamination tectosome 52 (72) 2 side of the 2nd substrate P and
The mode contacted with the UV hardening solid being coated in the 2nd substrate P 2, clamps the 1st substrate P 1 and the 2nd substrate P 2 simultaneously from two sides
It is allowed to be close to.Thereafter, irradiation unit UVS, to the 1st substrate P 1 for being wound in cylinder DRS with the state overlapped each other and being transported
And the 2nd substrate P 2 irradiate UV light.The hardening of the UV between the 1st substrate P 1 and the 2nd substrate P 2 is connect by the irradiation of this UV light
Agent hardening, therefore form following layer 54 (or 74), lamination tectosome 52 (72) and the 2nd substrate P 2 are by securely then.Herein
After the irradiation of UV, the 1st substrate P 1 is separated from each other with the 2nd substrate P 2 by guide roll GR7, GR8.Whereby, it is formed in the 1st substrate
Lamination tectosome 52 (72) on P1 is transferred to the 2nd substrate P 2.
[the 2nd implementation form]
In 2nd implementation form, illustrate the specific manufacturing method of the pixel circuit of organic el display.Figure 19 is display active
The figure of pixel circuit an example of one light emitting pixel of the organic el display of matrix-style, Figure 20 are pictures shown in display Figure 19
The figure of the specific configuration of plain circuit.Pixel circuit has TFT, capacitor C and Organic Light Emitting Diode (OLED:Organic
Light Emitting Diode).The one of the source electrode S and drain electrode D of TFT and its incidental wiring L1, capacitor C
The pixel electrode E of square electrode C1 and the cathode for being connected to OLED, are formed in the 1st conductive layer 102 of lamination tectosome 100.
The electrode C2 of another party of the gate electrode G of TFT and its incidental wiring L2 and capacitor C, is formed in lamination tectosome 100
The 2nd conductive layer 104.The electrode C2 of this capacitor C is connected to ground connection GND (ground wire).Also, being formed in the 1st that must link and leading
The position of the wiring L1 of the electric layer 102 and wiring L2 for being formed in the 2nd conductive layer 104 is equipped with electroless plating contact M.In addition, Figure 20
In, it in order to distinguish the 1st conductive layer 102 and the 2nd conductive layer 104, and is that the 1st conductive layer 102 is indicated with oblique line for convenience of description.
Illustrate the manufacturing method with the pixel circuit of top contact type TFT in this 2nd implementation form.Figure 21 and Figure 22 is aobvious
Show the flow chart of step an example of the manufacturing method of pixel circuit.
Firstly, the step of by step S101~step S105, as shown in figure 23, sequentially from the surface side of the 1st substrate P 1
Peeling layer 106, the 1st conductive layer 102, semiconductor layer 108, insulating layer 110 and the 2nd conductive layer 104 are formed in the 1st substrate P 1
On.The step of this step S101~step S105, with the step of Fig. 7 S31~step S35 the step of, are identical.Semiconductor layer 108 and
Insulating layer 110 constitutes the 112, the 1st conductive layer 102 of functional layer, functional layer 112 (semiconductor layer 108 and insulating layer 110), the 2nd conduction
Layer 104 constitutes lamination tectosome 100.In this 2nd implementation form, the 1st conductive layer 102 and the 2nd conductive layer 104 are with Cu (copper) shape
At semiconductor layer 108 is formed with one kind that is, ZnO of oxide semiconductor, and insulating layer 110 is with SiO2It is formed.
Then, it by photolithographic etching process is utilized, as shown in Figure 24 and Figure 25, is formed both in the 2nd conductive layer 104
Determine pattern (pattern of the electrode C2 of above-mentioned gate electrode G, wiring L2 and capacitor C).In addition, in Figure 24, in the 2nd conduction
Layer 104 only illustrates gate electrode G and wiring L2.Also, in order to distinguish the 1st conductive layer 102 and the 2nd conductive layer 104, being in Figure 25
The 1st conductive layer 102 is shown with oblique line.
Simple declaration is by being utilized the formation of gate electrode that photolithographic etching process carries out etc., firstly, in step
S106, in forming photoresist layer on the 2nd conductive layer 104.Then, in step S107, using ultraviolet light by predetermined pattern (gate electrode
G, the pattern of wiring L1 and electrode C2) it is exposed to be coated with photoresist layer, develop in step S108.Whereby, in photoresist layer
Form predetermined pattern.Secondly, by the corrosive liquid that the 1st substrate P 1 is impregnated in two iron of oxidation, imposing will form in step S109
There is etching process of the photoresist layer of predetermined pattern as exposure mask, and forms gate electrode G etc. in the 2nd conductive layer 104.Then, exist
Step S110, stripping resistance layer carry out cleaning for the 1st substrate P 1.The step of this step S106~step S110 is the step with Fig. 7
Rapid S36~step S40 is identical.In region after removing the 2nd conductive layer 104 by this etching process, functional layer 112 is exposed.
Thereafter, it in step S111, by the 1st substrate P 1 to be impregnated in the corrosive liquid of hydrogen fluoride, and also loses as shown in figure 24
Carve (processing) functional layer 112.Function in region after being removed the 2nd conductive layer 104 due to the etching process by step S109
Ergosphere 112 exposes, therefore the functional layer 112 for being removed the region after the 2nd conductive layer 104 is the etching process by step S111
And it removes.
Thereafter, in step S112, by surface side (the 2nd conduction for the 1st substrate P 1 for being formed with lamination tectosome 100
104 side of layer) it is coated with solid and forms following layer 114.Then, in step S113, the 2nd substrate P 2 is located at the 2nd conductive layer 104
The mode of side makes the 1st substrate P 1 temporarily approach or be close to the 2nd substrate P 2, and as shown in figure 26, will be formed in the 1st substrate P 1
Lamination tectosome 100 be transferred to the 2nd substrate P 2.This transfer is transferred by laminater 30.This step S112 and step
The step of S113 is identical as the step of Fig. 8 S41~step S43.
Then, it by photolithographic etching process is utilized, is formed both as Figure 27 and Figure 28 is shown in the 1st conductive layer 102
Determine pattern (pattern of above-mentioned source electrode S and drain electrode D, wiring L1, the electrode C1 of capacitor C and pixel electrode E).
In addition, only illustrating source electrode S, drain electrode D and wiring L1 in the 1st conductive layer 102 in Figure 27.Also, in Figure 28, for area
Other 1st conductive layer 102 and the 2nd conductive layer 104, and the 1st conductive layer 102 is shown with oblique line.
Simple declaration is by being utilized the formation of source electrode that photolithographic etching process carries out etc., Figure 22 the step of
S114 forms photoresist layer in the surface side (102 side of the 1st conductive layer) of the 2nd substrate P 2.Then, in step S115, ultraviolet light is used
Predetermined pattern (pattern of source electrode S, drain electrode D, wiring L1, electrode C1 and pixel electrode E) is exposed to and is formed by
Photoresist layer develops in step S116.Whereby, predetermined pattern is formed in photoresist layer.Secondly, in step S117, by by the 2nd
Substrate P 2 is impregnated in the corrosive liquid of two iron of oxidation, and the photoresist layer for being formed with predetermined pattern is imposed etching process as exposure mask, with
Source electrode S and drain electrode D etc. are formed in the 1st conductive layer 102.At this point, to the contact hole H for forming electroless plating contact M
Opening portion be also formed in the 1st conductive layer 102.Then, in step S118, removing is located at the photoresist on the 1st conductive layer 102
Layer carries out cleaning for the 2nd substrate P 2.The step of this step S114~step S118, other than forming this point of contact hole H,
Step S44~step S48 of Yu Junyu Fig. 8 is identical.
Then, by photolithographic etching process is utilized, as shown in figure 29, the functional layer 112 of the part contact hole H is etched
(semiconductor layer 108 and insulating layer 110).Also that is, in step S119, in the surface side (102 side of the 1st conductive layer) of the 2nd substrate P 2
Form photoresist layer.Then, in step S120, predetermined pattern is exposed to using ultraviolet light and is formed by photoresist layer, in step
S121 develops.Whereby, predetermined pattern is formed in photoresist layer.Secondly, being impregnated in step S122 by by the 2nd substrate P 2
The corrosive liquid of hydrogen fluoride, and etching process is imposed using the photoresist layer for being formed with predetermined pattern as exposure mask, and also etch contact hole H
Partial functional layer 112.Whereby, contact hole H is completed.
Thereafter, in step S123, electroless treatment is carried out to the part contact hole H, as shown in figure 30, formed with such as Cu,
The electroless plating contact M of the compositions such as Cr, NiP, the 1st conductive layer 102 (wiring L1) and the 2nd conductive layer 104 (wiring L2) is electrical
Connection.Then, in step S124, removing is located at the photoresist layer in the 2nd substrate P 2, carries out cleaning for the 2nd substrate P 2.By such as with
On step, pixel circuit as shown in figure 20 can be manufactured.
In addition, in above-mentioned 1st implementation form (also including variation) and above-mentioned 2nd implementation form, though using being utilized
Photolithographic etching process carrys out film processed, but as long as being the working process that photo-patterning method is utilized, then any method.
As the working process that photo-patterning method is utilized, other than photolithographic etching process is utilized, such as has and make to be formed
The pattern light that ultraviolet light is irradiated in the state of having the 1st substrate P 1 of lamination tectosome 52 to be impregnated in special liquid is coating to etch
In the gimmick of the resist layer on the 2nd conductive layer 52c, or by with the figure of the point irradiation ultraviolet light of the laser beam of high NA optically focused
Case light degrades gimmick etc. with directly remove (etching) the 2nd conductive layer 52c.
Also, in above-mentioned 1st implementation form (also including variation) and above-mentioned 2nd implementation form, though with bottom-gate structure
It is illustrated for the TFT made, but also can be the TFT of top gate configuration.Also, being formed in the 1st substrate P 1 (supporting substrate)
Lamination tectosome 52,72 etc. be not limited to thin film transistor (TFT) (TFT), to the system of the electronic component comprising thin film diode (TFD)
It is also useful for making.Furthermore in the composition of lamination tectosome 52,72 etc., it is sandwiched in upper and lower the 1st conductive layer and the 2nd conductive layer
Between functional layer 52b (72b) also can be 2 layers or more of film.For example, being with the 1st functional membrane in functional layer 52b (72b)
The occasion constituted with the lamination of the 2nd functional membrane, also can the 1st functional membrane in the 1st substrate P 1 in integrally right with element area
The region answered similarly forms a film, and the 2nd functional membrane selectively forms a film in the region of a part on the 1st functional membrane.
In addition, in above-mentioned 1st implementation form (also include variation) and above-mentioned 2nd implementation form etc., by the 1st substrate
In P1 (the supporting substrate of metal foil etc.) surface lamination have the rugosity on the insulating layer of lamination tectosome or the surface of semiconductor layer with
The occasion indicated using the arithmetic average rugosity Ra value (nm) of JIS specification, rugosity Ra value are decided to be no more than institute's lamination
Insulating layer (or semiconductor layer) thickness range.However, in order to guarantee the movement steady in a long-term as TFT, the 1st substrate P 1
Surface rugosity Ra value preferably be located at 200nm or less (below ultra micro rice), be more preferably located at 1nm~tens of nm range.
Rugosity Ra value is set smaller, the electronics degree of excursion of the electrical characteristic as TFT, ON/OFF are got over than each characteristic of, leakage current
It is promoted.Though rugosity Ra value can also be set as to 1nm is less than, as practical rugosity Ra value, as long as number nm or so.It is such
Rugosity Ra value can be easily made with current surface treatment (grinding) technology.Also, being to form a film on the surface of the 1st substrate P 1
Out when the 1st conductive layer (52a, 72a, 84a, 102) of lamination tectosome, also it may replace the 1st substrate P 1 with milled processed etc.
The mode of surface planarisation, but after the surface of the 1st substrate P 1 forms planarization film, in sequentially forming stripping on the planarization film
Absciss layer (50,70,80,106), the 1st conductive layer (52a, 72a, 84a, 102).Planarization film is to fill 1 surface of the 1st substrate P
Heating of the recess portion with gentle bumps and with strong etching patience, at transfer (lamination) or when after annealing (post annealing)
Handle the material such as silica (SiO that will not be also denaturalized2) system wet type material constitute.As the material of such planarization film,
Sumisefine (registered trademark), Cao Da limited liability company, the Japan system of Sumitomo Osaka cement Co., Ltd can be used
BISUTOREITA (registered trademark), the COLCOAT (registered trademark) of COLCOAT limited liability company, Han Wei affiliated company
Or smoothing material SOG (Spin On Glass) peddled such as chemical conversion limited liability company, Hitachi etc..
[variation of above-mentioned each implementation form]
Above-mentioned each implementation form (also including each variation) further can also have following deformation.
[variation 1]
Figure 31 is to be likewise shown in the 1st substrate P 1 to be continuously formed electronic component with the film formation device 10 of previous Fig. 1
The schematic configuration of the film formation device 10A of lamination tectosome.The film formation device 10A of Figure 31 have process chamber 16, vacuum pump 18,
Film forming rotor 22 is configured at around film forming rotor 22 and continuously to accumulate multiple film forming raw material (films
Raw material) multiple substrate 20A, 20B, 20C and guide roll GR1~GR3.As illustrated by the previous each implementation form or variation,
In formation conductive layer (metal film, ito film etc.), 2 layers of tectosome of insulating layer (dielectric film) in the 1st substrate P 1 or in this 2 layers
Structurally film forming has 3 layers of tectosome of semiconductor layer.Therefore, the substrate 20A being configured at around film forming rotor 22, be by
By vapor deposition, sputter or CVD etc. come the conductive layer that forms a film out, substrate 20B is come on conductive layer by vapor deposition, sputter or CVD etc.
Form a film out insulating layer, substrate 20C, is by vapor deposition, sputter or CVD etc. come in the semiconductor layer that forms a film out on insulating layer.In addition,
It is to form the occasion of 2 layers of tectosome of conductive layer and insulating layer in the 1st substrate P 1, as long as the film forming without substrate 20C is
It can.Furthermore the difference of the construction according to TFT to be made, the also configuration of replaceable substrate 20B and substrate 20C, and with conduction
Layer, semiconductor layer, insulating layer sequence form a film.
As above-mentioned, used by each film forming portion of the substrate 20A, 20B, 20C of multiple thin-film materials to be sequentially configured to film forming
Around rotor 22, due to once forming desired lamination construction on the surface to recycle the 1st substrate P 1 that reel 14 is rolled
Body, therefore be not required to that reel 14 will be recycled to change and be located at other film formation device, productivity is promoted.Under this situation, preferably first in substrate
The film forming portion of 20A, the film forming portion of substrate 20B, substrate 20C film forming portion, be set to mutually synthermal.Also, as film formation device
10A can be that such as No. 2013/176222 revealed misted deposition method of specification of International Publication No. (atomization CVD method) is utilized
Device.Under this situation, the substrate of filmogen is in the mist for sparging 1 surface of the 1st substrate P with ionic condition or nanoparticle
Sub- state is contained.Furthermore if being made in the space between 1 surface of spray nozzle and the 1st substrate P of mist using high-voltage pulse electric
The atmospheric pressure plasma-based of nonequilibrium condition generates, even if then the temperature of the 1st substrate P 1 is 200 DEG C or so, also can be carried out atomization CVD method
Good filming, rate of film build also promotes.
[variation 2]
Figure 32 is the skeleton diagram for showing the variation of previous Fig. 9 A~Fig. 9 D, Figure 10 A~Figure 10 C transfer printing, to figure
The identical component of symbol (layer, film, material etc.) in 9A~Fig. 9 D, Figure 10 A~Figure 10 C assigns identical identical symbol.Formerly
It is as shown in Figure 9 B, in sequentially laminated peel layer 70, the 1st conductive layer 72a, half in the 1st substrate P 1 in the example of preceding Fig. 9 A~Fig. 9 D
After conductor layer 72b1, insulating layer 72b2, the 2nd conductive layer 72c, i.e., as shown in Figure 9 C, etches the 2nd conductive layer 72c and form grid
Electrode.Though the 1st substrate P 1 shown in Figure 32 is also similarly, laminated peel layer 70, the 1st conductive layer 72a, semiconductor layer 72b1,
Insulating layer 72b2, the 2nd conductive layer 72c, but in this variation, not semiconductor layer 72b1 is identically formed in the 1st conduction
On layer 72a, but in the regional area selectivity for being equivalent to channel part (gap portion of source electrode and drain electrode) of TFT
Ground forms semiconductor layer 72b1.Under this situation, as long as in forming photoresist layer on the 1st conductive layer 72a, by photoetching process in be formed
The region of semiconductor layer 72b1 forms the opening portion of resist layer, in its opening portion by the accumulations such as vapor deposition, sputter, CVD half
Conductor material.
Thereafter, in the variation of Figure 32, the 1st conductive layer 72a and semiconductor layer 72b1 that is formed selectively is same
The mode covered to sample forms a film out insulating layer 72b2, further conductive in the 2nd conductive layer 72c that forms a film out on insulating layer 72b2, the 2nd
Layer 72c is to be processed to gate electrode by photolithographic etching process is utilized in the same manner as previous Fig. 9 C and (and connect with it
The wiring connect).In this variation, it is selectively formed a film due to that semiconductor layer 72b1 can be limited to the forming region of TFT,
Therefore it can inhibit the usage amount of semiconductor material.It is such as above-mentioned, it is transferred in the lamination tectosome 72 that will be formed in the 1st substrate P 1
When 2 substrate P 2, though it is to be coated with following layer 74 in 72 surface of lamination tectosome of the 1st substrate P 1 in Yu Xianqian Fig. 9 D, at this
It is to form following layer 74 in 2 side of the 2nd substrate P as shown in figure 32 in variation.The 2nd substrate P 2 in this variation, is in PET
Or the composition of the buffer layer P2b of surface area layer polyethylene (PE) of the plate shape substrates P2a of PEN etc. etc., in the surface of buffer layer P2b
Following layer 74 is formed by sealant (Silicon Sealant etc.) P2c.
As shown in figure 32, the lamination tectosome 72 in 1 side of the 1st substrate P is electric with the semiconductor layer 72b1 of selectivity or grid
It is concave-convex due to that can generate in lamination tectosome 72 with the opposite face of the 2nd substrate P 2 when pole is formed, when also having a transfer with
The inhomogenous situation of the abutting of 2nd substrate P 2.Therefore, buffer layer P2b is equipped in order to absorb such concave-convex.As buffer layer
P2b preferably has stability and plasticity person, and the occasion being thermally compressed in transfer, which is preferably polyethylene (PE) etc., to be had
The material of thermoplasticity.Furthermore it is formed in the following layer 74 on buffer layer P2b, in this variation, for vinyl acetate tree
Synthetic resin emulsifying solid EVA (the Ethylene Vinyl of rouge, ethene-vinyl acetate copolymer resin as main body
Acetate).By such composition is taken, has the lamination tectosome 72 of indent and convex 1st substrate P, 1 side, not will receive slight crack etc.
Damage, can critically be transferred to 2 side of the 2nd substrate P.
[variation 3]
As shown in above-mentioned Figure 32, using following layer 74 (EVA) though occasion can transfer well, if the 1st substrate
The bumps of the lamination tectosome 72 of the side P1 are larger, it is likely that because the internal stress generated when following layer 74 (EVA) hardening makes firmly
It is especially the 2nd top conductive layer 72c of lamination tectosome 72 in following layer 74 (EVA) after change or nearby generates fine slight crack.
It therefore, is as shown in figure 32 in formation lamination tectosome 72 (the 1st conductive layer 72a, semiconductor layer 72b1, insulation in the 1st substrate P 1
Layer 72b2, the 2nd conductive layer 72c) after, as shown in figure 33, planarization film is formed in the mode for covering whole on lamination tectosome 72
FP.This planarization film FP is to fill the recess portion of lamination tectosome 72 with gentle bumps and have strong etching patience, in transfer (product
Layer) when or the material that will not also be denaturalized of heat treatment when after annealing, such as silica (SiO2) system wet type material constitute.Make
For the material of such planarization film FP, the sumisefine (registrar of Sumitomo Osaka cement Co., Ltd can be used
Mark), the BISUTOREITA (registered trademark) of Cao Da limited liability company, Japan, COLCOAT limited liability company
The smoothing material SOG that COLCOAT (registered trademark), Han Wei affiliated company or chemical conversion limited liability company, Hitachi etc. are peddled
(Spin On Glass) etc..Then after the material of planarization film FP is completely dried or it is dry on the way, in the 2nd substrate P 2
Following layer 74 (EVA) crimping transfer have planarization film FP lamination tectosome 72.
Planarization film FP is an inorganic insulating membrane (or organic insulating film), have by with by the following layer 74 of lamination
(EVA) effect that slight crack caused by internal stress when directly engaging and hardening following layer 74 (EVA) lowers.In addition,
In Figure 33, though it is after forming lamination tectosome 72 in the 1st substrate P 1, the wet type material of coating flat film FP thereon,
Also can be as shown in figure 32, after forming following layer 74 (EVA) in the 2nd substrate P 2, planarized in being formed on its following layer 74 (EVA)
Lamination tectosome 72 in 1st substrate P 1 is transferred to planarization before planarization film FP is dry by film FP while heating
Film FP.Also, in Figure 32, Tu33Zhong, though in the bright lamination tectosome 72 being formed in the 1st substrate P 1, the of 1 side of the 1st substrate P
1 conductive layer 72a becomes the source electrode/drain electrode and wiring connected to it of TFT, the 2nd conductive layer of 2 side of the 2nd substrate P
72c becomes the gate electrode and wiring connected to it of TFT, but also can be opposite.Also that is, also can using the 1st conductive layer 72a as
The gate electrode of TFT and wiring connected to it, using the 2nd conductive layer 72c as source electrode/drain electrode of TFT and and its
The wiring of connection.
[the 3rd implementation form]
Figure 34 A~Figure 34 D to Figure 36 A~Figure 36 B is shown the manufacturing method of the implementation form of previous Figure 23~Figure 30
The figure of the manufacturing step of electronic component (TFT) after a part improvement.Therefore to Figure 34 A~Figure 34 D to Figure 36 A~Figure 36 B institute
Person identical as each component (material) in Figure 23~Figure 30 in each component (material) shown assigns and the symbol in Figure 23~Figure 30
Identical symbol.In this implementation form, as shown in fig. 34 a, the 1st substrate P 1 is the copper (Cu) of tens of μm~hundreds of μm degree of thickness
Sheet foil plate, have the 1st conductive layer 102 of copper (Cu) in comprehensive lamination across peeling layer 106 in its surface.This 1st conduction
Layer 102 is that thickness is calendered into tens of μm below copper foil laminated to be formed on peeling layer 106.The 1st after lamination is conductive
Layer 102, be on one side reduce its thickness, while so that the arithmetic average rugosity Ra value on surface is become the side of the number number of nm~ten nm or so
Formula grinding.
Secondly, as illustrated in figure 34b, on the 1st conductive layer 102 of the 1st substrate P 1, forming the gate insulating film as TFT
And the insulating layer 110 functioned.This insulating layer 110 is typical silicon oxide layer (SiO2), it can be by the 1st conductive layer 102
Remove the method for the silicon oxide layer other than the forming region of TFT after film forming by etching etc. comprehensively or by selectively forming a film
It is formed from method that silicon oxide layer only initially is deposited to the forming region of TFT etc..Due to the 1st substrate P 1 and the 1st conductive layer
102 be the high copper of heat resistance (Cu), therefore can in vacuo high temperature be formed a film, and the flatness (rugosity Ra) of silicon oxide layer can be made good
It is good.
Secondly, as shown in figure 34 c, in 110 (SiO of insulating layer2) on form semiconductor layer 108.Herein, semiconductor layer 108
For the IGZO (oxide semiconductor) being made of indium (Indium), gallium (Gallium), zinc (Zinc) and oxygen (Oxide).IGZO
Semiconductor layer 108, be using indium, gallium, zinc and oxygen as constitution element, by by the atom relative to indium and the indium of the total amount of gallium
The atomicity than the zinc with the total amount relative to indium and gallium and zinc is counted than being set as the oxidate sintered body of set ratio as sputter target
Sputtering unit formed a film.It before sputter step, is implemented in the comprehensive resist layer being formed in the 1st substrate P 1
The place of window corresponding with the forming region of semiconductor layer 108 is formed by lithography step (exposure of pattern and the development of resist)
Reason also implements the step of removing resist layer after sputtering unit sputter IGZO semiconductor.Whereby as shown in figure 34 c, in exhausted
The semiconductor layer 108 of IGZO is formed selectively in edge layer 110.
Secondly, as shown in Figure 34 D, as the source electrode 104 (S) and drain electrode 104 (D) of the 2nd conductive layer 104, with
Mode on semiconductor layer 108 as channel part (Channel) is oppositely disposed with certain interval and is formed.It is also same herein
Ground forms the window portion of resist layer in the region for forming source electrode 104 (S) and drain electrode 104 (D) using lithography step,
In source electrode 104 (S) and drain electrode 104 (D) in its window portion by deposits such as vapor depositions.Source electrode 104 (S)
It with drain electrode 104 (D), engage due to semiconductor layer 108, preferably the big gold of service factor (Au), but also may be used
Conductive ink material for other metal materials (aluminium, copper) or comprising Nano silver grain or metallic carbon nanotubes.Herein, source
Pole electrode 104 (S) and drain electrode 104 (D), are formed as extending to from channel part outside the region of insulating layer 110 as shown in Figure 34 D
1st conductive layer 102 of side, source electrode 104 (S) and drain electrode 104 (D) become the shape with 102 electrically conducting of the 1st conductive layer
State (Ohmic contact).By above step, in formation lamination tectosome 100 (the 1st conductive layer 102, insulating layer in the 1st substrate P 1
110, semiconductor layer 108, the 2nd conductive layer 104).
Figure 35 is the figure for showing the planar configuration for the lamination tectosome 100 being formed in the 1st substrate P 1 and constituting.As TFT
Electrical characteristic, the electronics degree of excursion that is expected to is all high with ON/OFF ratio and leakage current is fully small.In this embodiment, it is
The surface of the 1st conductive layer 102 of the substrate as TFT is set to become arithmetic average rugosity Ra value fully small even surface.Therefore,
Insulating layer 110 formed thereon, semiconductor layer 108 are also formed as the planar film of homogeneous thickness, and semiconductor layer 108 is led with the 2nd
The flatness of the contact interface of electric layer 104 (source electrode and drain electrode) is also well maintained.Whereby, electronics degree of excursion,
ON/OFF ratio, leakage current obtain good characteristic.Also, due to can be by the source electrode 104 (S) and drain electrode of channel part
The gap of 104 (D) is set as several μm or so of small―gap suture, therefore can obtain playing the high performance TFT of IGZO characteristic of semiconductor.This
Outside, as shown in figure 35, insulating layer 110, semiconductor layer 108, the 2nd conductive layer 104 (source electrode and drain electrode) lamination
When, it is necessary to opposite overlapping is carried out with micron grade.Therefore alignment actions must be carried out in lithography step, i.e., with exposure device
Interior alignment sensor detects that the specific position in the 1st substrate P 1 (especially the 1st conductive layer 102) is formed by alignment mark
Position, to adjust pattern exposure position.
Figure 36 A~Figure 36 B is to show lamination tectosome 100 shown in Figure 34 A~Figure 34 D, Figure 35 being transferred to the 2nd substrate
P2 and further impose working process situation figure.Figure 36 A is display by transfer (lamination) step and in the 1st substrate P 1
Lamination tectosome 100 is transferred to the situation at a moment after the 2nd substrate P 2.This implementation form also similarly, such as with elder generation before transfer
As preceding Figure 33 is illustrated, the comprehensive planarization film FP of lamination tectosome 100 for covering the 1st substrate P 1 is formed in the 1st substrate P 1
On, and as to be ready for buffer layer P2b shape of the surface plate shape substrates P2a by polyvinyl resin of PET as illustrated by previous Figure 32
As the 2nd substrate P 2 of given thickness, further in the following layer (EVA) 114 of vinyl acetate resin is formed in the 2nd substrate P 2
For given thickness.It is the following layer (EVA) on the planarization film FP and the 2nd substrate P 2 made in the 1st substrate P 1 on one side in transfer
114 with set pressure crimping, hardens following layer (EVA) 114 by heating on one side, removes lamination tectosome from the 1st substrate P 1
100.Whereby, as shown in Figure 36 A, in the 2nd substrate P 2, lamination tectosome 100 is exposed to most upper with the 1st conductive layer (Cu) 102
The state in face is bonded.
After transferring shown in Figure 36 A in the state of a moment, the residue for having peeling layer 106 sometimes is attached to the 1st conduction
The situation on 102 surface of layer.In this case, the surface of the 1st conductive layer 102 can be cleaned or is ground.In particular, the 1st
Conductive layer 102 with a thickness of tens of μm or so of occasion, due to spending the time to carry out the 1st conductive layer 102 hereafter sometimes
Working process (especially etching process), therefore grinding steps can be first placed in, the thickness of the 1st conductive layer 102 is first made several μm
Left and right.In this implementation form, due to being equipped with following layer 114, the planarization film FP of buffer layer P2b, EVA, by the 1st conduction
The external force when grinding on 102 surface of layer, it is damaged (slight crack, broken string) to can inhibit internal TFT.Also, when being manufactured in the 1st substrate P 1
In alignment mark used in lithography step when the lamination tectosome 100 of TFT, it is formed in multiple positions of the 1st conductive layer 102
When the alignment mark for each position set is fine through hole (such as circle, the rectangle at 20 μm of angles of 20 μm of diameters etc.), due to such as
1st conductive layer 102 shown in Figure 36 A is the top, therefore easily can detect its alignment with the alignment sensor of exposure device
Label.Therefore in lithography step 1 conductive layer 102 of working process, it can be correctly special using the position of alignment mark as benchmark
Make the position of the TFT of 102 lower layer of the 1st conductive layer, particularly each position of source electrode 104 (S) and drain electrode 104 (D).
It is coated with resist layer in the surface of the 1st conductive layer 102 of Figure 36 A, by exposure device, by the grid electricity with TFT
Pole, source electrode, drain electrode and with this etc. the corresponding pattern light of the connected shape of wiring of electrodes be exposed to resist
Layer.At this point, the launching position of pattern light, is to detect to be formed in the 1st conductive layer 102 by the alignment sensor with exposure device
Alignment mark critically set.By the development treatment of the resist layer after exposure, the etching of the 1st conductive layer 102 (Cu)
Processing, as shown in figure 36b as formed the gate electrode 102G of the 1st conductive layer 102, source electrode 102S, drain electrode 102D (and
The wiring being connect with the grade electrodes).At this point, implement alignment and patterning, to become the source electrode 102S after etching and with half
Source electrode 104 (S) engagement, drain electrode 102D and the leakage bound directly with semiconductor layer 108 that conductor layer 108 is bound directly
The state of pole electrode 104 (D) engagement.In turn, the gate electrode 102G after etching, is patterned into channel shown in coverage diagram 35
Portion's (clearance portion of source electrode 104 (S) and drain electrode 104 (D)).
Figure 37 is to show that the planar configuration of the TFT of Figure 36 B constitutes the figure of an example, and the 36B-36B ' arrow in Figure 37 regards section
For Figure 36 B.Though removing the unwanted part of the 1st conductive layer 102, in the part being removed, insulating properties by etching process
Planarization film FP expose.In order to manufacture electronic component, will more multifunctional element (resistance, capacitor, light-emitting component, light
Element, IC etc.) when being formed in the 2nd substrate P 2, can the welding such as wiring part for being formed of 1 conductive layer 102 of Yu Yi this etc. functions
Element.Also, in the occasion that the 1st conductive layer 102 is copper (Cu), it also will can prevent from aoxidizing the insulating properties, heat-resisting of caused corrosion
The film of property selectively or is integrally formed.
More than, in this embodiment, in order to make the 1st conductive layer of the lamination tectosome 100 being formed in the 1st substrate P 1
102 arithmetic average rugosity Ra value is fully small and can use vacuum manufacturing process or high temperature manufacturing process and use metal foil
(copper foil) is used as the 1st substrate P 1, and can form high performance TFT.Therefore manufactured by can finally making in flexible 2nd substrate P 2
Promoted to the performance great-jump-forward of electronic component (display panel, touch panel, sheet body sensor etc.).In addition, in this implementation form,
Though will be formed in 104 working process of the 2nd conductive layer in the lamination tectosome 100 in the 1st substrate P 1 at TFT source electrode,
Drain electrode, but also can be by 104 working process of the 2nd conductive layer at gate electrode.Under this situation, as long as in Figure 34 A~Figure 34 D institute
Make insulating layer 110 and semiconductor layer on the 1st conductive layer 102 in the manufacturing step of the TFT (lamination tectosome 100) shown
108 sequence (upper and lower relation) is opposite.Also that is, initially forming semiconductor layer in the given area on the 1st conductive layer 102
108, and insulating layer 110 is formed with the size that semiconductor layer 108 is completely covered thereon, and on its insulating layer 110, by the 2nd
The gate electrode of conductive layer 104 is formed as being combined with 102 part of the 1st conductive layer.
Also, in this above implementation form, though the 1st substrate P 1 is the sheet foil plate of copper (Cu), in its surface across stripping
Absciss layer 106 and the 1st conductive layer 102 for forming lamination tectosome 100, but also can be by the sheet foil plate of the copper (Cu) of the 1st substrate P 1
Itself it is made the 1st conductive layer 102 of lamination tectosome 100.Under this situation, the 1st substrate P 1 can be the arithmetic for being rolled into its surface
Average boldness Ra value fully small metal foil (copper foil), and according further to needing surface grinding.
Also, when the 1st conductive layer 102 is 1 substrate P 1, since the 1st substrate P 1 itself becomes 102 (electricity of the 1st conductive layer
Pole, wiring) it is transferred to 2 side of the 2nd substrate P, therefore preferably a moment carries out making the 1st substrate P 1 that (the 1st leads for example after transfer step
Electric layer 102) thickness reduction milled processed.In this way, the 1st substrate P 1 as 1 conductive layer 102 when, being will be comprising the 1
Substrate P 1 and lamination tectosome (conductive layer, the insulating layer, semiconductor layer) collective transfer constituted are to 2 side of the 2nd substrate P, result
It is then that the 1st substrate P 1 is also transferred to 2 side of the 2nd substrate P.
Also, in this above implementation form, though by conductive with the 1st conductive layer 102 (or the 1st substrate P 1 itself) and the 2nd
Layer 104 clips insulating layer 110 and 2 layers of composition of semiconductor layer 108 is made lamination tectosome, but also can be such as previous Fig. 5 A~figure
Shown in 5F, insulating layer (or only semiconductor will be only clipped with the 1st conductive layer 102 (or the 1st substrate P 1 itself) and the 2nd conductive layer 104
Layer) composition be made lamination tectosome.
In this way, when the 1st substrate P 1 is configured to a part of lamination tectosome in itself, composition electronics will be formed with
1st substrate of at least part lamination tectosome of element is transferred to the manufacturing method on the 2nd substrate, is to implement step 1
Suddenly and second step, which is the 1st conductive layer for preparing the 1st substrate and being constituted as conductive material suddenly, conductive in the 1st
The functional layer that the material of at least one party of insulating properties and semiconductor is constituted is formed on layer, in formation electric conductivity material in the functional layer
Expect the 2nd constituted conductive layer, forms lamination tectosome whereby, which is to be located at the 2nd substrate-side with the 2nd conductive layer
Mode makes the 1st substrate and the 2nd substrate temporarily approach or be close to, and will include that the lamination tectosome of the 1st substrate is transferred to the 2nd base
Plate.
Also, when the 1st substrate P 1 is configured to a part of lamination tectosome in itself, in being transferred substrate transfer structure
At the transfer substrate of at least part lamination tectosome of electronic component, has by conductive material and play the 1st conductive layer
The conductive foil (such as metal foil) of function is formed in the 1st conductive layer by the material of insulating properties and at least one party of semiconductor
On functional layer and the 2nd conductive layer that is formed in by conductive material in functional layer.It is under this situation, transfer substrate is whole
Body transfers (fitting) to being transferred substrate.
Furthermore in the implementation form of above-mentioned Figure 34 A~Figure 34 D, though in the 1st substrate P 1 across 106 lamination of peeling layer
Copper foil is using as the 1st conductive layer 102, but in addition to this, also can lamination aluminium (Al), zinc (Zn), molybdenum (Mo), nickel (Ni), tantalum (Ta),
The foil or the foil made of grade foils plating deposit (Au) etc. that the foil of tin (Sn), stainless steel (SUS) etc. or the grade alloys are constituted come
As the 1st conductive layer 102.These metal foils, though calendering foil, electrolysis paper tinsel (anodized foil) are generated as, in order to when improving lamination
Close property, the opposite back side must have a degree of rugosity (such as to be for arithmetic average boldness Ra value with the 1st substrate P 1
200nm or so).On the other hand, the surface of the formation functional layer (insulating layer or semiconductor layer etc.) of metal foil, it is necessary to be rugosity Ra
Value is the even surface of number nm~tens of nm or so.Therefore in the occasion that the 1st conductive layer 102 is metal foil metal can be made with being intended to
The surface of foil is different from the rugosity Ra value at the back side, using the big face of rugosity Ra value as 1 side of the 1st substrate P, by the small face of rugosity Ra value
As the face for forming lamination tectosome.
Claims (10)
1. a kind of transfer substrate, be at least part lamination tectosome for being transferred substrate transfer and constituting electronic component,
It is characterized by:
It is formed with aforementioned lamination tectosome in the surface of preceding transfer substrate, aforementioned lamination tectosome is to use conductive material
The 1st conductive layer that is formed on preceding transfer substrate is formed in the aforementioned 1st using an at least material for insulating properties and semiconductor and leads
It functional layer in electric layer and is constituted using the 2nd conductive layer that conductive material is formed in aforementioned functional layer,
In aforementioned 2nd conductive layer or aforementioned 1st conductive layer, before being formed with the working process using photo-patterning method to detect
State the alignment mark for being transferred the position of substrate.
2. transfer substrate as described in claim 1, wherein aforementioned functional layer is with insulating layer or semiconductor layer and insulating layer
Two sides constitute.
3. transfer substrate as claimed in claim 1 or 2, wherein in the surface of preceding transfer substrate to cover the big of the surface
The continuous lamination of comprehensive mode is caused to have aforementioned 1st conductive layer, aforementioned functional layer and aforementioned 2nd conductive layer.
4. transfer substrate as claimed in claim 1 or 2, wherein aforementioned 1st conductive layer, aforementioned functional layer and the aforementioned 2nd
Conductive layer any one or all, be with any one of vapor deposition, sputter and CVD formed.
5. transfer substrate as claimed in claim 1 or 2, wherein preceding transfer substrate is flexible base board；
Aforementioned 1st conductive layer, aforementioned functional layer and aforementioned 2nd conductive layer are aforementioned soft to transporting by roll-to-roll mode
Property substrate is formed.
6. transfer substrate as claimed in claim 1 or 2, wherein be equipped between preceding transfer substrate and aforementioned 1st conductive layer
With the peeling layer constituted to the material that alkali is solubility；
Aforementioned peeling layer is removed by the molten coal of alkalinity from aforementioned 1st conductive layer after transfer.
7. transfer substrate as claimed in claim 1 or 2, wherein aforementioned 1st conductive layer is in the formation on preceding transfer substrate
For the element area of aforementioned electronic element similarly or in selectively accumulating in the element area, aforementioned functional layer is in aforementioned
It similarly or is selectively accumulated on 1 conductive layer, aforementioned 2nd conductive layer is in similarly or selectively heap in aforementioned functional layer
Product.
8. a kind of transfer substrate is in order to before transfer is constituted on the product substrate for forming the electronic component comprising semiconductor element
It states at least part lamination tectosome of electronic component and supports aforementioned lamination tectosome, it is characterised in that:
Aforementioned lamination tectosome is from the surface side of aforementioned transfer substrate to use conductive material similarly or selective landform
At the 1st conductive layer, using insulating material or show the material of characteristic of semiconductor similarly or the function that is formed selectively
Layer and using conductive material similarly or the sequential lamination of the 2nd conductive layer that is formed selectively,
Aforementioned 1st conductive layer and the interface of aforementioned functional layer or the interface of aforementioned functional layer and aforementioned 2nd conductive layer, with ultra micro
Rice grade below is flattened.
9. transfer substrate as claimed in claim 8, wherein preceding transfer substrate is constituted with metal material,
Said conductive material is metal material identical with preceding transfer substrate or ITO, and aforementioned functional layer is aforementioned dielectric
Any one of the material of material and aforementioned display characteristic of semiconductor is formed by layer or aforementioned dielectric material and aforementioned display half
The lamination of the material of conductor characteristics.
10. transfer substrate as claimed in claim 8 or 9, wherein the material of preceding transfer substrate is set as copper, before composition
The said conductive material for stating the 1st conductive layer and aforementioned 2nd conductive layer is set as copper.
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| JP2014171246 | 2014-08-26 | ||
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| CN201580045821.XA CN106605294B (en) | 2014-08-26 | 2015-08-24 | Element manufacturing method and transfer substrate |
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| US10586817B2 (en) | 2016-03-24 | 2020-03-10 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device, manufacturing method thereof, and separation apparatus |
| CN108962975A (en) * | 2018-06-26 | 2018-12-07 | 武汉华星光电技术有限公司 | A kind of low-temperature polysilicon film transistor and preparation method thereof, display device |
| KR20210137176A (en) * | 2019-05-20 | 2021-11-17 | 미쓰이금속광업주식회사 | Metal foil having a carrier, and a method for using and manufacturing the same |
| JPWO2021044705A1 (en) * | 2019-09-03 | 2021-03-11 | ||
| TWI715447B (en) * | 2020-02-21 | 2021-01-01 | 友達光電股份有限公司 | Method for fabricating backplane |
| CN112687548A (en) * | 2020-12-25 | 2021-04-20 | 光华临港工程应用技术研发(上海)有限公司 | Preparation method and structure of transferable flexible interconnection structure |
| US11178774B1 (en) | 2021-03-23 | 2021-11-16 | Chung W. Ho | Method for manufacturing circuit board |
| CN114281215A (en) * | 2021-12-28 | 2022-04-05 | 安徽辅朗光学材料有限公司 | Touch panel, touch module and preparation process |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08240814A (en) * | 1995-03-03 | 1996-09-17 | Dainippon Printing Co Ltd | Thin-film transistor and its production and active matrix substrate and its production |
| JP2003031780A (en) * | 2001-06-07 | 2003-01-31 | Ind Technol Res Inst | Method for manufacturing thin film transistor panel |
| CN1492481A (en) * | 2002-09-25 | 2004-04-28 | ������������ʽ���� | Single crystal silicon and SOI base board, semiconductor device and its producing method and display device |
| TW200416966A (en) * | 2002-10-08 | 2004-09-01 | Seiko Epson Corp | Circuit board and its manufacturing method, transfer chip, transfer source substrate, optoelectronic apparatus, and electronic machine |
| JP2005150686A (en) * | 2003-10-22 | 2005-06-09 | Sharp Corp | Semiconductor device and its manufacturing method |
| CN101506985A (en) * | 2006-09-22 | 2009-08-12 | 国产大学法人东北大学 | Semiconductor device and semiconductor device manufacturing method |
| CN103299448A (en) * | 2010-09-29 | 2013-09-11 | Posco公司 | Method for manufacturing a flexible electronic device using a roll-shaped motherboard, flexible electronic device, and flexible substrate |
Family Cites Families (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3738798B2 (en) * | 1997-07-03 | 2006-01-25 | セイコーエプソン株式会社 | Method for manufacturing active matrix substrate and method for manufacturing liquid crystal panel |
| JP4837240B2 (en) * | 2002-09-25 | 2011-12-14 | シャープ株式会社 | Semiconductor device |
| JP4310685B2 (en) * | 2003-09-03 | 2009-08-12 | セイコーエプソン株式会社 | Transfer device |
| JP4651924B2 (en) * | 2003-09-18 | 2011-03-16 | シャープ株式会社 | Thin film semiconductor device and method for manufacturing thin film semiconductor device |
| KR101429098B1 (en) * | 2004-06-04 | 2014-09-22 | 더 보오드 오브 트러스티스 오브 더 유니버시티 오브 일리노이즈 | Methods and devices for fabricating and assembling printable semiconductor elements |
| JP5041686B2 (en) * | 2004-07-30 | 2012-10-03 | 株式会社半導体エネルギー研究所 | Method for peeling thin film integrated circuit and method for manufacturing semiconductor device |
| WO2006011664A1 (en) * | 2004-07-30 | 2006-02-02 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
| JP2007150097A (en) * | 2005-11-29 | 2007-06-14 | Toshiba Corp | Semiconductor device, and method of manufacturing same |
| KR20110028473A (en) * | 2008-06-30 | 2011-03-18 | 가부시키가이샤 니콘 | Method and apparatus for manufacturing display element, method and apparatus for manufacturing thin film transistor, and circuit forming apparatus |
| JP2010238873A (en) * | 2009-03-31 | 2010-10-21 | Panasonic Corp | Flexible semiconductor device and method for manufacturing the same |
| JP5677306B2 (en) * | 2009-09-25 | 2015-02-25 | 出光興産株式会社 | Organic thin film transistor |
| US9117920B2 (en) * | 2011-05-19 | 2015-08-25 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device using oxide semiconductor |
| TW201417191A (en) * | 2012-08-01 | 2014-05-01 | Tokyo Electron Ltd | Method for forming pattern for electronic device, electronic device, and pattern forming device |
| JP6222218B2 (en) * | 2013-02-15 | 2017-11-01 | 株式会社ニコン | Thin film transfer method, thin film transistor manufacturing method, and pixel electrode forming method for liquid crystal display device |
-
2015
- 2015-08-24 CN CN201580045821.XA patent/CN106605294B/en active Active
- 2015-08-24 CN CN201911389514.XA patent/CN111128707B/en active Active
- 2015-08-24 CN CN201910554294.5A patent/CN110379715A/en active Pending
- 2015-08-24 WO PCT/JP2015/073700 patent/WO2016031762A1/en active Application Filing
- 2015-08-24 JP JP2016545518A patent/JP6593336B2/en active Active
- 2015-08-24 KR KR1020177005139A patent/KR102454094B1/en active IP Right Grant
- 2015-08-26 TW TW109102232A patent/TWI760683B/en active
- 2015-08-26 TW TW108115735A patent/TWI777064B/en active
- 2015-08-26 TW TW104127815A patent/TWI662587B/en active
-
2019
- 2019-09-10 JP JP2019164387A patent/JP6897734B2/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08240814A (en) * | 1995-03-03 | 1996-09-17 | Dainippon Printing Co Ltd | Thin-film transistor and its production and active matrix substrate and its production |
| JP2003031780A (en) * | 2001-06-07 | 2003-01-31 | Ind Technol Res Inst | Method for manufacturing thin film transistor panel |
| CN1492481A (en) * | 2002-09-25 | 2004-04-28 | ������������ʽ���� | Single crystal silicon and SOI base board, semiconductor device and its producing method and display device |
| TW200416966A (en) * | 2002-10-08 | 2004-09-01 | Seiko Epson Corp | Circuit board and its manufacturing method, transfer chip, transfer source substrate, optoelectronic apparatus, and electronic machine |
| JP2005150686A (en) * | 2003-10-22 | 2005-06-09 | Sharp Corp | Semiconductor device and its manufacturing method |
| CN101506985A (en) * | 2006-09-22 | 2009-08-12 | 国产大学法人东北大学 | Semiconductor device and semiconductor device manufacturing method |
| CN103299448A (en) * | 2010-09-29 | 2013-09-11 | Posco公司 | Method for manufacturing a flexible electronic device using a roll-shaped motherboard, flexible electronic device, and flexible substrate |
Also Published As
| Publication number | Publication date |
|---|---|
| TWI760683B (en) | 2022-04-11 |
| TWI662587B (en) | 2019-06-11 |
| JPWO2016031762A1 (en) | 2017-06-08 |
| CN106605294B (en) | 2020-01-21 |
| WO2016031762A1 (en) | 2016-03-03 |
| JP6593336B2 (en) | 2019-10-23 |
| KR102454094B1 (en) | 2022-10-14 |
| KR20170048353A (en) | 2017-05-08 |
| JP6897734B2 (en) | 2021-07-07 |
| TW202018789A (en) | 2020-05-16 |
| TW201933449A (en) | 2019-08-16 |
| TWI777064B (en) | 2022-09-11 |
| JP2020074364A (en) | 2020-05-14 |
| CN111128707B (en) | 2023-06-16 |
| CN111128707A (en) | 2020-05-08 |
| CN106605294A (en) | 2017-04-26 |
| TW201621978A (en) | 2016-06-16 |
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