CN110336554A - Tri-state gate circuit - Google Patents
Tri-state gate circuit Download PDFInfo
- Publication number
- CN110336554A CN110336554A CN201910571380.7A CN201910571380A CN110336554A CN 110336554 A CN110336554 A CN 110336554A CN 201910571380 A CN201910571380 A CN 201910571380A CN 110336554 A CN110336554 A CN 110336554A
- Authority
- CN
- China
- Prior art keywords
- phase inverter
- nmos tube
- tri
- input terminal
- output end
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
Abstract
The invention discloses a kind of tri-state gate circuits.Tri-state gate circuit includes the first phase inverter, the first NAND gate, the second phase inverter, the second NAND gate, third phase inverter, the first NMOS tube and the second NMOS tube.It can make the stability that circuit is simple, cost reduces and improve corresponding function using tri-state gate circuit provided by the invention.
Description
Technical field
The present invention relates to electronic technology field more particularly to tri-state gate circuits.
Background technique
Tri-state gate circuit is widely used in electronic technology field, especially integrated circuit, the complexity of circuit and steady
It is qualitative to directly influence chip cost and performance.
Summary of the invention
Present invention seek to address that the deficiencies in the prior art, provide a kind of tri-state gate circuit.
Tri-state gate circuit, including the first phase inverter, the first NAND gate, the second phase inverter, the second NAND gate, third reverse phase
Device, the first NMOS tube and the second NMOS tube:
The input of first phase inverter terminates input terminal B, and output terminates an input terminal of first NAND gate；Described first
One input termination input terminal A of NAND gate, another input terminate the output end of first phase inverter, output termination described second
The input terminal of phase inverter；The input of second phase inverter terminates the output end of first NAND gate, output termination described the
The grid of one NMOS tube；One input termination input terminal A of second NAND gate, another input terminate input terminal B, output termination
The input terminal of the third phase inverter；The input of the third phase inverter terminates the output end of second NAND gate, output end
Connect the grid of second NMOS tube；The grid of first NMOS tube connects the output end of second phase inverter, and drain electrode connects electricity
Source voltage VCC, source electrode meet the drain electrode of second NMOS tube and the output end OUT as tri-state gate circuit；2nd NMOS
The grid of pipe connects the output end of the third phase inverter, and drain electrode connects the source electrode of first NMOS tube and as tri-state gate circuit
Output end OUT, source electrode ground connection.
When the input terminal A of tri-state gate circuit is low level, when input terminal B is low level, the grid of first NMOS tube
Extremely low level, the grid of second NMOS tube are low level, and the output end OUT of tri-state gate circuit is high-impedance state；Work as tri-state
When the input terminal A of gate circuit is low level, when input terminal B is high level, the grid of first NMOS tube is low level, described
The grid of second NMOS tube is low level, and the output end OUT of tri-state gate circuit is high-impedance state；The input terminal A of tri-state gate circuit is
When high level, when input terminal B is low level, the grid of first NMOS tube is high level, the grid of second NMOS tube
For low level, the output end OUT of tri-state gate circuit is high level；When the input terminal A of tri-state gate circuit is high level, input terminal B
When for high level, the grid of first NMOS tube is low level, and the grid of second NMOS tube is high level, tri-state gate electricity
The output end OUT on road is low level.
Detailed description of the invention
Fig. 1 is the circuit diagram of tri-state gate circuit of the invention.
Specific embodiment
The content of present invention is further illustrated below in conjunction with attached drawing.
Tri-state gate circuit, as shown in Figure 1, including the first phase inverter 10, the first NAND gate 20, the second phase inverter 30, second
NAND gate 40, third phase inverter 50, the first NMOS tube 60 and the second NMOS tube 70:
The input of first phase inverter 10 terminates input terminal B, and output terminates an input terminal of first NAND gate 20；It is described
One input termination input terminal A of the first NAND gate 20, another input terminate the output end of first phase inverter 10, output termination
The input terminal of second phase inverter 30；The input of second phase inverter 30 terminates the output end of first NAND gate 20,
Output terminates the grid of first NMOS tube 60；One input termination input terminal A of second NAND gate 40, another input terminal
Input terminal B is met, output terminates the input terminal of the third phase inverter 50；The input termination described second of the third phase inverter 50
The output end of NAND gate 40, output terminate the grid of second NMOS tube 70；The grid of first NMOS tube 60 connects described
The output end of second phase inverter 30, drain electrode meet supply voltage VCC, and source electrode connects the drain electrode of second NMOS tube 70 and as tri-state
The output end OUT of gate circuit；The grid of second NMOS tube 70 connects the output end of the third phase inverter 50, and drain electrode connects described
The source electrode of first NMOS tube 60 and output end OUT as tri-state gate circuit, source electrode ground connection.
When the input terminal A of tri-state gate circuit is low level, when input terminal B is low level, first NMOS tube 60
Grid is low level, and the grid of second NMOS tube 70 is low level, and the output end OUT of tri-state gate circuit is high-impedance state；When
When the input terminal A of tri-state gate circuit is low level, when input terminal B is high level, the grid of first NMOS tube 60 is low electricity
Flat, the grid of second NMOS tube 70 is low level, and the output end OUT of tri-state gate circuit is high-impedance state；Tri-state gate circuit
When input terminal A is high level, when input terminal B is low level, the grid of first NMOS tube 60 is high level, described second
The grid of NMOS tube 70 is low level, and the output end OUT of tri-state gate circuit is high level；The input terminal A of tri-state gate circuit is height
When level, when input terminal B is high level, the grid of first NMOS tube 60 is low level, the grid of second NMOS tube 70
Extremely high level, the output end OUT of tri-state gate circuit are low level.
Claims (1)
1. tri-state gate circuit, it is characterised in that: including the first phase inverter, the first NAND gate, the second phase inverter, the second NAND gate,
Third phase inverter, the first NMOS tube and the second NMOS tube；
The input of first phase inverter terminates input terminal B, and output terminates an input terminal of first NAND gate；Described first
One input termination input terminal A of NAND gate, another input terminate the output end of first phase inverter, output termination described second
The input terminal of phase inverter；The input of second phase inverter terminates the output end of first NAND gate, output termination described the
The grid of one NMOS tube；One input termination input terminal A of first NAND gate, another input terminate input terminal B, output termination
The input terminal of the third phase inverter；The input of the third phase inverter terminates the output end of second NAND gate, output end
Connect the grid of second NMOS tube；The grid of first NMOS tube connects the output end of second phase inverter, and drain electrode connects electricity
Source voltage VCC, source electrode meet the drain electrode of second NMOS tube and the output end OUT as tri-state gate circuit；2nd NMOS
The grid of pipe connects the output end of the third phase inverter, and drain electrode connects the source electrode of first NMOS tube and as tri-state gate circuit
Output end OUT, source electrode ground connection.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910571380.7A CN110336554A (en) | 2019-06-28 | 2019-06-28 | Tri-state gate circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910571380.7A CN110336554A (en) | 2019-06-28 | 2019-06-28 | Tri-state gate circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110336554A true CN110336554A (en) | 2019-10-15 |
Family
ID=68143514
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910571380.7A Pending CN110336554A (en) | 2019-06-28 | 2019-06-28 | Tri-state gate circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110336554A (en) |
-
2019
- 2019-06-28 CN CN201910571380.7A patent/CN110336554A/en active Pending
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| WD01 | Invention patent application deemed withdrawn after publication | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20191015 |