CN110830031A - Three-state gate - Google Patents
Three-state gate Download PDFInfo
- Publication number
- CN110830031A CN110830031A CN201910997676.5A CN201910997676A CN110830031A CN 110830031 A CN110830031 A CN 110830031A CN 201910997676 A CN201910997676 A CN 201910997676A CN 110830031 A CN110830031 A CN 110830031A
- Authority
- CN
- China
- Prior art keywords
- inverter
- input end
- output end
- gate
- nmos tube
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
Abstract
The invention discloses a tri-state gate. A tri-state gate comprises a first phase inverter, a first NAND gate, a second phase inverter, a third phase inverter, a fourth phase inverter, a first NMOS transistor and a second NMOS transistor. The tri-state gate provided by the invention can reduce the complexity of the circuit and improve the stability.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a tri-state gate.
Background
The tri-state gate is widely applied to integrated circuits, and the complexity and stability of the circuit directly affect the cost and performance of the chip.
Disclosure of Invention
The present invention is directed to solving the deficiencies of the prior art and providing a tri-state gate.
A kind of three state gate, including the first inverter, the first NAND gate, the second inverter, the third inverter, the fourth inverter, the first NMOS pipe and the second NMOS pipe:
the input end of the first inverter is connected with the input end A, and the output end of the first inverter is connected with one input end of the first NAND gate; one input end of the first NAND gate is connected with the output end of the first inverter, the other input end of the first NAND gate is connected with the output end of the third inverter and the input end of the fourth inverter, and the output end of the first NAND gate is connected with the input end of the second inverter; the input end of the second inverter is connected with the output end of the first NAND gate, and the output end of the second inverter is connected with the grid electrode of the first NMOS tube; the input end of the third inverter is connected with the input end B, and the output end of the third inverter is connected with the input end of the fourth inverter and one input end of the first NAND gate; the input end of the fourth inverter is connected with the output end of the third inverter and one input end of the first NAND gate, and the output end of the fourth inverter is connected with the grid electrode of the second NMOS tube; the grid electrode of the first NMOS tube is connected with the output end of the second phase inverter, the drain electrode of the first NMOS tube is connected with a power supply voltage VCC, and the source electrode of the first NMOS tube is connected with the drain electrode of the second NMOS tube and serves as the output end OUT of the tri-state gate; the grid electrode of the second NMOS tube is connected with the output end of the fourth phase inverter, the drain electrode of the second NMOS tube is connected with the source electrode of the first NMOS tube and serves as the output end OUT of the tri-state gate, and the source electrode of the second NMOS tube is grounded.
When the input end A of the tri-state gate is at a low level and the input end B is at a low level, the grid of the first NMOS tube is at a high level, the grid of the second NMOS tube is at a low level, and the output end OUT of the tri-state gate is at a high level; when the input end A of the tri-state gate is at a low level and the input end B is at a high level, the grid of the first NMOS tube is at a low level, the grid of the second NMOS tube is at a high level, and the output end OUT of the tri-state gate is at a low level; when the input end A of the tri-state gate is at a high level and the input end B is at a low level, the grid of the first NMOS tube is at a low level, the grid of the second NMOS tube is at a low level, and the output end OUT of the tri-state gate is at a high-resistance state; when the input end A of the tri-state gate is at a high level and the input end B is at a high level, the grid of the first NMOS tube is at a low level, the grid of the second NMOS tube is at a high level, and the output end OUT of the tri-state gate is at a low level.
Drawings
FIG. 1 is a circuit diagram of a tri-state gate of the present invention.
Detailed Description
The present invention will be further explained with reference to the accompanying drawings.
A tristate gate, as shown in FIG. 1, comprises a first inverter 10, a first NAND gate 20, a second inverter 30, a third inverter 40, a fourth inverter 50, a first NMOS transistor 60 and a second NMOS transistor 70:
the input end of the first inverter 10 is connected with the input end a, and the output end is connected with one input end of the first nand gate 20; one input end of the first nand gate 20 is connected to the output end of the first inverter 10, the other input end is connected to the output end of the third inverter 40 and the input end of the fourth inverter 50, and the output end is connected to the input end of the second inverter 30; the input end of the second inverter 30 is connected with the output end of the first nand gate 20, and the output end is connected with the gate of the first NMOS transistor 60; the input end of the third inverter 40 is connected to the input end B, and the output end is connected to the input end of the fourth inverter 50 and an input end of the first nand gate 20; the input end of the fourth inverter 50 is connected to the output end of the third inverter 40 and an input end of the first nand gate 20, and the output end is connected to the gate of the second NMOS transistor 70; the gate of the first NMOS transistor 60 is connected to the output terminal of the second inverter 30, the drain is connected to the power supply voltage VCC, and the source is connected to the drain of the second NMOS transistor 70 and serves as the output terminal OUT of the tri-state gate; the gate of the second NMOS transistor 70 is connected to the output terminal of the fourth inverter 50, the drain is connected to the source of the first NMOS transistor 60 and serves as the output terminal OUT of the tri-state gate, and the source is grounded.
When the input end a of the tri-state gate is at a low level and the input end B is at a low level, the gate of the first NMOS transistor 60 is at a high level, the gate of the second NMOS transistor 70 is at a low level, and the output end OUT of the tri-state gate is at a high level; when the input end a of the tri-state gate is at a low level and the input end B is at a high level, the gate of the first NMOS transistor 60 is at a low level, the gate of the second NMOS transistor 70 is at a high level, and the output end OUT of the tri-state gate is at a low level; when the input end a of the tri-state gate is at a high level and the input end B is at a low level, the gate of the first NMOS transistor 60 is at a low level, the gate of the second NMOS transistor 70 is at a low level, and the output end OUT of the tri-state gate is at a high impedance state; when the input end a of the tri-state gate is at a high level and the input end B is at a high level, the gate of the first NMOS transistor 60 is at a low level, the gate of the second NMOS transistor 70 is at a high level, and the output end OUT of the tri-state gate is at a low level.
Claims (1)
1. A tri-state gate, comprising: comprises a first inverter, a first NAND gate, a second inverter, a third inverter,
The fourth phase inverter, the first NMOS tube and the second NMOS tube;
the input end of the first inverter is connected with the input end A, and the output end of the first inverter is connected with one input end of the first NAND gate; one input end of the first NAND gate is connected with the output end of the first inverter, the other input end of the first NAND gate is connected with the output end of the third inverter and the input end of the fourth inverter, and the output end of the first NAND gate is connected with the input end of the second inverter; the input end of the second inverter is connected with the output end of the first NAND gate, and the output end of the second inverter is connected with the grid electrode of the first NMOS tube; the input end of the third inverter is connected with the input end B, and the output end of the third inverter is connected with the input end of the fourth inverter and one input end of the first NAND gate; the input end of the fourth inverter is connected with the output end of the third inverter and one input end of the first NAND gate, and the output end of the fourth inverter is connected with the grid electrode of the second NMOS tube; the grid electrode of the first NMOS tube is connected with the output end of the second phase inverter, the drain electrode of the first NMOS tube is connected with a power supply voltage VCC, and the source electrode of the first NMOS tube is connected with the drain electrode of the second NMOS tube and serves as the output end OUT of the tri-state gate; the grid electrode of the second NMOS tube is connected with the output end of the fourth phase inverter, the drain electrode of the second NMOS tube is connected with the source electrode of the first NMOS tube and serves as the output end OUT of the tri-state gate, and the source electrode of the second NMOS tube is grounded.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910997676.5A CN110830031A (en) | 2019-10-21 | 2019-10-21 | Three-state gate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910997676.5A CN110830031A (en) | 2019-10-21 | 2019-10-21 | Three-state gate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110830031A true CN110830031A (en) | 2020-02-21 |
Family
ID=69549820
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910997676.5A Pending CN110830031A (en) | 2019-10-21 | 2019-10-21 | Three-state gate |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110830031A (en) |
-
2019
- 2019-10-21 CN CN201910997676.5A patent/CN110830031A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105958822B (en) | Voltage conversion circuit | |
| CN105471409B (en) | Low area flip-flop with shared inverter | |
| CN107181482A (en) | input and output receiving circuit | |
| CN104836570B (en) | It is a kind of based on transistor level and/NOR gate circuit | |
| WO2021121107A1 (en) | Logic circuit design method | |
| CN110830031A (en) | Three-state gate | |
| CN103501173A (en) | Pull-up resistor circuit for preventing inverse current transmission and input-output port circuit | |
| CN105375916A (en) | Improved XOR gate logic unit circuit | |
| CN110620580A (en) | Three-state gate circuit | |
| CN110708059A (en) | Three-state gate | |
| CN212392867U (en) | Power rail switching circuit | |
| CN110708057A (en) | Three-state gate | |
| CN205039798U (en) | Output circuit of compatible PECLTTLCMOS level | |
| CN110620579A (en) | Three-state gate circuit | |
| CN110784209A (en) | Three-state gate device | |
| CN110336554A (en) | Tri-state gate circuit | |
| CN110737226A (en) | MTP high-voltage burning pin circuit structure | |
| CN207782386U (en) | One kind preventing leakage circuit after chip power-down | |
| CN108923777A (en) | The inverter module of radiation hardened | |
| CN109450437A (en) | A kind of tri-state gate circuit | |
| CN209488553U (en) | A kind of cmos circuit structure | |
| CN210518265U (en) | Drive circuit of level conversion module | |
| CN109547012A (en) | A kind of tri-state gate circuit | |
| CN109245760A (en) | Tri-state door gear | |
| CN104601160A (en) | Built-in electrostatic protection device type high-speed output circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20200221 |
|
| WD01 | Invention patent application deemed withdrawn after publication |