CN110336262B - Surge protection circuit - Google Patents
Surge protection circuit Download PDFInfo
- Publication number
- CN110336262B CN110336262B CN201910620110.0A CN201910620110A CN110336262B CN 110336262 B CN110336262 B CN 110336262B CN 201910620110 A CN201910620110 A CN 201910620110A CN 110336262 B CN110336262 B CN 110336262B
- Authority
- CN
- China
- Prior art keywords
- surge
- voltage
- diode
- series module
- protection circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
- H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
- H02H9/045—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere
Abstract
The application provides a surge protection circuit, which comprises a series module and a surge discharge unit; when the series module and the surge relief unit respectively meet corresponding relief requirements, the received surge voltage is relieved to the ground, so that the input voltage of the electronic equipment is clamped at the safe working voltage of the electronic equipment, and the safe working of the electronic equipment is ensured; in addition, compare with prior art, this application has established ties the parasitic capacitance of a series module for it on the parasitic capacitance's of surge bleeder unit basis, and the parasitic capacitance of series module is less than the parasitic capacitance of surge bleeder unit for surge protection circuit's total parasitic capacitance reduces, and distortion to high-speed signal reduces, consequently makes the surge protection circuit that this application provided can be applied to the high-speed port.
Description
Technical Field
The invention relates to the technical field of power electronics, in particular to a surge protection circuit.
Background
The surge voltage is instantaneous overvoltage exceeding working voltage, and has the characteristics of large voltage, extremely short generation time and the like. When power grid fluctuation, electrostatic discharge and the like occur, surge voltage is easily generated at a port of electronic equipment, such as a charging port of the electronic equipment; if the surge voltage exceeds the withstand capability of the port of the electronic device, it may have a destructive effect on the electronic device.
In order to protect the charging port of the electronic device, a TVS (Transient Voltage Suppressor) diode is generally connected in parallel between the charging port of the electronic device and ground, or an IC having a surge protection function is applied to the charging port of the electronic device. When the surge voltage Vsurge occurs, as shown in fig. 1, the surge voltage is discharged to the ground through a TVS transient surge suppression diode or an Integrated Circuit (IC) having a surge protection function, and the input voltage of the charging port is clamped at the clamp voltage Vclamp, so as to ensure the safe operation of the corresponding electronic device.
However, the surge protection circuit in the prior art can only be applied to a low-speed port, i.e., a port with relatively stable voltage, such as a charging port; when applied to a high-speed port, such as a data port, a high-speed signal may be distorted, which may affect data transmission of an electronic device.
Disclosure of Invention
In view of this, embodiments of the present invention provide a surge protection circuit to solve the problem that the surge protection circuit in the prior art cannot be applied to a high-speed port.
In order to achieve the above purpose, the embodiments of the present invention provide the following technical solutions:
the application provides a surge protection circuit is applied to electronic equipment, includes: the surge relief unit is connected with the series module; wherein:
the output end of the series module is connected with the input end of the surge discharge unit; the input end of the series module receives surge voltage, and the output end of the surge bleeder unit is grounded;
when the series module and the surge bleeding unit respectively meet corresponding bleeding requirements, the series module and the surge bleeding unit bleed the surge voltage to the ground;
the parasitic capacitance of the series module is smaller than that of the surge bleeder unit.
Optionally, the series module includes: the first switch tube and the first diode; wherein:
the first switch tube is connected with the first diode in parallel in the opposite direction.
Optionally, the first switch tube is an isolated low-voltage tube.
Optionally, the first diode is a parasitic diode of the first switching tube.
Optionally, the first switch tube is an N-type metal-oxide-semiconductor field effect transistor NMOS transistor;
the cathode of the first diode is connected with the grid electrode and the drain electrode of the NMOS transistor, and the connection point is used as the input end of the series module;
and the anode of the first diode is connected with the source electrode of the NMOS transistor, and the connection point is used as the output end of the series module.
Optionally, the first switching tube is a P-type metal-oxide-semiconductor field effect transistor NMOS transistor;
the cathode of the first diode is connected with the source electrode of the PMOS transistor, and the connection point is used as the input end of the series module;
and the anode of the first diode is connected with the grid electrode and the drain electrode of the PMOS transistor, and the connection point is used as the output end of the series module.
Optionally, the surge bleeding unit includes: the second switch tube, the second diode, the voltage stabilizing diode and the grounding resistor; wherein:
the input end of the second switching tube is connected with the cathode of the second diode and the cathode of the voltage stabilizing diode, and the connection point is used as the input end of the surge discharge unit;
the anode of the voltage stabilizing diode is connected with one end of the grounding resistor, and the connecting point is connected with the control end of the second switch tube;
the output end of the second switch tube is connected with the other end of the grounding resistor, and the connection point is used as the output end of the surge unit.
Optionally, the series module and the surge bleeding unit are integrated in an integrated circuit.
Optionally, the second switch tube is a high-voltage NMOS transistor.
Optionally, the surge bleeding unit includes: the transient suppression diode TVS.
The application provides a surge protection circuit, which comprises a series module and a surge discharge unit; when the series module and the surge relief unit respectively meet corresponding relief requirements, the received surge voltage is relieved to the ground, so that the input voltage of the electronic equipment is clamped at the safe working voltage of the electronic equipment, and the safe working of the electronic equipment is ensured; in addition, compare with prior art, this application has established ties the parasitic capacitance of a series module for it on the parasitic capacitance's of surge bleeder unit basis, and the parasitic capacitance of series module is less than the parasitic capacitance of surge bleeder unit for surge protection circuit's total parasitic capacitance reduces, and distortion to high-speed signal reduces, consequently makes the surge protection circuit that this application provided can be applied to the high-speed port.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
FIG. 1 is a schematic diagram of a surge voltage and a voltage at an input port with a surge protection device in the prior art;
fig. 2 is a schematic diagram of a surge protection circuit in the prior art;
fig. 3 is a simulation experiment data diagram obtained by performing a simulation experiment on a surge protection circuit in the prior art;
fig. 4 is a schematic diagram of a surge protection circuit according to an embodiment of the present application;
FIG. 5 is a schematic diagram of an embodiment of a series module according to another embodiment of the present application;
FIG. 6 is a schematic diagram of an embodiment of a series module according to another embodiment of the present application;
fig. 7 is a schematic diagram of an implementation of a surge relief unit according to another embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In this application, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
In the prior art, a specific structure of a surge protection circuit is shown in fig. 2, and includes: a series branch 10, a voltage-dividing resistor R and a switch tube M.
The input end of the series branch 10 is connected with the input port of the electronic device and receives a surge voltage Vsurge; the output end of the series branch 10 is connected to one end of the voltage dividing resistor R, and the connection point is denoted as point a. The series branch 10 is composed of N zener diodes, wherein the N zener diodes are respectively represented as Z1-Zn, and N is an integer not less than 1; the N voltage-stabilizing diodes are sequentially connected in series, the serially connected negative electrode serves as the input end of the serial branch circuit, and the serially connected positive electrode serves as the output end of the serial branch circuit; in addition, the reverse breakdown voltages of the N voltage stabilizing diodes are the same and are all VBR. When the surge voltage Vsurge is less than or equal to N times the reverse breakdown voltage N × VBR, that is, Vsurge ≦ N × VBR, the serial branch 10 is not broken down; when the surge voltage Vsurge is greater than N times the reverse breakdown voltage VBR, i.e., Vsurge > N × VBR, the series branch 10 is broken down.
The other end of the divider resistor R is grounded GND. When the series branch 10 is not broken down, no current flows through the voltage dividing resistor R, and no voltage is generated at the two ends of the voltage dividing resistor R; when the series branch 10 is broken down, a current flows through the voltage-dividing resistor R, and then a voltage is generated across the voltage-dividing resistor R, and the voltage Vr across the voltage-dividing resistor R increases with the increase of the current flowing through the voltage-dividing resistor R, that is, the voltage Vr across the voltage-dividing resistor R increases with the increase of the surge voltage Vsurge.
The input end of the switching tube M is connected with the input end of the series branch 10; the control end of the switching tube M is connected with the point A; the output end of the switch tube M is connected with the other end of the divider resistor R. When the voltage Vr at the two ends of the voltage dividing resistor R is smaller than or equal to the threshold voltage Vth _ M of the switching tube M, namely Vr is less than or equal to Vth _ M, the switching tube M is turned off, and the surge voltage Vsurge is not released; when the voltage Vr at the two ends of the divider resistor R is greater than the threshold voltage Vth _ M of the switching tube M, that is, Vr > Vth _ M, the switching tube M is turned on, the surge voltage Vsurge is discharged to the ground GND, and the input voltage VIN of the input port of the electronic device is clamped in the safe working voltage range.
For better explanation, a simulation experiment is performed on an electronic device with a surge protection circuit in practical application, the result of the simulation experiment is shown in fig. 3, when a surge voltage Vsurge exceeds 37V, a control terminal voltage NGATE of a switching tube M is greater than a threshold voltage Vth _ M of the switching tube M, the switching tube M is turned on, the surge protection circuit starts to work, the surge voltage Vsurge is discharged to a ground GND, and an input voltage VIN of the electronic device is clamped at about 37V, so that the electronic device is ensured not to be damaged by the surge voltage; and the surge current IIN varies with the variation of the surge voltage.
However, when the surge protection circuit is applied to a high-speed port, that is, a port capable of transmitting a high-speed signal during normal operation, the parasitic capacitance of the surge protection circuit to the ground GND is large, so that the high-speed signal passing through the high-speed port is distorted, and the normal transmission of the high-speed signal is affected; therefore, the surge protection circuit in the prior art cannot be applied to a high-speed port.
In order to solve the problem that the surge protection circuit in the prior art cannot be applied to a high-speed port, the present application provides a surge protection circuit, and the specific structure is as shown in fig. 4, including: a tandem module 100 and a surge relief unit 200.
The output end of the series module 100 is connected with the input end of the surge bleed-off unit 200; the input end of the series module receives the surge voltage Vsurge, and the output end of the surge discharging unit 200 is grounded to GND.
When the series module 100 and the surge bleeding unit 200 respectively satisfy the corresponding bleeding requirements, the series module 100 and the surge bleeding unit 200 bleed the surge voltage Vsurge to the ground GND.
If the surge voltage Vsurge is a positive voltage, the discharging requirement of the series module 100 is: the surge voltage Vsurge is greater than the first threshold voltage Vth1, i.e., Vsurge > Vth 1; when the series module 100 meets the discharge requirement, discharging the surge voltage Vsurge to the input end of the surge discharge unit 200; when the series module 100 cannot meet the bleeding requirement, the surge voltage Vsurge is not bled.
If the surge voltage Vsurge is a positive voltage, the discharge requirement of the surge discharge unit 200 is: the surge voltage Vsurge is greater than the second threshold voltage Vth2, i.e., Vsurge > Vth 2; when the surge discharging unit 200 meets the discharging requirement, discharging the surge voltage Vsurge to the ground GND; when the surge bleeding unit 200 cannot meet the bleeding requirement, the surge voltage Vsurge is not bled.
If the surge voltage Vsurge is a negative voltage, both the series module 100 and the surge bleeding unit 200 satisfy the bleeding requirement, and the surge voltage Vsurge is discharged to the ground.
Note that, the first threshold voltage Vth1 and the second threshold voltage Vth2 are both positive voltages; the first threshold voltage Vth1 and the second threshold voltage Vth2 are selected according to the safe operating voltage of the input port in practical application and in combination with practical situations; in addition, the first threshold voltage Vth1 may be smaller than the second threshold voltage Vth2, or may be equal to or greater than the second threshold voltage Vth2, which is not limited herein and is within the protection scope of the present application; however, the magnitude relationship between the first threshold voltage Vth1 and the second threshold voltage Vth2 is preferably: the first threshold voltage Vth1 is less than the second threshold voltage Vth2, i.e., Vth1< Vth 2.
Optionally, the series module 110 and the surge bleed-off unit 200 may be integrated in an integrated circuit, or may be composed of discrete devices; when composed of discrete devices, the surge bleed-off unit 200 may also be composed of a TVS (Transient Voltage Suppressor) alone.
In addition, the parasitic capacitance of series module 100 is less than the parasitic capacitance of surge bleed unit 200.
It should be noted that, the series module 100 is connected in series with the surge relief unit 200, and the parasitic capacitance of the series module 100 is smaller than the parasitic capacitance of the surge relief unit 200, which is equivalent to connecting a smaller parasitic capacitance in series on the basis of the parasitic capacitance of the surge relief unit 200, that is, the parasitic capacitance of the series module 100, so according to the calculation formula of the series capacitance, it can be deduced that: the total parasitic capacitance after series connection is less than the parasitic capacitance of the series module 100.
When the series module 100 and the surge bleeding unit 200 respectively meet the corresponding bleeding requirements, the surge protection circuit provided by this embodiment bleeds the received surge voltage Vsurge to the ground, so that the input voltage of the electronic device is clamped at the safe working voltage of the electronic device, and the safe working of the electronic device is ensured; in addition, compare with prior art, this application is on surge bleeder unit 200's parasitic capacitance's basis, the parasitic capacitance of series module 100, and the parasitic capacitance of series module 100 is less than surge bleeder unit 200's parasitic capacitance for surge protection circuit's total parasitic capacitance reduces, and distortion to high-speed signal influences and reduces, makes the surge protection circuit that this application provided can be applied to high-speed port, for example USB D +/D-, type CSBU.
In another embodiment of the present application, an embodiment of a serial module 100 is provided, and the specific structure is as shown in fig. 5 or fig. 6, including: a first switch transistor M1 and a first diode D1.
As shown in fig. 5, if the first switch M1 is an NMOS transistor (N-Metal-Oxide-Semiconductor field effect transistor), the cathode of the first diode D1 is connected to both the gate and the drain of the NMOS transistor, and the connection point is used as the input end of the series module 100; the anode of the first diode D1 is connected to the source of the NMOS transistor, and the connection point is the output terminal of the series module 100.
When the surge voltage Vsurge is a positive voltage, the first diode D1 is turned off in the reverse direction, and when the surge voltage Vsurge is a positive voltage and is greater than the threshold voltage Vth _ N of the NMOS transistor, that is, Vsurge > Vth _ N, the NMOS transistor is turned on, and outputs the surge voltage Vsurge to the input terminal of the surge bleeder unit 200; when the surge voltage Vsurge is a positive voltage and is less than or equal to the threshold voltage Vth _ N of the NMOS transistor, that is, Vsurge ≦ Vth _ N, the NMOS transistor is turned off, and the surge voltage Vsurge cannot be released.
Note that the first threshold voltage Vth1 is equal to the threshold voltage Vth _ N of the NMOS transistor, that is, Vth1 is equal to Vth _ N, so that the first threshold voltage Vth1 can be adjusted by adjusting the threshold voltage Vth _ N of the NMOS transistor.
As shown in fig. 6, if the first switch M1 is a PMOS transistor (P-Metal-Oxide-Semiconductor field effect transistor), the cathode of the first diode D1 is connected to the source of the PMOS transistor, and the connection point is used as the input end of the series module 100; and, the anode of the first diode D1 is connected to the gate and the drain of the PMOS transistor, and the connection point is the output terminal of the series module 100.
When the surge voltage Vsurge is a positive voltage, the first diode D1 is turned off in the reverse direction, and when the surge voltage Vsurge is a positive voltage and is greater than the absolute value of the threshold voltage of the PMOS transistor, i.e., Vsurge > | Vth _ P |, the PMOS transistor is turned on, outputting the surge voltage Vsurge to the surge discharging unit 200; when the surge voltage Vsurge is a positive voltage and is less than or equal to the absolute value of the threshold voltage of the PMOS transistor, i.e., Vsurge ≦ | Vth _ P |, the PMOS transistor turns off, and the surge voltage Vsurge cannot be discharged.
Note that the first threshold voltage Vth1 is equal to the absolute value | Vth _ P | of the threshold voltage of the PMOS transistor, that is, Vth1 | Vth _ P |, so the first threshold voltage Vth1 can be adjusted by adjusting the threshold voltage | Vth _ P | of the PMOS transistor.
Optionally, the NMOS transistor and the PMOS transistor are isolated low voltage transistors; the first diode D1 is a parasitic diode of the first switch tube M1.
The rest of the structure and the working principle are the same as those of the above embodiments, and are not described in detail here.
In another embodiment of the present invention, an implementation of a surge relief unit 200 is provided, and the specific structure is as shown in fig. 7, including: a second switch tube M2, a second diode D2, a zener diode Z and a ground resistor R.
The input end of the second switching tube M2 is connected to both the cathode of the second diode D2 and the cathode of the zener diode Z, and the connection point is used as the input end of the surge discharging unit 200; the anode of the voltage-stabilizing diode Z and one end of the grounding resistor R are both connected, and the connecting point is connected with the control end of the second open-hanging tube M2; the output end of the second switching tube M2 is connected with the other end of the ground resistor R, and the connection point is used as the output end of the surge discharging unit.
If the surge voltage Vsurge is a positive voltage, the second switching tube M2 is not turned on before the zener diode Z is reversely broken down by the surge voltage Vsurge, and the surge voltage Vsurge cannot be discharged; after the voltage stabilizing diode Z is reversely broken down by the surge voltage Vsurge, current flows through the grounding resistor R, and voltage VR is generated on the grounding resistor R; when the voltage VR is greater than the threshold voltage Vth _ M2 of the second switching tube M2, that is, VR > Vth _ M2, a turn-on signal is output to the control terminal of the second switching tube M2 to turn on the second switching tube M2, and the surge voltage is discharged to the ground GND; when the voltage VR is less than or equal to the threshold voltage Vth _ M2 of the second switching tube M2, i.e., VR ≦ Vth _ M2, the off signal is output to the control terminal of the second switching tube M2, so that the second switching tube M2 cannot release the surge voltage Vsurge.
When the surge voltage Vsurge is a negative voltage, the first diode D1 and the second diode D2 are turned on, and the surge voltage Vsurge is discharged to the ground GND.
It should be noted that the second threshold voltage Vth2 is equal to the sum of the conduction voltage drop of the first switching tube M1, the reverse breakdown voltage VBR of the zener diode Z, and the threshold voltage Vth _ M2 of the second switching tube M2, that is, Vth2 is Vds _ M1+ VBR + Vth _ M2, so that the second threshold voltage Vth2 can be adjusted by adjusting the reverse breakdown voltage VBR of the zener diode Z and/or the threshold voltage Vth _ M2 of the second switching tube M2 when the conduction voltage drop of the first switching tube M1 is constant.
Optionally, the zener diode Z may be replaced by a zener branch formed by sequentially connecting N zener diodes in series, where N is an integer greater than or equal to 1; other components or circuits that perform the same function may be substituted for the above components or circuits, and are not particularly limited herein.
Optionally, since the input port generally requires a certain voltage endurance capability, the second switching tube M2 needs to be a high voltage NMOS transistor, and may also be another element that achieves the same function as the isolated high voltage NMOS transistor, which is not limited herein.
It should be noted that the parasitic capacitance to ground of the original surge bleeding unit 200 is Cbig, and the parasitic capacitance of the first switching tube M1 to the output end of the series module 100 is Csmall, so that the total capacitance after the two are connected in series is smaller than Csmall, that is, the capacitance is reduced as a result of the series connection. Since the first switch tube M1 in the above embodiment is in a diode connection manner, and the first switch tube M1 may be an isolated low-voltage switch tube, the overcurrent capability of the first switch tube M1 is stronger, and further the size of the first switch tube M1 is smaller than that of the second switch tube M2, so that the parasitic capacitance of the first switch tube M1 is much smaller than that of the second switch tube M2, that is, the parasitic capacitance of the series module 100 is much smaller than that of the surge bleeder unit 200.
It should be noted that this embodiment merely provides a specific implementation of the surge relief unit, and other implementations that achieve the same function are within the protection scope of this embodiment.
The rest of the structure and the working principle are the same as those of the above embodiments, and are not described in detail here.
The embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, the system or system embodiments are substantially similar to the method embodiments and therefore are described in a relatively simple manner, and reference may be made to some of the descriptions of the method embodiments for related points. The above-described system and system embodiments are only illustrative, wherein the units described as separate parts may or may not be physically separate, and the parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment. One of ordinary skill in the art can understand and implement it without inventive effort.
Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative components and steps have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (7)
1. A surge protection circuit applied to an electronic device, comprising: the surge relief unit is connected with the series module; wherein:
the output end of the series module is connected with the input end of the surge discharge unit; the input end of the series module receives surge voltage, and the output end of the surge bleeder unit is grounded;
when the series module and the surge bleeding unit respectively meet corresponding bleeding requirements, the series module and the surge bleeding unit bleed the surge voltage to the ground;
the tandem module, comprising: the first switch tube and the first diode; wherein: the first switch tube is connected with the first diode in parallel in the opposite direction;
the surge bleed-off unit comprises: the second switch tube, the second diode, the voltage stabilizing diode and the grounding resistor; wherein: the input end of the second switching tube is connected with the cathode of the second diode and the cathode of the voltage stabilizing diode, and the connection point is used as the input end of the surge discharge unit; the anode of the voltage stabilizing diode is connected with one end of the grounding resistor, and the connecting point is connected with the control end of the second switch tube; the output end of the second switching tube is connected with the other end of the grounding resistor and the anode of the second diode, and the connection point is used as the output end of the surge discharge unit;
the parasitic capacitance of the series module is smaller than that of the surge bleeder unit.
2. The surge protection circuit of claim 1, wherein the first switching tube is an isolated low voltage tube.
3. The surge protection circuit of claim 1, wherein the first diode is a parasitic diode of the first switching tube.
4. The surge protection circuit of claim 1, wherein the first switching transistor is an NMOS transistor;
the cathode of the first diode is connected with the grid electrode and the drain electrode of the NMOS transistor, and the connection point is used as the input end of the series module;
and the anode of the first diode is connected with the source electrode of the NMOS transistor, and the connection point is used as the output end of the series module.
5. The surge protection circuit of claim 1, wherein the first switching transistor is a P-type metal-oxide-semiconductor field effect transistor (PMOS) transistor;
the cathode of the first diode is connected with the source electrode of the PMOS transistor, and the connection point is used as the input end of the series module;
and the anode of the first diode is connected with the grid electrode and the drain electrode of the PMOS transistor, and the connection point is used as the output end of the series module.
6. The surge protection circuit of claim 1, wherein the series module and the surge bleed unit are integrated in an integrated circuit.
7. The surge protection circuit of claim 1, wherein the second switching tube is a high voltage NMOS transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910620110.0A CN110336262B (en) | 2019-07-10 | 2019-07-10 | Surge protection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910620110.0A CN110336262B (en) | 2019-07-10 | 2019-07-10 | Surge protection circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110336262A CN110336262A (en) | 2019-10-15 |
| CN110336262B true CN110336262B (en) | 2021-11-12 |
Family
ID=68146156
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910620110.0A Active CN110336262B (en) | 2019-07-10 | 2019-07-10 | Surge protection circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110336262B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112234594B (en) * | 2020-10-09 | 2023-11-10 | 清华大学深圳国际研究生院 | Surge protection system and method |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201160222Y (en) * | 2008-02-21 | 2008-12-03 | 中兴通讯股份有限公司 | Second-generation extremely high speed digital subscriber line protection circuit |
| CN101436592A (en) * | 2007-11-12 | 2009-05-20 | 恩益禧电子股份有限公司 | Semiconductor integrated circuit |
| CN201898328U (en) * | 2010-11-30 | 2011-07-13 | 百圳君耀电子（深圳）有限公司 | Semiconductor surge protection device |
| CN102176624A (en) * | 2011-03-11 | 2011-09-07 | 上海长园维安微电子有限公司 | Low-capacitance low-clamping overvoltage protection device |
| CN102460955A (en) * | 2009-06-09 | 2012-05-16 | 高通股份有限公司 | Capacitor switching circuit |
| CN105789332A (en) * | 2016-04-25 | 2016-07-20 | 矽力杰半导体技术(杭州)有限公司 | Rectifying device, manufacturing method thereof and electro-static discharge (ESD) protection device |
| CN106449634A (en) * | 2016-09-23 | 2017-02-22 | 矽力杰半导体技术(杭州)有限公司 | Transient voltage suppressor and manufacturing method therefor |
| CN109301806A (en) * | 2018-11-08 | 2019-02-01 | 上海艾为电子技术股份有限公司 | A kind of surge protection circuit |
| CN109473426A (en) * | 2019-01-17 | 2019-03-15 | 上海艾为电子技术股份有限公司 | Electrostatic discharge circuit and electronic equipment |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006303110A (en) * | 2005-04-19 | 2006-11-02 | Nec Electronics Corp | Semiconductor device |
| KR100651579B1 (en) * | 2005-11-15 | 2006-11-29 | 매그나칩 반도체 유한회사 | Esd protection circuit |
| CN108880212B (en) * | 2018-06-30 | 2021-07-20 | 唯捷创芯(天津)电子技术股份有限公司 | Surge-proof power supply clamping circuit, chip and communication terminal |
-
2019
- 2019-07-10 CN CN201910620110.0A patent/CN110336262B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101436592A (en) * | 2007-11-12 | 2009-05-20 | 恩益禧电子股份有限公司 | Semiconductor integrated circuit |
| CN201160222Y (en) * | 2008-02-21 | 2008-12-03 | 中兴通讯股份有限公司 | Second-generation extremely high speed digital subscriber line protection circuit |
| CN102460955A (en) * | 2009-06-09 | 2012-05-16 | 高通股份有限公司 | Capacitor switching circuit |
| CN201898328U (en) * | 2010-11-30 | 2011-07-13 | 百圳君耀电子（深圳）有限公司 | Semiconductor surge protection device |
| CN102176624A (en) * | 2011-03-11 | 2011-09-07 | 上海长园维安微电子有限公司 | Low-capacitance low-clamping overvoltage protection device |
| CN105789332A (en) * | 2016-04-25 | 2016-07-20 | 矽力杰半导体技术(杭州)有限公司 | Rectifying device, manufacturing method thereof and electro-static discharge (ESD) protection device |
| CN106449634A (en) * | 2016-09-23 | 2017-02-22 | 矽力杰半导体技术(杭州)有限公司 | Transient voltage suppressor and manufacturing method therefor |
| CN109301806A (en) * | 2018-11-08 | 2019-02-01 | 上海艾为电子技术股份有限公司 | A kind of surge protection circuit |
| CN109473426A (en) * | 2019-01-17 | 2019-03-15 | 上海艾为电子技术股份有限公司 | Electrostatic discharge circuit and electronic equipment |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110336262A (en) | 2019-10-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR102379554B1 (en) | Protection circuit | |
| CN101702509B (en) | Blocking surge protection device | |
| US7974061B2 (en) | Common gate connected high voltage transient blocking unit | |
| CN110336262B (en) | Surge protection circuit | |
| US8681467B2 (en) | Surge protection apparatus and method using the same | |
| CN110112720B (en) | Surge protection circuit, port chip and surge protection method | |
| US20060250736A1 (en) | Transient blocking apparatus with electrostatic discharge protection | |
| CN107979281B (en) | Input voltage division module and overvoltage protection switch | |
| CN110571776B (en) | Surge protection circuit | |
| CN215185854U (en) | Surge protection circuit | |
| CN111130086B (en) | Power supply system safety potential protection circuit | |
| CN108879633B (en) | ESD protection circuit and method | |
| CN109217278B (en) | Surge protection circuit, circuit system and electronic equipment | |
| US10607949B2 (en) | Electrostatic discharge (ESD) protection for a high side driver circuit | |
| CN114172137A (en) | Circuit and method for electrostatic discharge protection | |
| CN109361203B (en) | Protection circuit | |
| CN114204535B (en) | Blocking type surge protector with accelerated turn-off | |
| CN109301807B (en) | Surge protection circuit, circuit system and electronic equipment | |
| US11929609B2 (en) | Surge protection circuit | |
| US11824350B1 (en) | Clamping circuit for protecting FACTs | |
| KR101689969B1 (en) | A power supply circuit system using a negative threshold five-terminal NMOS FET device with multiple step connection for negative DC/DC converter | |
| KR20160150303A (en) | A power supply circuit system using a negative threshold five-terminal NMOS FET device with multiple step connection for double power amplification | |
| KR101694013B1 (en) | A power supply circuit system using a negative threshold five-terminal NMOS FET device with multiple step connection for boosting voltage | |
| CN210273497U (en) | Differential mode surge protection circuit | |
| CN209250234U (en) | Protect circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |