CN110335823A - Laminated semiconductor packaging body with cantilevered pad - Google Patents
Laminated semiconductor packaging body with cantilevered pad Download PDFInfo
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- CN110335823A CN110335823A CN201910592880.9A CN201910592880A CN110335823A CN 110335823 A CN110335823 A CN 110335823A CN 201910592880 A CN201910592880 A CN 201910592880A CN 110335823 A CN110335823 A CN 110335823A
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- cantilevered
- packaging body
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 122
- 239000004065 semiconductor Substances 0.000 title claims abstract description 56
- 239000000758 substrate Substances 0.000 claims abstract description 67
- 238000003466 welding Methods 0.000 claims abstract description 27
- 238000000034 method Methods 0.000 claims description 14
- 230000008878 coupling Effects 0.000 claims description 5
- 238000010168 coupling process Methods 0.000 claims description 5
- 238000005859 coupling reaction Methods 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 238000005538 encapsulation Methods 0.000 claims 1
- 239000000725 suspension Substances 0.000 claims 1
- 238000010521 absorption reaction Methods 0.000 abstract description 2
- 239000000463 material Substances 0.000 description 39
- 239000004020 conductor Substances 0.000 description 14
- 239000012774 insulation material Substances 0.000 description 14
- 238000005516 engineering process Methods 0.000 description 7
- 230000008021 deposition Effects 0.000 description 5
- 238000003754 machining Methods 0.000 description 5
- 238000012545 processing Methods 0.000 description 5
- 229910000679 solder Inorganic materials 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 239000000919 ceramic Substances 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 239000011162 core material Substances 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 238000003475 lamination Methods 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 229920000642 polymer Polymers 0.000 description 3
- 238000005452 bending Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000007613 environmental effect Effects 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000011900 installation process Methods 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- VLLVVZDKBSYMCG-UHFFFAOYSA-N 1,3,5-trichloro-2-(2-chlorophenyl)benzene Chemical compound ClC1=CC(Cl)=CC(Cl)=C1C1=CC=CC=C1Cl VLLVVZDKBSYMCG-UHFFFAOYSA-N 0.000 description 1
- SMZOUWXMTYCWNB-UHFFFAOYSA-N 2-(2-methoxy-5-methylphenyl)ethanamine Chemical compound COC1=CC=C(C)C=C1CCN SMZOUWXMTYCWNB-UHFFFAOYSA-N 0.000 description 1
- NIXOWILDQLNWCW-UHFFFAOYSA-N 2-Propenoic acid Natural products OC(=O)C=C NIXOWILDQLNWCW-UHFFFAOYSA-N 0.000 description 1
- 229920000297 Rayon Polymers 0.000 description 1
- 230000009471 action Effects 0.000 description 1
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- 230000001070 adhesive effect Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 150000002118 epoxides Chemical class 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000001746 injection moulding Methods 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
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- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 229920002635 polyurethane Polymers 0.000 description 1
- 239000004814 polyurethane Substances 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000009824 pressure lamination Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 238000007711 solidification Methods 0.000 description 1
- 230000008023 solidification Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15182—Fan-in arrangement of the internal vias
- H01L2924/15183—Fan-in arrangement of the internal vias in a single layer of the multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3512—Cracking
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
One or more embodiments be related to include multiple stacked package bodies the semiconductor package body with one or more cantilevered pads.In one embodiment, recess is located in the substrate of packaging body, faces cantilevered pad.Cantilevered pad includes the conductive welding disk for being formed with conducting sphere thereon.Cantilevered pad is configured for stress of the absorption on packaging body.
Description
Divisional application explanation
The application be on December 18th, 2015 applying date, application No. is 201510958774.X, entitled " with cantilever
The divisional application of the Chinese patent application of the laminated semiconductor packaging body of formula pad ".
Technical field
The embodiment of present disclosure be related to include packaging body lamination (PoP) semiconductor package body and preparation method thereof.
Background technique
The reliability of semiconductor package body is very important.Although various problems result in the reliable of semiconductor package body
Property problem, known to one of integrity problem the reason is that packaging body and to the substrate or plate for installing packaging body thereon by various
The material of type is formed, and every kind of material has different thermal expansion coefficients (CTE).Generate heat during use, and by
In different CTE, stress may be introduced into packaging body and/or plate.Stress can for example lead to crack in pad, such as will
Semiconductor package body those of is coupled on printed circuit board (PCB) pad, from there through upsetting between packaging body and PCB
Electric coupling and the board level reliability for influencing packaging body.
When multiple packaging bodies stack on top of each other (such as in the stacked package body of also referred to as PoP), by difference
CTE caused by problem may be further complicated.In general, in PoP, stacked package body by be located at adjacent package body it
Between multiple conducting spheres be coupled together.Due to the stress being introduced in as caused by different CTE in packaging body, Mei Gefeng
Filling body all may warpage.Meanwhile two adjacent packaging bodies may warpage away from each other so that top packaging body to
It is upper bending and lower part packaging body be bent downwardly, thus these conducting spheres are placed in draftability stress, specifically, by these
Conducting sphere is placed at the periphery of PoP.In addition, interconnecting these as greater amount of packaging body stacks on top of each other
Generated stress may will increase on those of packaging body solder ball.
Summary of the invention
One or more embodiments are related to the semiconductor package body with one or more cantilevered pads.Implement at one
In example, recess is located in the substrate of packaging body, faces cantilevered pad.Cantilevered pad includes being formed with leading for conducting sphere thereon
Electrical bonding pads.Cantilevered pad is configured for stress of the absorption on the packaging body.For example, cantilevered pad can be by
It is disposed for bending and enters recess and/or bent outward from recess.In this regard, cantilevered pad can be in response to positive interaction
Stress in a variety of materials of semiconductor package body and responded easily.For example, during operation, in response to a kind of or
Multiple material by the expansion caused by a variety of materials that are expanded with different CTE and with different rate, cantilevered weldering
Disk may be configured to inwardly flexure, bend and/or bend outward far from recess towards recess.To reduce in packaging body
Or be coupled to the packaging body PCB electric structure in formed crack a possibility that.In one embodiment, cantilevered pad can be with
It prevents that crack occurs in multiple conducting spheres that packaging body is electrically coupled to PCB or reduces its possibility.
In some embodiments, multiple cantilevered pads are formed in two opposite sides of substrate.Another embodiment relates to
It and include the PoP of one or more packaging bodies with multiple cantilevered pads.In one embodiment, PoP includes vertically
The first packaging body being stacked on the second packaging body.First packaging body and the second packaging body respectively include the weldering of at least one cantilevered
Disk.Second packaging body includes substrate and including multiple cantilevered pads in the opposed surface of the substrate.
Detailed description of the invention
In the drawings, identical reference number identifies similar element.It is not necessarily drawn to scale the element in attached drawing
Size and relative position.
Figure 1A is the cross-sectional view according to the semiconductor package body of one embodiment of present disclosure.
Figure 1B is the close-up cross-sectional view of the packaging body of Fig. 1.
Fig. 1 C is the feature bottom view of the close-up illustration of Figure 1B.
Fig. 2 is coupled to the close-up cross-sectional view of the packaging body of Fig. 1 of another device.
Fig. 3 illustrates the bottom surface of the packaging body including some cantilevered pads according to one embodiment.
Fig. 4 A-4H illustrates cross-sectional view, shows according to one embodiment in each fabrication stage with the feature of Figure 1B
View assembles the packaging body of Fig. 1.
Fig. 5 A illustrates the cross-sectional view of the PoP of one embodiment according to present disclosure.
Fig. 5 B is the close-up cross-sectional view of the PoP of Fig. 5 A.
Specific embodiment
Although, can be it should be understood that there is described herein the specific embodiment of present disclosure for illustrative purpose
Various modifications are made in the case where the spirit and scope for not departing from present disclosure.
In the following description, certain details be set forth in order to provide the comprehensive of the different aspect to disclosed theme
Understand.However, disclosed theme may be practiced without these specific details.In some instances, not yet right
The well-known semiconductor machining structures and methods of embodiment including theme disclosed herein are described in detail to keep away
Exempt from the otherwise description of fuzzy present disclosure.
Figure 1A shows the cross-sectional view of the packaging body 10 according to one embodiment of present disclosure.Figure 1B shows Figure 1A's
The close-up illustration of a part.Packaging body 10 includes the semiconductor bare chip 12 on the upper surface of substrate 14 13.Semiconductor bare chip 12
Electric structure including electronic device (such as integrated circuit).
Substrate 14 has the lower surface 15 opposite with upper surface 13, and including one or more conductive layer and insulating layers.
In the embodiment shown, substrate 14 includes the first insulation material layer 17 and the second insulation material layer 19；However, substrate 14 can
To include any amount of insulating layer.These insulating layers may include any insulating materials, including ceramics, glass, polymer or
Any other suitable insulating materials.The one or more conductive layer can be any conductive material, such as metal material.At one
In embodiment, these conductive layers are copper.
Semiconductor bare chip 12 is coupled to the upper surface 13 of substrate 14 by jointing material 18.Jointing material 18 can be half
Semiconductor die 12 is bonded to any jointing material 18 of the upper surface 13 of substrate 14, such as viscose glue, glue, epoxides, double-sided adhesive
Band or any other suitable material.
The upper surface 13 of substrate 14 includes multiple conductive fingers of one or more adjacent edges positioned at semiconductor bare chip 12
Shape object 20.Although illustrating only two conductive fingers 20, it should be understood that any amount of conductive fingers 20 can be provided,
Including only one.In some embodiments, multiple conductive fingers 20 are located on every side of semiconductor bare chip 12.It is general and
Speech, these conductive fingers 20 are electrically isolated from each other, however, two or more can be coupled by one or more conductive traces
Together.
Semiconductor bare chip 12 is electrically coupled to these conductive fingers 20.Specifically, the electronic device of semiconductor bare chip 12 is logical
It crosses a plurality of conductive connection 22 and is coupled to these conductive fingers 20.More specifically, the first end 27 of conductive connection 22 is coupled to half
The bonding welding pad of semiconductor die 12, the bonding welding pad can be coupled to each electronic component of electronic device, and conductive connection
Second end 24 be coupled to conductive fingers.In another embodiment, as known in the art, semiconductor bare chip 12
Electronic device these conductive fingers 20 are coupled to by flip-chip arrangement.In this regard, these conductive fingers 20 will
Positioned at 12 lower section of semiconductor bare chip and those of semiconductor bare chip 12 bonding welding pad is coupled to by multiple conducting spheres.
The lower surface 15 of substrate 14 includes multiple cantilevered pads 26.As being best shown in fig. ib, these cantilevers
Formula pad 26 includes the conductive welding disk 28 that is supported by substrate supports part 30 on the conductive welding disk 28 of cantilevered pad 26
It is conducting sphere 31 (such as solder ball), which is configured for packaging body 10 being coupled to another substrate or plate, such as
PCB50 (Fig. 2).
These cantilevered pads 26 are by being located at multiple recess 32 of these 26 tops of cantilevered pad and by serving as a contrast
Multiple pass through openings 33 along three sides of these cantilevered pads 26 in bottom 14 and suspend.Specifically, these recess 32
In first layer 17, and these pass through openings 33 are located in the second layer 19 being connected to these recess 32.Such as in fig. 1 c most
It shows goodly, multiple pass through openings 33 are from one end of these cantilevered pads 26 and along the side surface of these cantilevered pads
Extend, is formed in plan view.In plan view, pass through openings 33, which can be, is formed together cantilevered weldering with recess 32
Any shape of disk.For example, pass through openings 33 can also be V-arrangement or U-shaped.
The thickness of cantilevered pad 26 is when packaging body 10 to be attached on another substrate or plate for cantilevered pad
26, which provide suitable structural support simultaneously, also allows any thickness of cantilevered pad 26 centainly bent.Cantilevered pad 26 can
To allow to bend in one direction and (enter recess 32 or flexure far from the recess as bent) or bend (such as in two directions
Flexure enters recess 32 and bends far from the recess).
It is bent in view of cantilevered pad 26 and enters recess 32, recess 32 can have the depth for being enough to provide gap appropriate
Degree, so that the upper surface of cantilevered pad 26 does not connect with the contacted inner surfaces for defining recess 32 of substrate 14.
These conductive fingers 20, which pass through one or more conductive trace 36 and extend through the multiple of substrate 14, to be penetrated through
Hole 38 is electrically coupled to the conductive welding disk 28 of these cantilevered pads 26.It is, these conductive fingers 20 are coupled to positioned at
The trace 36 of one layer of 17 top.The first layer 17 and the second layer 19 of trace 36 on first layer 17 by extend through substrate 14
Multiple perforation via holes 38 are coupled to the trace 36 on the second layer 19.In the embodiment shown, interior trace 44 is by first layer
Perforation via hole 38 in 17 is coupled to the perforation via hole 38 in the second layer 19.
Dielectric layer 46 is located on these traces 36 and in the first surface and second surface of substrate 14.Dielectric
Layer 46, which can be, any can provide protection against environmental damage source (e.g., burn into physical damage, damp damages or to electric special
Sign other sources of damage) influence material.In one embodiment, dielectric layer 46 is solder mask material.The welding resistance
Mask can be the fluent material such as hardened during solidification process.
Encapsulating material 48 is located at substrate, surrounds the bare die, these conductive fingers 20 and these conductive connections 22.Packet
Closure material 48 can be it is any be configured for provide protection against environmental damage source (e.g., burn into physical damage,
Damp damages or other sources of damage to electronic device) influence material.Encapsulating material 48 can be mold compound, should
Mold compound includes one or more of the following items: polymer, polyurethane, acrylic acid, epoxy resin, silicone or any
Other suitable materials.
Fig. 2 shows the portions that plate (such as printed circuit board (PCB) 50) is coupled to by these conducting spheres 31 of packaging body 10
Point.As shown in FIG. 2, the flexure of cantilevered pad 26 enters recess 32.Cantilevered pad 26 can be absorbed in packaging body
A variety of materials or component or be coupled to generated stress in the component of packaging body.Specifically, cantilevered pad 26 can be rung
Recess 32 should be moved into multiple power those of (such as caused by the thermal expansion of one or more components power) and/or moved away from
Thus the recess prevents from forming crack in electronic component (such as conducting sphere 31) or reduces its possibility.Due to cantilevered pad
26 flexibility improves the conductive junction point reliability or welding point reliability of packaging body 10.
During installation process, cantilevered pad 26 can be bent into recess 32, in the installation process, packaging body 10
It is also attached on PCB 50.For example, due to multiple non-planar conducting spheres 31 (for example, the height of support of these conducting spheres is poor),
Certain cantilevered pads 26 can be bent inwardly or outwardly from recess.In some embodiments, pressure can be applied during installation
Power, thus will on these cantilevered pads 26 applied force to move inward.Non-planar conducting sphere may be by distribution different proportion
Formation these balls conductive material or warpage by all parts of packaging body caused by.
Packaging body 10 may include any amount of cantilevered pad 26.In one embodiment, all of packaging body lead
Electrical bonding pads are all cantilevered pads 26.In other embodiments, only having some in the conductive welding disk of packaging body is cantilevered pad
26, and other conductive welding disks are not cantilevered.In one embodiment, cantilevered pad 26 is located on packaging body and is corresponding to
In the position for applying the maximum amount of expected stress to pad and on the conducting sphere on pad.
Fig. 3 illustrates the layout of the bottom surface of packaging body 10a, which includes being fixed to multiple as described above hang
Multiple conducting spheres 31 on arm-type pad 26 and be not cantilevered traditional pad 27.It is, these cantilevered pads 26
It is located at the periphery of packaging body 10a with conducting sphere 31, and these conductive welding disks 28 and conducting sphere 31 at the center of packaging body 10a
It is traditional non-cantilevered pad.In some embodiments, during thermal expansion, the conduction those of at the periphery of packaging body
Pad and convex block may be by the stress bigger than those center bonding pads.In this regard, in those of outer circumference of packaging body
Cantilevered pad 26 is able to respond to be bent in generated stress wherein, and those center bonding pads are not answered significantly
Power.
Fig. 4 A-4H illustrates cross-sectional view, illustrates according to one embodiment in each fabrication stage with the feature of Figure 1B
View assembles the packaging body 10 of Figure 1A.Fig. 4 A shows the first insulating core material layer 17, which can be ceramics, glass
Glass, polymer or any suitable core material.Although it is not shown, in some embodiments, during at least part of processing,
First layer 17 can be coupled to support construction.First insulation material layer 17 has first surface 62 and second surface 64.
As shown by figure 4b, the multiple portions of the first insulation material layer 17 are removed.Specifically, in first layer 17
Multiple recess 32 are formed in second surface 64, and form multiple through-holes 66 that second surface 64 is extended to from first surface 62.
These recess 32 correspond to the position for these cantilevered pads 26, and these through-holes 66 correspond to for Figure 1A and Figure 1B
Those of conductive perforation via hole 38 position.
Recess 32 and through-hole 66 are formed using the semiconductor machining of standard, the semiconductor machining of the standard includes using light
Quick material (such as photoresist and etching (for example, wet etching and/or dry etching)) carrys out patterned second surface.Although only showing
One recess and through-hole, by those skilled in the art it is evident that in the second surface 64 of first layer 17 shape
At multiple recess 32 and through-hole 66.
As shown by figure 4 c, via hole 38 is penetrated through to fill through-hole 66 to form conduction with conductive material.Similarly,
Conductive material is deposited on the first surface 62 and second surface 64 of first layer 17, conduction perforation via hole 38 above and under
Side forms trace 36 and conductive fingers 20.Deposition is executed using the semiconductor processing technology of standard, the semiconductor of the standard
Processing technology may include: patterning conductive material or blanket deposition conductive material, and then remove the multiple of conductive material
Part is to form a plurality of trace and multiple conductive fingers.As described above, conductive material can be any conductive material, and
It is copper in one embodiment.In another embodiment, the conductive material in through-hole can be different from the conduction material to form trace
Material.
As shown by fig. 4d, the second insulation material layer 19 is fixed on the second surface 64 of first layer 17.The
(including lamination, may include pressure lamination and/or heat lamination) first layer can be fixed to by any method for two layer 19
On 17.The thickness of the second layer 19 depends on the material property for the second layer 19 and changes, and might also depend on and to form mark
The mechanical property of the conductive material of line 36 and conductive welding disk 28.In the embodiment that the second layer 19 is ceramics, the second layer 19 can be with
It is film.
As shown by fig. 4d, formed in the second layer 19 under the conductive perforation via hole 38 in first layer 17 logical
Hole 68.Through-hole 68 is formed using the processing technology (including pattern and etch as mentioned above) of standard.It can incite somebody to action
The second layer 19 forms through-hole 68 before or after being fixed on first layer 17.
As shown in Fig. 4 E, conductive material is deposited in the through-hole 68 of the second layer 19 and was penetrated through with forming conduction
Hole 38.The perforation via hole 38 of the second layer 19 is electrically coupled to the perforation via hole 38 of first layer 17 by interior trace 44.Note that internal
Trace 44 laterally extends perforation via hole 38.It in view of through-hole 66 and 68 is etched in different procedure of processings, interior trace
44 can solve any misalignment occurred between the perforation via hole 38 of first layer 17 and the perforation via hole 38 of the second layer 19
Problem.
As shown in Fig. 4 E, conductive material is deposited on the bottom surface of the second layer 19 to form trace 36 and lead
Electrical bonding pads 28.The semiconductor technology of standard mentioned above can be used to deposit and patterning conductive material.
As shown in Fig. 4 F, dielectric layer 46 is deposited on the multiple portions and of first layer 17 and the second layer 19
On various structures (e.g., trace 36) on one layer 17 and the second layer 19.Dielectric layer 46 is the semiconductor machining by standard
Technology including the blanket deposition with patterning and etching or patterns light-sensitive material then patterned deposition come what is deposited.
As described above, dielectric layer 46 can be formed by the fluent material of deposition hardening.The fluent material can be hard with the time
Change or can be hardened in heating or curing schedule.
As shown in Fig. 4 F, the conductive welding disk 28 on the second layer 19 keeps exposure, and leading on first layer 17
Electric finger-shaped material 20 keeps exposure.In addition, the part 70 of the second layer 19 keeps not covered by dielectric layer 46.Part 70 is at least partly
Ground is located at 32 lower section of recess.
The part 70 stayed open has shape corresponding with the shape of pass through openings 33 in Fig. 1 C.However, as above
Pointed by text, the shape of part 70 can be a part for leading to the second layer 19 when being etched and recess 32 is formed
Cantilevered pad 26 any shape.To, which can be any both sides shape or triangle, as C-shaped, U-shaped, V-arrangement or
Any other suitable shape.
As shown in Fig. 4 G, such as in dry etching or wet etch step, the removal second layer 19 is being recessed
The part 70 of lower section.In one embodiment, dielectric layer serves as etching mask.When removing the part 70 of the second layer 19, shape
At cantilevered pad 26.
As shown in Fig. 4 H, semiconductor bare chip 12 is coupled to the upper surface 13 of substrate 14 by jointing material 18.
It is, jointing material can be applied in one or two of upper surface 13 and rear surface of semiconductor bare chip 12.Such as
It is well known in the art, conductive connection 22 is coupled between semiconductor bare chip 12 and conductive fingers 20.In substrate
Encapsulating material 48 is formed on 14 upper surface 13, encapsulates the various parts of packaging body.The semiconductor machining of standard can be used
Technology forms encapsulating material, these technologies include using mold, in the mold and surrounds all parts injection moldings
Close object.Then, mold compound hardens in cure step, which includes curing schedule or heating stepses.It can be
Conducting sphere 31 is formed on cantilevered pad 26, such as passes through solder distribution technique.However, in other embodiments, in packaging body 10
Formation conducting sphere 31 on another device thereon will be coupled to.
It should be understood that these method and steps can execute in any order, so as to with it is shown or described
Order in a different order execute.For example, can be before first layer 17 and the second layer 19 be couple to together in the second layer 19
Middle formation pass through openings 33.
Fig. 5 A shows the cross-sectional view of stacked package body or PoP 72 according to one embodiment of present disclosure.PoP 72
Including the first packaging body (packaging body 10 of such as Fig. 1) being stacked on the second packaging body 74.Pass through those of first packaging body 10
Conducting sphere 31 is by the mechanical coupling of the first packaging body 10 and is electrically coupled to the second packaging body 74.Though it is shown that two packaging bodies, it should
PoP can comprise more than two packaging bodies.
Second packaging body 74 is substantially similar to the packaging body 10 of Fig. 1, and is included in and is structurally and functionally similar to
Many elements of those of one packaging body 10 element.So that for simplicity, the structure and function of these similar elements will
It is not repeated.Will be discussed in detail the second packaging body 74 below is different from those of the first packaging body 10 element.
Fig. 5 B shows the feature of the second packaging body 74 of PoP 72.Second packaging body 74 includes semiconductor bare chip 12, should
Semiconductor bare chip is coupled to the upper of substrate 14 by multiple conducting sphere 31a in flip-chip arrangement well known in the art
Multiple conductive welding disks on surface 13.The encapsulating material 48 on upper surface 13 by being located at substrate 14 is come encapsulating semiconductor bare die
12 and these conducting spheres 31a.
The substrate includes two or three insulation material layers, and first layer 17 is with two second layers 19 in the opposite of first layer 17
On side.First layer 17 includes the multiple recess 32 formed on the opposite side.In the embodiment shown, these are recessed 32 each other
It is formed on the contrary；It is to be understood, however, that these recess 32 can be offset from one another.These second insulation material layers 19 include
A part of recesses those of in multiple pass through openings 33, these pass through openings and the first insulation material layer 17 in recess 32
It closes.These second layers 19 form multiple cantilevered pads 26 on these recess 32.
Substrate 14 includes providing be electrically connected multiple between lower surface 15 of the upper surface of substrate 14 13 with substrate 14 to lead
Electricity perforation via hole 38 and a plurality of interior trace 44.These conduction perforation via holes 38 are with the first end close to upper surface 13 and connect
The second end of nearly lower surface 15.The first end and second end of these conduction perforation via holes 38 is coupled to one or more by trace 36
A cantilevered pad 26.In this regard, the second packaging body 72 includes multiple cantilevers in the upper and lower surfaces of substrate 14
Formula pad 26.These cantilevered pads 26 can be opposite each other in upper and lower surfaces as shown in Figure 5 or can be each other
Offset.
As being best shown in fig. 5, these cantilevered pads 26 on the upper surface of the second packaging body 74 pass through this
A little conducting spheres 31 are coupled to those of the first packaging body 10 cantilevered pad 26.In this regard, these conducting spheres 31 are in the first envelope
It provides and is electrically connected between dress body 10 and the second packaging body 74.It should be appreciated that in some embodiments, there was only one in these pads
(including one) can be cantilevered pad a bit.
Multiple conducting sphere 31a are located on the second packaging body 74.These conducting spheres 31a provides being electrically connected outside PoP 72
It is logical.In this regard, these conducting spheres 31a provides external be connected to 74 the two of the second packaging body for the first packaging body 10.Tool
Body, the first packaging body 10 have through the trace 44,36 of conducting sphere 31 and conductive via 38 and the second packaging body 74 to leading
The power path of electric ball 31a.The semiconductor that the semiconductor bare chip 12 of second packaging body 74 can be electrically coupled to the second packaging body 10 is naked
Piece 12 such as passes through perforation via hole 38, trace 44,36 and cantilevered pad 26.Although having been not shown, the first packaging body 10 and
Two packaging bodies 72 can be by other conductive interconnections (the multiple conductive vias such as extended from the opposed surface of substrate) by substrate coupling
It is connected together.
PoP 72 is formed using the method similar with those methods above by reference to described in Fig. 4 A-4H.However, should
Understand, the two sides of the first insulation material layer 17 will be all processed to form those cantilevered pads 26 on two sides.For example,
Multiple recess 32 are formed on the two sides of the first insulation material layer 17, and form mark on the two sides of the first insulation material layer 17
Line 44 and the second insulation material layer 19.
It is possible, firstly, to as formed on those of the first packaging body 10 cantilevered pad 26 referring to described in Fig. 4 H
These conducting spheres 31.Alternatively, conducting sphere 31,31a are formed on the cantilevered pad 26 of the second packaging body 74.
These cantilevered pads 26 allow the flexure of the conducting sphere 31,31a in PoP 72.It is, these cantilevereds are welded
Disk 26 can bend the stress with receiving effect on it up and/or down.In this regard, when cantilevered pad is bent,
First packaging body 10 and the second packaging body 74 can keep substantially flat, thus reduce answering on the element for acting on PoP 72
Power.
Various types of materials can be used in the various embodiments that this is discussed.It is provided below and can be used for Fig. 1 extremely
The material of the embodiment of Fig. 5 B and an example of thickness.It should be understood that following set these materials and thickness are only
It is only an example, and many other materials and thickness can be used.
First insulation material layer 17 of substrate, which can be, to be mentioned by (Hitachi) company, Hitachi with component names E679-FGB
The core of confession, and there is the thickness between about 0.095mm and 0.225mm, however, many other acceptable materials and conjunction
Suitable thickness can be used.The thickness of first layer can depend on whether cantilevered pad is formed in the opposite each other of substrate
Opposite side on or cantilevered pad whether be formed on the side of substrate or be offset from one another on the opposite side.
The second insulation material layer of those of substrate 19 can be by Hitachi, Ltd with component names GEA-E679FG (GZPE)
Provided prepreg, and there is the thickness between about 0.032mm and 0.048mm, however, many other acceptable
Material and suitable thickness can be used.The opening in recess and the second layer in first layer can about 0.04mm with
Between 0.60mm.It should be understood by those skilled in the art that depend on packaging body used in material (including first absolutely
Edge material layer), the thickness of these recess and opening can be different.
These traces 36, conductive welding disk 28 and conductive fingers 20 can be copper and can have in about 0.012mm
Thickness between 0.023mm.These dielectric layers 46 can be by sun ironworker (Taiyo) company with component names AUS
Solder masks provided by 308, and there is the thickness between about 0.010mm and 0.030mm.
Each embodiment described above can be combined to provide further embodiment.It quotes in the present specification
And/or enumerated in application data form all United States Patent (USP)s, U.S. Patent Application Publication, U.S. Patent application, foreign country specially
Benefit, foreign patent application and non-patent disclosure are entirely incorporated by reference in this.If it is necessary, can be to each side of embodiment
Face is modified, and provides further embodiment with concept using each patent, application and publication.
In light of the above-detailed description, these and other changes can be made to embodiment.In short, in following following claims
In book, used term is not construed as claims being confined to disclosed in the specification and claims
Specific embodiment, but should be interpreted as including all possible embodiment, together with these claims have the right obtain
The entire scope of equivalent.Correspondingly, claims are not exposed to the limitation of present disclosure.
Claims (19)
1. a kind of stacked package body component, comprising:
Top packaging body, the top packaging body include:
First substrate, first substrate have first surface and second surface；
Opening at the second surface of first substrate, the opening is in the first surface and the second surface
Between form recess；
First cantilevered pad, the first cantilevered pad are suspended by the recess, and the first cantilevered pad is formed
A part of the second surface of the substrate, the first conductive welding disk are located on the first cantilevered pad；And
First semiconductor bare chip, first semiconductor bare chip are coupled to the first surface of first substrate, and described
Semiconductor bare die is electrically coupled to first conductive welding disk；
It is coupled to multiple conducting spheres of the top packaging body；And
The lower part packaging body being stacked below the top packaging body, the lower part packaging body are coupled by the multiple conducting sphere
To the top packaging body, the lower part packaging body includes:
Second substrate, second substrate have third surface and the 4th surface；
The second opening at the third surface, second opening in second substrate, on the third surface and
Recess is formed between 4th surface；
Second cantilevered pad, the second cantilevered pad are suspended by the recess, and form second substrate
The a part on the third surface；
Second conductive welding disk, second conductive welding disk are located on the second cantilevered pad；And
Second semiconductor bare chip, second semiconductor bare chip are coupled to the third surface and described of second substrate
One of four surfaces, one of second semiconductor bare chip and first semiconductor bare chip are electrically coupled to the described second conductive weldering
Disk.
2. stacked package body component as described in claim 1, wherein the multiple conducting sphere is coupled to described in first side position
Second conductive welding disk and first conductive welding disk is coupled at second side.
3. stacked package body component as described in claim 1, wherein the first cantilevered pad and the first conductive weldering
Disk is one of multiple first cantilevered pads and multiple first conductive welding disks respectively.
4. stacked package body component as claimed in claim 3, wherein the multiple first cantilevered pad and the multiple
One conductive welding disk is located at the periphery of the second surface.
5. stacked package body component as claimed in claim 3, wherein the second cantilevered pad and the second conductive weldering
Disk is one of multiple second cantilevered pads and multiple second conductive welding disks respectively, wherein the multiple second conductive welding disk is logical
It crosses the multiple conducting sphere and is electrically coupled to the multiple first conductive welding disk.
6. stacked package body component as described in claim 1, wherein the first cantilevered pad and second cantilevered
Pad is respectively partially by C-shaped pass through openings, U-shaped pass through openings and the V-arrangement in first substrate and second substrate
The formation of one of pass through openings.
7. stacked package body component as described in claim 1, further comprises:
Opening at the 4th surface of second substrate, the opening form recess in second substrate；With
And third cantilevered pad, the third cantilevered pad extend on the recess in second substrate.
8. a kind of packaging body laminated module, comprising:
Top packaging body, the top packaging body include the first semiconductor bare chip for being coupled to the first surface of the first substrate, institute
Stating the first substrate includes the multiple first cantilevered pads being electrically connected with first semiconductor bare chip, the multiple first cantilever
Formula pad is covered each by the recess in first substrate；
It is coupled to multiple conductive interconnection parts of the top packaging body；And
Lower part packaging body below the top packaging body, the lower part packaging body include be coupled to the second substrate second
Second semiconductor bare chip on surface, the lower part packaging body are coupled to the top by the multiple conductive interconnection part and encapsulate
Body, second substrate include multiple second cantilevered pads, and the multiple second cantilevered pad is covered each by described second
Recess in substrate, the second cantilevered pad of at least one of the multiple second cantilevered pad and first semiconductor
Bare die is electrically connected.
9. packaging body laminated module as claimed in claim 8, wherein the multiple second cantilevered pad is located at described second
On the second surface of substrate.
10. packaging body laminated module as claimed in claim 8, wherein the multiple second cantilevered pad is located at described the
On two substrates, opposite with second surface third surfaces.
11. packaging body laminated module as claimed in claim 9 further comprises the second surface in second substrate
On multiple third cantilevered pads, wherein it is outstanding that the multiple conductive interconnection part in first side position is coupled to the multiple first
Arm-type pad and the multiple third cantilevered pad is coupled at second side.
12. packaging body laminated module as claimed in claim 11, wherein the multiple third cantilevered pad and the multiple
Second cantilevered pad overlaps each other on the opposite flank of the lower part packaging body.
13. packaging body laminated module as claimed in claim 8, wherein first semiconductor bare chip is led by the multiple
One or more conductive interconnection parts in electrical interconnection are electrically coupled to second semiconductor bare chip.
14. packaging body laminated module as claimed in claim 8, wherein the multiple conductive interconnection part is multiple conducting spheres.
15. a kind of packaging method, comprising:
Multiple conductive interconnection parts are formed on the packaging body of top, the top packaging body includes the first table for being coupled to the first substrate
First semiconductor bare chip in face, first substrate include respectively by the more of multiple recesses suspension in first substrate
A first cantilevered pad, the multiple first cantilevered pad is electrically connected with first semiconductor bare chip, wherein forming institute
Stating multiple conductive interconnection parts includes: that the multiple conductive interconnection part is formed on the multiple first cantilevered pad；With
Lower part packaging body is coupled to the multiple conductive interconnection part, and forms packaging body laminated module, the lower part encapsulation
Body includes the second semiconductor bare chip being coupled on the second surface of the second substrate, and the lower substrate includes respectively by institute
State multiple second cantilevered pads that multiple recesses in the second substrate suspend, in the multiple second cantilevered pad at least
One the second cantilevered pad is electrically connected with first semiconductor bare chip, wherein the coupling includes: the multiple second outstanding
Arm-type pad is coupled to the multiple conductive interconnection part.
16. packaging method as claimed in claim 15, wherein after coupling the lower part packaging body, the multiple first
Cantilevered pad is towards the multiple second cantilevered pad.
17. packaging method as claimed in claim 15, wherein the multiple first cantilevered pad and the multiple second hangs
Arm-type pad has at least one shape in C-shaped, U-shaped and V-arrangement shape.
18. packaging method as claimed in claim 15, wherein couple the lower part packaging body to the multiple conductive interconnection part
At least one of the multiple first cantilevered pad and the multiple second cantilevered pad is caused to turn to.
19. packaging method as claimed in claim 15, wherein forming the multiple conductive interconnection part includes: the multiple
The multiple conductive interconnection part is distributed on first cantilevered pad.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US14/721,831 | 2015-05-26 | ||
| US14/721,831 US9768126B2 (en) | 2014-12-24 | 2015-05-26 | Stacked semiconductor packages with cantilever pads |
| CN201510958774.XA CN106206516B (en) | 2015-05-26 | 2015-12-18 | Laminated semiconductor packaging body with cantilevered pad |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510958774.XA Division CN106206516B (en) | 2015-05-26 | 2015-12-18 | Laminated semiconductor packaging body with cantilevered pad |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110335823A true CN110335823A (en) | 2019-10-15 |
Family
ID=56959844
Family Applications (3)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201521066505.4U Withdrawn - After Issue CN205609508U (en) | 2015-05-26 | 2015-12-18 | Stromatolite packaging body subassembly and packaging body stacked wafer module |
| CN201510958774.XA Active CN106206516B (en) | 2015-05-26 | 2015-12-18 | Laminated semiconductor packaging body with cantilevered pad |
| CN201910592880.9A Pending CN110335823A (en) | 2015-05-26 | 2015-12-18 | Laminated semiconductor packaging body with cantilevered pad |
Family Applications Before (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201521066505.4U Withdrawn - After Issue CN205609508U (en) | 2015-05-26 | 2015-12-18 | Stromatolite packaging body subassembly and packaging body stacked wafer module |
| CN201510958774.XA Active CN106206516B (en) | 2015-05-26 | 2015-12-18 | Laminated semiconductor packaging body with cantilevered pad |
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| CN (3) | CN205609508U (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN205609508U (en) * | 2015-05-26 | 2016-09-28 | 意法半导体公司 | Stromatolite packaging body subassembly and packaging body stacked wafer module |
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| US6281588B1 (en) * | 1995-09-12 | 2001-08-28 | Tessera, Inc. | Lead configurations |
| US20020190396A1 (en) * | 2000-08-16 | 2002-12-19 | Brand Joseph M. | Method and apparatus for removing encapsulating material from a packaged microelectronic device |
| US20100244240A1 (en) * | 2009-03-24 | 2010-09-30 | Christopher James Kapusta | Stackable electronic package and method of making same |
| US7982316B1 (en) * | 2008-02-04 | 2011-07-19 | Amkor Technology, Inc. | Semiconductor package having a land to absorb thermal and mechanical stress and fabricating method thereof |
| US20130043583A1 (en) * | 2011-08-17 | 2013-02-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Dummy Flip Chip Bumps for Reducing Stress |
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|---|---|---|---|---|
| JP3022312B2 (en) * | 1996-04-15 | 2000-03-21 | 日本電気株式会社 | Method of manufacturing probe card |
| US6064576A (en) * | 1997-01-02 | 2000-05-16 | Texas Instruments Incorporated | Interposer having a cantilevered ball connection and being electrically connected to a printed circuit board |
| JP3099066B1 (en) * | 1999-05-07 | 2000-10-16 | 東京工業大学長 | Manufacturing method of thin film structure |
| US6992399B2 (en) * | 2002-05-24 | 2006-01-31 | Northrop Grumman Corporation | Die connected with integrated circuit component for electrical signal passing therebetween |
| KR20040089244A (en) * | 2003-04-11 | 2004-10-21 | 주식회사 유림하이테크산업 | Needle assembly of probe card |
| KR100854031B1 (en) * | 2006-07-28 | 2008-08-26 | 삼성전자주식회사 | Stacked BGA Semiconductor Packages |
| CN205609508U (en) * | 2015-05-26 | 2016-09-28 | 意法半导体公司 | Stromatolite packaging body subassembly and packaging body stacked wafer module |
-
2015
- 2015-12-18 CN CN201521066505.4U patent/CN205609508U/en not_active Withdrawn - After Issue
- 2015-12-18 CN CN201510958774.XA patent/CN106206516B/en active Active
- 2015-12-18 CN CN201910592880.9A patent/CN110335823A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6281588B1 (en) * | 1995-09-12 | 2001-08-28 | Tessera, Inc. | Lead configurations |
| US20020190396A1 (en) * | 2000-08-16 | 2002-12-19 | Brand Joseph M. | Method and apparatus for removing encapsulating material from a packaged microelectronic device |
| US7982316B1 (en) * | 2008-02-04 | 2011-07-19 | Amkor Technology, Inc. | Semiconductor package having a land to absorb thermal and mechanical stress and fabricating method thereof |
| US20100244240A1 (en) * | 2009-03-24 | 2010-09-30 | Christopher James Kapusta | Stackable electronic package and method of making same |
| US20130043583A1 (en) * | 2011-08-17 | 2013-02-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Dummy Flip Chip Bumps for Reducing Stress |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106206516B (en) | 2019-08-06 |
| CN106206516A (en) | 2016-12-07 |
| CN205609508U (en) | 2016-09-28 |
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