CN110335817B

CN110335817B - Manufacturing method of Schottky

Info

Publication number: CN110335817B
Application number: CN201910601302.7A
Authority: CN
Inventors: 王万礼; 宋楠; 陈海洋; 乐春林; 刘闯; 刘文彬; 刘晓芳; 徐长坡
Original assignee: Tianjin Huanxin Technology & Development Co ltd
Current assignee: Tianjin Huanxin Technology & Development Co ltd
Priority date: 2019-07-03
Filing date: 2019-07-03
Publication date: 2022-07-08
Anticipated expiration: 2039-07-03
Also published as: CN110335817A

Abstract

The invention provides a manufacturing method of a Schottky, which comprises the following steps: s1: depositing a dielectric film on a substrate material; s2: photoetching a field limiting ring and carrying out ion implantation; s3: etching a field limiting ring region; s4: stripping the dielectric film; s5: depositing a metal layer; s6: and carrying out metal photoetching and etching. The method has the advantages that the field limiting ring area is etched, compared with the existing preparation process, one-time photoetching is reduced in the process flow, the production rate is improved, the production cost is reduced, and the occupied time for manufacturing the bottleneck equipment photoetching machine is shortened.

Description

Manufacturing method of Schottky

Technical Field

The invention belongs to the technical field of semiconductor devices, and particularly relates to a manufacturing method of a Schottky.

Background

At present, most of terminal structures of common Schottky devices are structures (single or multiple field limiting rings) with field plates and field limiting rings, the terminal structures do not contribute to forward conduction of the devices, meanwhile, the processing technological process of the Schottky devices with the structures is generally a three-layer photoetching structure, photoetching of the field limiting rings, photoetching of openings of dielectric layers and photoetching of metal layers are mainly performed, 3 times of photoetching is required for manufacturing the devices, and when a photoetching machine of key equipment is occupied, the output of a production line is limited; the processing cost of the three-time photoetching manufacturing is high, and the profitability of the product is influenced.

Disclosure of Invention

In view of the above problems, the present invention is to provide a method for manufacturing a schottky device, which is suitable for processing a schottky device, and adopts two times of photolithography to achieve self-alignment of a barrier region boundary and a field limiting ring, thereby reducing processing cost and equipment occupation.

In order to solve the technical problems, the invention adopts the technical scheme that: a manufacturing method of a Schottky comprises the following steps:

s1: depositing a dielectric film on a substrate material;

s2: photoetching and etching the field limiting ring;

s3: stripping the dielectric film;

s4: depositing a metal layer;

s5: and carrying out metal photoetching and etching.

Further, a layer of oxygen is formed on the substrate material prior to depositing a dielectric film on the substrate material.

Further, step S2 includes field limiting ring lithography and field limiting ring region etching, where the field limiting ring lithography includes the following steps:

s21: coating a first photoresist, and carrying out field limiting ring exposure and development;

s22: etching after photoetching the field limiting ring by adopting a dry etching process to form a field limiting ring window;

s23: performing ion implantation with the ion implantation dosage of 1.0E13-1.0E 16;

s24: and removing the first photoresist.

Further, the etching of the field limiting ring region comprises the following steps:

s25: etching the dielectric film and the oxide layer in the field limiting ring region;

s26: and carrying out silicon dry etching on the field limiting ring region, and etching through the PN junction.

Further, before etching the field limiting ring region, growing and advancing a first oxidation layer; the method specifically comprises the following steps:

cleaning a wafer; and

the silicon wafer is pushed into a furnace tube to grow and generate a first oxide layer.

Further, before the dielectric film is stripped, an oxide layer is grown, which specifically includes:

cleaning a wafer; and

and (4) entering a furnace tube to be pushed, and growing to generate an oxidation layer, wherein the thickness of the oxidation layer is 300-20000A.

Further, step S3 specifically includes the following steps:

s31: removing the dielectric film: wet etching or dry etching is adopted;

s32: and removing the oxide layer in the barrier region by adopting a self-alignment process.

Further, the metal layer of step S4 includes a barrier metal and a front metal, and the metal layer deposition specifically includes the following steps:

s41: depositing barrier metal to form barrier metal;

s42: and depositing the front metal to form the front metal.

Further, step S5 includes the following steps:

s51: coating a second photoresist, wherein the thickness of the second photoresist is 5000-50000A;

s52: metal photoetching: after exposure and development, wet etching or dry etching is adopted for metal etching;

s53: and removing the second photoresist.

Further, the back of the wafer is processed after metal photoetching and etching.

The invention has the advantages and positive effects that: by adopting the technical scheme, the field limiting ring area is etched in the Schottky preparation process, so that compared with the existing preparation process, one-time photoetching is reduced in the process flow, the production rate is improved, the production cost is reduced, and the occupied time of manufacturing a bottleneck equipment photoetching machine is shortened; the self-alignment technology is adopted to carry out Schottky preparation, and the photoetching step of alignment of the hole layer and the field limiting ring is removed, so that the alignment requirements of the contact hole layer and the field limiting ring can be reduced, and particularly, the field limiting ring structure with small line width is realized; the self-alignment of the boundary of the barrier region and the field limiting ring is realized, and the production efficiency is improved.

Drawings

FIG. 1 is a schematic structural diagram of an embodiment of the present invention;

FIG. 2 is an enlarged view of portion A of FIG. 1;

FIG. 3 is a schematic structural diagram of a substrate material of an embodiment of the present invention;

FIG. 4 is a schematic diagram of a structure after depositing a dielectric film according to one embodiment of the present invention;

FIG. 5 is a schematic diagram of a post-ion implantation structure according to an embodiment of the present invention;

FIG. 6 is a schematic structural view of the furnace tube after being advanced according to an embodiment of the present invention;

FIG. 7 is a schematic diagram of a structure after etching of a field limiting ring region according to an embodiment of the invention;

FIG. 8 is a schematic diagram of a structure of a grown oxide layer according to an embodiment of the present invention;

FIG. 9 is a schematic diagram of a structure after the dielectric film is stripped according to an embodiment of the invention;

FIG. 10 is a schematic diagram of a structure for depositing a barrier metal according to an embodiment of the invention;

FIG. 11 is a schematic structural view of a front metal deposition according to an embodiment of the present invention;

fig. 12 is a schematic structural diagram of the front metal after photolithography and etching according to an embodiment of the present invention.

In the figure:

1. front metal 2, epitaxial layer 3, substrate

4. Back metal 5, barrier metal 6, field limiting ring

7. Oxide layer 8, dielectric film 9, ion implantation

10. A first oxide layer.

Detailed Description

The invention is further described with reference to the following figures and specific embodiments.

Fig. 1 and 2 show a schematic structural diagram of an embodiment of the present invention, specifically showing the structure of the embodiment, the embodiment relates to a schottky manufacturing method, and is used for manufacturing a schottky device structure, fig. 1 and 2 show the schottky device structure manufactured by the method, the schottky device structure is manufactured by using a field limiting ring, a hole self-alignment technology and a LOCOS process, and the self-alignment of a barrier region and the field limiting ring is realized by using two times of photolithography, so that the processing cost and the equipment occupation are reduced, the alignment requirements of a control layer and the field limiting ring are reduced, especially the field limiting ring structure with a small line width is adopted, the number of processed photolithography layers is reduced, the processing cost is reduced, and the occupation time of a photolithography machine for manufacturing bottleneck equipment can be solved.

The manufacturing method of the Schottky comprises the following steps:

s1: firstly, preparing a substrate material, wherein the substrate material comprises a substrate 3 and an epitaxial layer 2, the epitaxial layer 2 is arranged on one side surface of the substrate 3, the epitaxial layer 2 is formed on one side surface of the substrate 3 in an epitaxial mode, and the substrate 3 material is an N-type substrate, which can be an N + substrate, an N-epitaxial layer or other N +/N-type substrates, and is selected according to actual requirements, and no specific requirement is made here. The total thickness of the substrate material is 300-. In this embodiment, taking the preparation on the epitaxial material as an example, a prepared N-type epitaxial substrate material is selected, the substrate is an N + substrate, the epitaxial layer is an N-, and the resistivity of the N-epitaxial layer is 0.01-50 Ω cm, the thickness thereof is 0.1-50um, the resistivity of the N + substrate is 0.0001-10 Ω cm, the thickness is 300-.

Secondly, preparing a layer of cushion oxygen on the substrate material after the substrate material is prepared; namely, a layer of pad oxygen is prepared on the upper surface of the N-epitaxial layer, the preparation of the pad oxygen adopts a thermal oxidation or deposition mode or other modes to oxidize silicon, and the silicon is selected according to actual requirements without specific requirements. The thermal oxidation comprises dry oxidation, wet oxidation, steam oxidation or other oxidation modes; the deposition process mainly refers to chemical vapor deposition, including low-pressure, normal-pressure and plasma chemical vapor deposition, or other deposition processes; no particular requirement is made here. The pad oxygen has a thickness of 10 a-5000 a, selected according to practical requirements, is an oxide layer formed by oxidizing silicon, and the major component is silicon dioxide.

The preparation of the oxygen cushion layer is selected according to the surface condition and the actual requirement of the N-epitaxial layer, can be prepared or not, and the arrangement of the oxygen cushion layer plays a role in buffering between the dielectric film 8 and the silicon surface and slows down the stress of the dielectric film 8 during the direct preparation on the silicon surface.

Thirdly, depositing a dielectric film 8 on the substrate material; that is, if the pad oxygen is prepared, the dielectric film 8 is prepared on the pad oxygen layer; if the pad oxygen layer is not prepared, the pad oxygen layer is directly prepared on the N-epitaxial layer, and the selection is carried out according to whether the pad oxygen layer is prepared or not in the previous step, wherein no specific requirement is made here. The dielectric film 8 is a hard mask layer of silicon nitride or silicon oxynitride having a thickness of 100 a-5000 a, and the dielectric film 8 is disposed to prevent the epitaxial layer 2 from being oxidized. The dielectric film 8 is prepared by a deposition method, and the deposition process mainly refers to chemical vapor deposition, including low-pressure, normal-pressure and plasma chemical vapor deposition, or other deposition processes, and is selected according to actual requirements, as shown in fig. 4.

S2: after the dielectric film 8 is prepared, field limiting ring photoetching is carried out, and ion implantation is carried out; as shown in fig. 5, specifically, including,

s21: coating a first photoresist; coating a layer of photoresist on the dielectric film 8 to facilitate field limiting ring lithography, wherein the first photoresist can be coated by adopting a screen printing or spin coating mode, and the like, the thickness of the first photoresist is 3000A-50000A, and the first photoresist is selected according to actual requirements;

s22: carrying out field limiting ring etching by adopting a dry etching process to form a field limiting ring window; namely, after the first photoresist is coated, the photoresist is subjected to photoetching on the dielectric film 8 according to the shape of the field limiting ring to be prepared, and the photoresist at the position of the field limiting ring to be prepared is removed through developing, so that the subsequent etching of the field limiting ring is facilitated. And after development, etching the dielectric film and the pad oxygen layer by adopting a dry etching process to form a field limiting ring window for facilitating subsequent ion injection, wherein the dry etching process comprises a plasma etching process, a reactive plasma etching process, an enhanced plasma etching process and the like, and selection is carried out according to actual requirements.

S23: after the field limiting ring window is formed, carrying out ion implantation, wherein the ion implantation dosage is 1.0E13-1.0E 16; specifically, after the field limiting ring window is formed, ion implantation is performed by an ion implanter to form the ion implantation layer 9, wherein the implantation dose of the ions is 1.0E13-1.0E16, the dose is determined by withstand voltage, and the selection is performed according to actual requirements.

S24: and removing the first photoresist, and after ion implantation, removing all the first photoresist, wherein dry photoresist removal or wet photoresist removal can be adopted, or mixed dry and wet photoresist removal or other modes are adopted, and selection is performed according to actual requirements.

Before etching the field limiting ring region, growing and advancing a first oxide layer 10; the method specifically comprises the following steps:

cleaning the wafer, namely cleaning the wafer subjected to the field limiting ring photoetching and ion implantation, wherein the cleaning mode is RCA cleaning or other cleaning modes, and the cleaning mode is selected according to actual requirements to remove stains and particles on the surface of the wafer and clean the wafer;

after the wafer is cleaned, the wafer enters a furnace tube for propulsion, and a first oxide layer 10 is grown in a field limiting ring region, as shown in fig. 6, the growth mode of the first oxide layer 10 is a deposition mode or other modes, and is selected according to actual requirements, and the first oxide layer is used for propelling impurity diffusion and simultaneously preventing impurities from diffusing into air.

Etching a field limiting ring region; the oxide layer and the silicon in the field limiting ring region are etched, specifically,

s25: etching the oxide layer in the field limiting ring region, removing the oxide layer in the field limiting ring region, exposing the surface of the silicon as shown in fig. 7, and further performing subsequent silicon etching; the oxide layer comprises the residual oxide layer during the etching of the field limiting ring, or a first oxide layer 10 generated by growth during the advancing of the furnace tube, the oxide layer is mainly an oxide of silicon dioxide, and the etching of the oxide layer can be selected according to actual requirements through dry etching or wet etching, or other etching modes.

S26: carrying out dry etching on the field limiting ring region, and etching through a PN junction: after the oxide layer is removed, dry etching is carried out on silicon in the field limiting ring region, PN junctions are etched through during the etching, parameters of devices are guaranteed, if the PN junctions are not etched and penetrated, the situation that the grooves are wrapped by the field limiting rings after subsequent diffusion can occur, parameters of the devices can be influenced, the grooves are formed after the field limiting ring region is etched, the groove depth of the grooves is related to the advancing depth of the PN junctions and the withstand voltage of the devices, the grooves are selected according to actual requirements, and the groove depth of the grooves is 0.3-10 um.

Meanwhile, after the field limiting ring region is etched, a field limiting ring 6 is formed, the field limiting ring 6 is positioned on the side wall of the groove, and the groove is positioned at the end part of the epitaxial layer 2.

Before the dielectric film 8 is stripped, the growth of an oxidation layer 7 is also carried out, and the method specifically comprises the following steps:

cleaning the wafer passing through the field limiting ring area, removing impurity contamination and particles generated by etching on the surface of the wafer, and cleaning the wafer; the cleaning mode is RAC cleaning or other cleaning modes, and is selected according to actual requirements.

After the wafer is cleaned, the wafer is advanced into a furnace tube, an oxide layer 7 is generated by growth, as shown in fig. 8, the oxide layer 7 is located at a groove, the groove is covered, the thickness of the oxide layer 7 is 300 a-20000 a, which is dependent on the device pressure resistance, the oxide layer is selected according to the actual device pressure resistance, the oxide layer has the function of protecting the exposed silicon surface, and the oxide layer isolates metal from silicon at the same time, otherwise the device parameters are abnormal.

S3: the dielectric film 8 is stripped, and the stripped dielectric film 8 is used for a contact hole self-alignment process without photoetching, so that the number of photoetching layers for processing is reduced, and the processing cost is reduced. In particular, the amount of the solvent to be used,

s31: removing the dielectric film 8: wet etching or dry etching is adopted: and (3) stripping or other wet process or dry etching is carried out by adopting phosphoric acid at the temperature of 100-200 ℃, the dielectric film 8 is removed, and the purpose of removing the dielectric film is to expose the barrier region inside.

S32: and removing the oxide layer of the barrier region by adopting a self-alignment process, removing the pad oxide layer of the barrier region by adopting a wet etching or dry etching mode after the dielectric film is removed, and forming a bare silicon surface for forming the barrier region subsequently, as shown in fig. 9.

S4: depositing a metal layer, wherein the metal layer comprises barrier metal 5 and front metal 1, and the barrier metal deposition and the front metal deposition are respectively carried out, and the metal layer deposition specifically comprises the following steps:

s41: barrier metal deposition to form a barrier metal 5, and evaporation or sputtering to form a barrier alloy in the barrier region, as shown in fig. 10, the barrier metal 5 is titanium or nickel or platinum or other metal.

S42: and depositing front metal to form front metal 1, and performing evaporation or sputtering to form the front metal on the barrier alloy and the upper surface of the oxide layer of the groove, wherein the front metal 1 is aluminum, silver, gold or other metals, as shown in fig. 11.

After the barrier metal is deposited, silicide is generated in the place where silicon exists, the metal on the oxide layer does not react, and the barrier metal is stripped according to the actual situation.

S5: metal lithography and etching are performed to remove a portion of the front metal 1 at the end portion within the trench, as shown in fig. 12, specifically,

s51: coating a second photoresist with the thickness of 5000-50000A, and selecting according to actual requirements;

s52: metal photoetching and etching: after the second photoresist is coated, metal etching is carried out through exposure and development and wet etching or dry etching, and the metal 1 on the front side of the end part of the bottom of the groove is removed;

s53: and removing the second photoresist after metal photoetching and etching.

Carrying out wafer back processing after metal photoetching and etching: according to the conventional wafer back processing technology, the back metal 4 is formed by film pasting, thinning, silicon etching, film uncovering, cleaning and back metallization, which is the prior art and is not described in detail herein.

A schottky barrier structure, as shown in fig. 1 and 2, includes a substrate material, the substrate material includes a substrate 3 and an epitaxial layer 2, the epitaxial layer 2 is disposed on one side of the substrate 3, the epitaxial layer 2 is formed on one side of the substrate 3 by epitaxy, the substrate material may be an N-type substrate, including but not limited to an N + substrate, an N-epitaxial layer, or other N +/N-type substrate, and is selected according to actual requirements, and is not specifically required here.

The schottky termination structure further includes:

and the groove is formed on the epitaxial layer 2 through photoetching and is positioned at the end part of the epitaxial layer 2, the cross section of the groove is in an L shape, and the groove is used for cutting off the protection ring and reducing the surface electric field of the device.

The length of the front metal 1 at the bottom of the groove is less than that of the oxide layer 7 at the bottom of the groove, and the front metal 1 includes but is not limited to metals such as aluminum, silver, gold and the like;

the bottom of the groove is of a field plate structure, the length of the field plate is 5-300um, and the length is selected according to the voltage-resistant grade of the device.

The depth of the groove is 0.3-10um, the groove is selected according to the voltage-resistant grade of the device, the depth of the groove is larger than or equal to the depth of the field limiting ring 6, the influence on the parameters of the device is reduced, the field limiting ring 6 is cut off by the groove, automatic quasi-process etching is adopted, and processes such as photoetching are not needed.

A field limiting ring 6 formed on the side wall of the corner of the trench by ion implantation; the width of the field limiting ring 6 is 0.3-10um, and is selected according to the voltage-resistant grade of the device; the depth of the field limiting ring 6 is 0.3-10um, and is selected according to the voltage-resistant grade of the device. The field limiting ring 6 is a P-type impurity, which can be boron, aluminum or other P-type impurities, and is selected according to actual requirements, and the doping concentration of the P-type impurity is 1.0E12-1.0E 18. The size of the field limiting ring 6 is smaller than that of a conventional field limiting ring structure, and only a small part of the conventional field limiting ring is needed to protect the boundary of the barrier layer in structural view, so that the voltage resistance of the device is ensured. The structure adopts a diffusion self-alignment process, the photoetching capability is not required, the field limiting ring has the function of protecting the boundary of the barrier region, electric field concentration can occur if the boundary of the barrier region is not protected, the device is low in breakdown, and the breakdown voltage of the barrier boundary can be improved by the field limiting ring.

The oxidation layer 7 is arranged on the side wall of the groove, the bottom of the groove and the corner of the groove, and can form growth on the side wall, the bottom and the corner of the groove in an oxidation or deposition mode; the oxide layer 7 is a single-layer or multi-layer dielectric film structure, and the dielectric film is preferably silicon oxide generated by oxidation of silicon, and the dielectric layer has a thickness of 200 a-20000 a, the oxide layer serving to protect the bare silicon surface while the oxide layer isolates metal from silicon, otherwise the device parameters are abnormal.

The barrier metal 5 is formed on the epitaxial layer 2 by deposition, which is evaporation or sputtering, and includes but is not limited to metals such as titanium, nickel, platinum, etc., and the barrier metal functions to form a schottky contact, which is a basic structure of a schottky device and can realize a low forward conducting voltage and a certain voltage tolerance in a reverse direction.

The front metal 1 is formed on the barrier metal 5 and the oxide layer 7 by deposition, the deposition mode is evaporation or sputtering, the front metal 1 includes but is not limited to metals such as aluminum, silver, gold and the like, and the front metal is used as an electrode connected with a tube shell when a chip is packaged.

And the other side of the substrate is provided with a back metal 4, the back metal adopts the conventional wafer back processing technology, and the steps of film sticking, thinning, silicon corrosion, film uncovering, cleaning and back metallization are carried out, and the back metal is used as an electrode connected with a tube shell during chip packaging.

When the device is reversely biased, the extension path of the electric field boundary of the terminal structure of the Schottky device is from the field limiting ring 6 to the corner of the groove and then to the flat silicon-oxygen interface at the bottom of the groove, and the electric field is excessively stable. The electric field expansion path is from the longitudinal direction to the transverse direction, and compared with a field limiting ring structure, the transverse dimension can be smaller to achieve the same voltage resistance.

The Schottky device is manufactured by two layers of photoetching, the size of a terminal voltage-resistant structure is reduced, the size of the terminal is smaller than that of a conventional design under the same voltage level, and the utilization rate of the area of a chip is effectively improved; the structure has a withstand voltage protection structure which protects the barrier region boundary of the field limiting ring and expands an electric field to the bottom of the groove, the manufacture of a device is realized without hole lithography through the self-aligned field limiting ring, the groove and the contact hole, the field limiting ring is used for protecting the barrier region boundary and expanding the electric field to the bottom of the groove to ensure the withstand voltage of the device, the structure has a small terminal structure and fewer photoetching layers; the device of different voltage classes can be through the depth of junction and the concentration of adjustment field limiting ring and the depth of the groove of matching and the thickness of trench oxidation, can realize the device structure and withstand voltage of full voltage platform, and one set of photoetching version can realize that different voltage classes are the same size schottky device and make, supports all voltage platforms, and the same terminal design can general different voltage the same size schottky device, need not change the version again, reduces the use amount of photoetching version.

While one embodiment of the present invention has been described in detail, the description is only a preferred embodiment of the present invention and should not be taken as limiting the scope of the invention. All equivalent changes and modifications made within the scope of the present invention shall fall within the scope of the present invention.

Claims

1. A manufacturing method of a Schottky is characterized in that: the method comprises the following steps:

s1: depositing a dielectric film on a substrate material;

s2: photoetching and etching the field limiting ring;

the step S2 includes field limiting ring photoetching and field limiting ring area etching, the field limiting ring photoetching includes the following steps:

s21: coating a first photoresist, and carrying out exposure and development on the field limiting ring;

s22: etching the field limiting ring after photoetching by adopting a dry etching process to form a field limiting ring window;

s23: carrying out ion implantation, wherein the ion implantation dosage is 1.0E13-1.0E 16;

s24: removing the first photoresist;

before etching the field limiting ring region, growing and advancing a first oxide layer, wherein the first oxide layer is positioned in the field limiting ring region;

the etching of the field limiting ring region comprises the following steps:

s25: etching the first oxide layer of the field limiting ring region;

s26: carrying out silicon dry etching on the field limiting ring region, and etching through a PN junction to form a groove;

growing an oxide layer, wherein the oxide layer is positioned on the side wall of the groove, the bottom of the groove and the corner of the groove;

s3: stripping the dielectric film;

s4: depositing a metal layer;

s5: and carrying out metal photoetching and etching.

2. The method of manufacturing a schottky as described in claim 1, wherein: preparing a layer of pad oxygen on the substrate material before depositing a layer of dielectric film on the substrate material.

3. The method of manufacturing a schottky as described in claim 1, wherein:

the growing and advancing of the first oxidation layer specifically comprises:

cleaning a wafer; and

and (4) entering a furnace tube for propulsion, and growing to generate the first oxide layer.

4. The method of manufacturing a schottky as claimed in claim 1 or 3, wherein: the growing of the oxide layer specifically comprises:

cleaning a wafer; and

and (3) entering a furnace tube to be pushed, and growing to generate an oxidation layer, wherein the thickness of the oxidation layer is 300A-20000A.

5. The method of manufacturing a schottky as claimed in claim 2, wherein: the step S3 specifically includes the following steps:

s31: removing the dielectric film: wet etching or dry etching is adopted;

s32: and removing the oxygen in the barrier region by adopting a self-alignment process.

6. The method of manufacturing a schottky as claimed in claim 5, wherein: the metal layer of the step S4 includes a barrier metal and a front metal, and the metal layer deposition specifically includes the following steps:

s41: depositing the barrier metal to form the barrier metal;

s42: and depositing the front metal to form the front metal.

7. The method of manufacturing a schottky as claimed in claim 5 or 6, wherein: the step S5 includes the steps of:

s53: and removing the second photoresist.

8. The method of manufacturing a schottky as described in claim 7, wherein: and carrying out wafer back processing after the metal is subjected to photoetching and etching.