CN210110775U - Schottky terminal structure - Google Patents

Abstract

The utility model provides a Schottky terminal structure, which comprises a substrate material, wherein the substrate material comprises a substrate and an epitaxial layer, and the epitaxial layer is arranged on one side of the substrate; and a trench formed on the epitaxial layer by etching; the field limiting ring is formed on the side wall of the groove through ion implantation; the oxide layer is arranged on the side wall of the groove, the bottom of the groove and the corner of the groove; a barrier metal formed on the epitaxial layer by deposition; and the front metal is formed on the barrier metal and the oxide layer through deposition. The beneficial effects of the utility model are that have field limiting ring, slot, contact hole self-alignment structure, realize that two-layer photoetching makes the schottky device, reduce the size of the withstand voltage structure in terminal, terminal size compares conventional design and will be little under the same voltage class, effectively promotes chip area's utilization ratio.

Description

Schottky terminal structure

Technical Field

The utility model belongs to the technical field of semiconductor device, especially, relate to a schottky terminal structure.

Background

At present, most of terminal structures of common Schottky devices are structures of field limiting rings and field plates, the field limiting ring structures are used for protecting boundaries of Schottky junctions and avoiding low breakdown, the field limiting rings of the structures are wide, the area of the terminal structures is large, the area of a chip occupied by the Schottky devices at low pressure is high, and the area of the part of the area does not contribute to forward conduction of the devices. The voltage resistance of the field limiting ring structure needs a certain width, so that the occupied size of the voltage resistance structure of the protection ring is large, and the area of the voltage resistance structure does not have obvious effect on forward conduction of the device. Especially in low voltage devices. Meanwhile, the field limiting ring needs to be aligned and photoetched when the subsequent pore layer is photoetched, so that the photoetching process is required. Relatively high-end lithographic equipment is required, increasing processing costs. Devices of the same size at different voltage levels typically require different sized termination designs, i.e., different reticles, to be fabricated. Adding to the manufacturing overhead of the reticle.

Disclosure of Invention

In view of the above, the to-be-solved problem of the present invention is to provide a schottky terminal structure, reduce the size of the terminal withstand voltage structure, improve chip effective area's utilization ratio.

In order to solve the technical problem, the utility model discloses a technical scheme is: a Schottky terminal structure comprises a substrate material, wherein the substrate material comprises a substrate and an epitaxial layer, and the epitaxial layer is arranged on one side of the substrate; and

a trench formed on the epitaxial layer by etching;

the field limiting ring is formed on the side wall of the groove through ion implantation;

the oxide layer is arranged on the side wall of the groove, the bottom of the groove and the corner of the groove;

a barrier metal formed on the epitaxial layer by deposition;

and the front metal is formed on the barrier metal and the oxide layer through deposition.

Furthermore, the groove is arranged at the end part of the epitaxial layer, and the cross section of the groove is L-shaped.

Further, the length of the front metal at the bottom of the trench is smaller than that of the oxide layer at the bottom of the trench.

Furthermore, the bottom of the trench is provided with a field plate structure.

Furthermore, the oxide layer is of a single-layer or multi-layer dielectric film structure, and the dielectric film is silicon oxide.

Furthermore, the depth of the field limiting ring is 0.3-10 um.

Further, the width of the field limiting ring is 0.3-10 um.

Furthermore, the field limiting ring is a P-type impurity, and the doping concentration is 1.0E12-1.0E 18.

Further, the other side of the substrate is provided with back metal.

The utility model has the advantages and positive effects that:

1. by adopting the technical scheme, the Schottky device is manufactured by two layers of photoetching due to the self-alignment structure of the field limiting ring, the groove and the contact hole, the size of the terminal voltage-resistant structure is reduced, the size of the terminal under the same voltage level is smaller than that of a conventional design, and the utilization rate of the area of a chip is effectively improved;

2. the structure has a voltage-resistant protection structure which protects the boundary of a barrier region by a field limiting ring and expands an electric field to the bottom of a groove, the voltage resistance of a device is realized without hole photoetching through the self-aligned field limiting ring, the groove and a contact hole, the field limiting ring is used for protecting the boundary of the barrier and expands the electric field to the bottom of the groove to ensure the voltage resistance of the device, the structure has a small terminal structure and fewer photoetching layers;

3. the device of different voltage classes can be through the depth of junction and the concentration of adjustment field limiting ring and the depth of the slot of matching and the thickness of slot oxidation, can realize the device structure and withstand voltage of full voltage platform, and one set of photoetching version can realize that the same size of different voltage classes schottky device makes, supports all voltage platforms, and the same terminal design can general different voltage same size schottky devices, need not change the version again, reduces the use amount of photoetching version.

Drawings

Fig. 1 is a schematic structural diagram of an embodiment of the present invention;

fig. 2 is an enlarged view of a portion a of fig. 1.

In the figure:

1. front metal 2, epitaxial layer 3, substrate

4. Back metal 5, barrier metal 6, field limiting ring

7. Oxide layer

Detailed Description

The invention will be further described with reference to the accompanying drawings and specific embodiments.

Fig. 1 and 2 show a schematic structural diagram of an embodiment of the present invention, specifically showing the structure of the embodiment, the embodiment relates to a schottky termination structure, and the self-aligned field limiting ring, trench, contact hole do not need to be etched to realize the withstand voltage of the device, the field limiting ring is used to protect the barrier boundary and simultaneously extend the electric field to the bottom of the trench to ensure the withstand voltage of the device; and the structure terminal structure is small, and the number of photoetching layers is small. Meanwhile, devices of different voltage levels can realize the device structure and withstand voltage of a full-voltage platform by adjusting the junction depth and concentration of the field limiting ring, the depth of the matched groove and the thickness of the groove oxidation, and one set of photoetching plate can realize the manufacture of Schottky devices of different voltage levels and the same size without re-edition.

Specifically, as shown in fig. 1 and 2, the schottky barrier structure includes a substrate material, the substrate material includes a substrate 3 and an epitaxial layer 2, the epitaxial layer 2 is disposed on one side of the substrate 3, the epitaxial layer 2 is formed on one side of the substrate 3 through an epitaxial process, and the substrate material may be an N-type substrate, including but not limited to an N + substrate, an N-epitaxial layer, or other N +/N-type substrates, and is selected according to actual requirements, which is not specifically required here.

The schottky termination structure further includes:

and the groove is formed on the epitaxial layer 2 through photoetching and is positioned at the end part of the epitaxial layer 2, the cross section of the groove is in an L shape, and the groove is used for cutting off the protection ring and reducing the surface electric field of the device.

The length of the front metal 1 at the bottom of the trench is less than that of the oxide layer 7 at the bottom of the trench, and the front metal 1 includes but is not limited to aluminum, silver, gold and other metals.

The bottom of the groove is of a field plate structure, the length of the field plate is 5-300um, and the length is selected according to the voltage-resistant grade of the device.

The depth of the groove is 0.3-10um, the groove is selected according to the voltage-resistant grade of the device, the depth of the groove is larger than or equal to the depth of the field limiting ring 6, the influence on the parameters of the device is reduced, the field limiting ring 6 is cut off by the groove, automatic quasi-process etching is adopted, and processes such as photoetching are not needed.

A field limiting ring 6 formed on the side wall of the corner of the trench by ion implantation; the width of the field limiting ring 6 is 0.3-10um, and is selected according to the voltage-resistant grade of the device; the depth of the field limiting ring 6 is 0.3-10um, and is selected according to the voltage-resistant grade of the device. The field limiting ring 6 is a P-type impurity, which can be boron, aluminum or other P-type impurities, and is selected according to actual requirements, and the doping concentration of the P-type impurity is 1.0E12-1.0E 18. The size of the field limiting ring 6 is smaller than that of a conventional field limiting ring structure, and only a small part of the conventional field limiting ring is needed to protect the boundary of the barrier layer in structural view, so that the voltage resistance of the device is ensured. The structure adopts a diffusion self-alignment process, the photoetching capability is not required, the field limiting ring has the function of protecting the boundary of the barrier region, electric field concentration can occur if the boundary of the barrier region is not protected, the device is low in breakdown, and the breakdown voltage of the barrier boundary can be improved by the field limiting ring.

The oxidation layer 7 is arranged on the side wall of the groove, the bottom of the groove and the corner of the groove, and can form growth on the side wall, the bottom and the corner of the groove in an oxidation or deposition mode; the oxide layer 7 is a single-layer or multi-layer dielectric film structure, the dielectric film is preferably silicon oxide generated by silicon oxidation, the thickness of the dielectric layer is 200A-20000A, the oxide layer is used for protecting the exposed silicon surface, and meanwhile, the oxide layer isolates metal from silicon, otherwise, the parameters of the device are abnormal.

The barrier metal 5 is formed on the epitaxial layer 2 by deposition, the deposition is evaporation or sputtering, the barrier metal 5 includes but is not limited to metals such as titanium, nickel, platinum, etc., the barrier metal is used for forming a schottky contact, and the schottky contact is a basic structure of a schottky device, and can realize the endurance of a forward conducting voltage and a reverse voltage.

The front metal 1 is formed on the barrier metal 5 and the oxide layer 7 by deposition, the deposition mode is evaporation or sputtering, the front metal 1 includes but is not limited to metals such as aluminum, silver, gold and the like, and the front metal is used as an electrode connected with a tube shell when a chip is packaged.

And the other side of the substrate is provided with a back metal 4, the back metal adopts the conventional wafer back processing technology, and the steps of film pasting, thinning, silicon corrosion, film uncovering, cleaning and back metallization are carried out, and the back metal is used as an electrode connected with a tube shell during chip packaging.

The self-alignment structure is realized by that the residual dielectric film layer after the first layer of photoetching and etching hinders oxidation, the dielectric film layer and other areas after the pad oxygen stripping are all provided with oxidation layers, the non-self-alignment structure generally exposes the silicon surface of the barrier region through photoetching and etching, and the self-alignment structure does not need photoetching. When the device is reversely biased, the electric field boundary extension path of the Schottky terminal structure is from the field limiting ring to the corner of the groove and then to the flat silicon-oxygen interface at the bottom of the groove, and the electric field is excessively stable. The electric field expansion path is from the longitudinal direction to the transverse direction, and compared with a field limiting ring structure, the transverse dimension can be smaller to achieve the same voltage resistance.

The manufacturing method of the Schottky comprises the following steps:

s1: firstly, preparing a substrate material, wherein the substrate material comprises a substrate 3 and an epitaxial layer 2, the epitaxial layer 2 is arranged on one side surface of the substrate 3, the epitaxial layer 2 is formed on one side surface of the substrate 3 through an epitaxial process, the substrate 3 material is an N-type substrate, and can be an N + substrate, an N-epitaxial layer or other types of substrate materials with an N-/N + structure, and the substrate material is selected according to actual requirements without specific requirements. The total thickness of the substrate material is 300-. In this embodiment, taking the preparation on the epitaxial material as an example, a prepared N-type epitaxial substrate material is selected, the substrate is an N + substrate, the epitaxial layer is an N-, and the resistivity of the N-epitaxial layer is 0.01-50 Ω cm, the thickness thereof is 0.1-50um, the resistivity of the N + substrate is 0.0001-10 Ω cm, the thickness is 300-.

Secondly, preparing a layer of cushion oxygen on the substrate material after the substrate material is prepared; namely, a layer of pad oxygen is prepared on the upper surface of the N-epitaxial layer, the preparation of the pad oxygen adopts a thermal oxidation or deposition mode or other modes to oxidize silicon, and the pad oxygen is selected according to actual requirements without specific requirements. The thermal oxidation comprises dry oxidation, wet oxidation, steam oxidation or other oxidation modes; the deposition process mainly refers to chemical vapor deposition, including low-pressure, normal-pressure and plasma chemical vapor deposition, or other deposition processes; no particular requirement is made here. The thickness of the pad oxygen is 10A-5000A, and the pad oxygen is selected according to actual requirements, is an oxide layer and is formed by oxidizing silicon, and the main component of the pad oxygen is silicon dioxide.

The preparation of the oxygen cushion layer is selected according to the surface condition and the actual requirement of the N-epitaxial layer, can be prepared or not, and the arrangement of the oxygen cushion layer plays a role in buffering between the dielectric film 8 and the silicon surface and slows down the stress of the dielectric film 8 when the silicon surface is directly prepared.

Thirdly, depositing a dielectric film 8 on the substrate material; that is, if the pad oxygen is prepared, the dielectric film 8 is prepared on the pad oxygen layer; if the pad oxygen layer is not prepared, the pad oxygen layer is directly prepared on the N-epitaxial layer, and the selection is carried out according to whether the pad oxygen layer is prepared in the previous step or not, wherein no specific requirement is made. The dielectric film 8 is a hard mask layer of silicon nitride or silicon oxynitride, the thickness of the hard mask layer is 100A-5000A, and the epitaxial layer 2 can be prevented from being oxidized due to the arrangement of the dielectric film 8. The preparation method of the dielectric film 8 adopts a deposition method, and the deposition process mainly refers to chemical vapor deposition, including low-pressure, normal-pressure and plasma chemical vapor deposition, or other deposition processes, and is selected according to actual requirements.

S2: after the dielectric film 8 is prepared, field limiting ring photoetching is carried out, and ion implantation is carried out; in particular, it comprises, in particular,

s21: coating a first photoresist; coating a layer of photoresist on the dielectric film 8 to facilitate field limiting ring photoetching, wherein the first photoresist can be coated in a screen printing or spin coating mode, the thickness of the first photoresist is 3000A-50000A, and the first photoresist is selected according to actual requirements;

s22: performing field limiting ring etching by adopting a dry etching process to form a field limiting ring window; namely, after the first photoresist is coated, the photoresist is subjected to photoetching on the dielectric film 8 according to the shape of the field limiting ring to be prepared, and the photoresist at the position of the field limiting ring to be prepared is removed through development, so that the subsequent etching of the field limiting ring is facilitated. And after development, etching the dielectric film and the pad oxygen layer by adopting a dry etching process to form a field limiting ring window for facilitating subsequent ion injection, wherein the dry etching process comprises a plasma etching process, a reactive plasma etching process, an enhanced plasma etching process and the like, and selection is carried out according to actual requirements.

S23: after the field limiting ring window is formed, carrying out ion implantation, wherein the ion implantation dosage is 1.0E13-1.0E 16; specifically, after the field limiting ring window is formed, ion implantation is performed by an ion implanter to form the ion implantation layer 9, wherein the implantation dose of the ions is 1.0E13-1.0E16, the dose is determined by withstand voltage, and the selection is performed according to actual requirements.

S24: and removing the first photoresist, and after ion implantation, removing all the first photoresist, wherein dry photoresist removal or wet photoresist removal can be adopted, or mixed dry and wet photoresist removal or other modes are adopted, and selection is performed according to actual requirements.

Before etching the field limiting ring region, growing a first oxide layer 10; the method specifically comprises the following steps:

cleaning the wafer, namely cleaning the wafer subjected to the field limiting ring photoetching and ion implantation, wherein the cleaning mode is RCA cleaning or other cleaning modes, and the cleaning mode is selected according to actual requirements to remove stains and particles on the surface of the wafer and clean the wafer;

after the wafer is cleaned, the wafer enters a furnace tube for propulsion, a first oxidation layer 10 is generated in a field limiting ring area in a growing mode, the growing mode of the first oxidation layer 10 is a deposition mode or other modes, selection is carried out according to actual requirements, and the first oxidation layer is used for propelling impurity diffusion and avoiding the impurity from diffusing into the air.

S3: etching a field limiting ring region; the oxide layer and the silicon in the field limiting ring region are etched, specifically,

s31: and etching the oxide layer in the field limiting ring region, removing the oxide layer in the field limiting ring region, exposing the surface of silicon, and further performing subsequent silicon etching, wherein the oxide layer comprises the oxide layer remained during the field limiting ring etching, or a first oxide layer 10 generated by growth when a furnace tube is pushed, the oxide layer is mainly an oxide of silicon dioxide, and the etching of the oxide layer can be selected according to actual requirements through dry etching or wet etching, or other etching modes.

S32: carrying out dry etching on the field limiting ring region, and etching through a PN junction: after the oxide layer is removed, dry etching is carried out on silicon in the field limiting ring region, PN junctions are etched through during the etching, parameters of devices are guaranteed, if the PN junctions are not etched and penetrated, the situation that the grooves are wrapped by the field limiting rings after subsequent diffusion can occur, parameters of the devices can be influenced, the grooves are formed after the field limiting ring region is etched, the groove depth of the grooves is related to the advancing depth of the PN junctions and the withstand voltage of the devices, the grooves are selected according to actual requirements, and the groove depth of the grooves is 0.3-10 um.

Meanwhile, after the field limiting ring region is etched, a field limiting ring 6 is formed, the field limiting ring 6 is positioned on the side wall of the groove, and the groove is positioned at the end part of the epitaxial layer 2.

Before the dielectric film 8 is stripped, the growth of an oxidation layer 7 is also carried out, and the method specifically comprises the following steps:

cleaning the wafer passing through the field limiting ring area, removing contamination and particles generated by etching on the surface of the wafer, and cleaning the wafer; the cleaning mode is RAC cleaning or other cleaning modes, and is selected according to actual requirements.

After the wafer is cleaned, the wafer enters a furnace tube to be pushed, an oxide layer 7 is generated by growth, the oxide layer 7 is located at the groove and covers the groove, the thickness of the oxide layer 7 is 300A-20000A, the oxide layer is selected according to the withstand voltage of an actual device, the oxide layer is used for protecting the exposed silicon surface, meanwhile, the oxide layer isolates metal from silicon, and otherwise, the parameters of the device are abnormal.

S4: the dielectric film 8 is stripped, and the stripped dielectric film 8 is used for a contact hole self-alignment process without photoetching, so that the number of photoetching layers for processing is reduced, and the processing cost is reduced. In particular, the amount of the solvent to be used,

s41: removing the dielectric film 8: adopting a wet process or a dry etching: stripping or other wet process or dry etching is carried out by adopting phosphoric acid at the temperature of 100-200 ℃, the dielectric film 8 is removed, and the purpose of removing the dielectric film is to expose the potential barrier region inside;

s42: and removing the oxide layer of the barrier region by adopting a self-alignment process, and removing the oxygen cushion layer of the barrier region by adopting a wet etching or dry etching mode after the dielectric film is removed to form a bare silicon surface for forming the barrier region subsequently.

S5: depositing a metal layer, wherein the metal layer comprises barrier metal 5 and front metal 1, and the barrier metal deposition and the front metal deposition are respectively carried out, and the metal layer deposition specifically comprises the following steps:

s51: depositing barrier metal to form barrier metal 5, and depositing barrier metal by evaporation or sputtering to form a barrier alloy in the barrier region, wherein the barrier metal 5 is titanium or nickel or platinum or other metals.

S52: and depositing front metal to form front metal 1, performing the front metal deposition by adopting evaporation or sputtering, and forming the front metal on the barrier alloy and the upper surface of the oxide layer of the groove, wherein the front metal 1 is aluminum, silver, gold or other metals.

After the barrier metal is deposited, silicide is generated in the place where silicon exists, the metal on the oxide layer does not react, and the barrier metal is stripped according to the actual situation.

S6: and performing metal photoetching and etching to remove part of the front metal 1 at the end part in the groove, specifically,

s61: coating a second photoresist, wherein the thickness of the second photoresist is 5000-50000A, and selecting according to actual requirements;

s62: metal photoetching and etching: after the second photoresist is coated, metal etching is carried out through exposure and development and wet etching or dry etching, and the metal 1 on the front side of the end part of the bottom of the groove is removed;

s63: and after metal photoetching, removing the second photoresist.

Carrying out wafer back processing after metal photoetching: according to the conventional wafer back processing technology, the back metal 4 is formed by film pasting, thinning, silicon corrosion, film uncovering, cleaning and back metallization, which is the prior art and is not described in detail herein.

The utility model has the advantages and positive effects that: by adopting the technical scheme, the Schottky device is manufactured by 2-layer photoetching due to the self-alignment structure of the field limiting ring, the groove and the contact hole, the size of the terminal voltage-resistant structure is reduced, the size of the terminal under the same voltage level is smaller than that of a conventional design, and the utilization rate of the area of a chip is effectively improved; the structure has a voltage-resistant protection structure which protects the boundary of a barrier region by a field limiting ring and expands an electric field to the bottom of a groove, the voltage resistance of a device is realized without hole photoetching through the self-aligned field limiting ring, the groove and a contact hole, the field limiting ring is used for protecting the boundary of the barrier and expands the electric field to the bottom of the groove to ensure the voltage resistance of the device, the structure has a small terminal structure and fewer photoetching layers; the device of different voltage classes can be through the depth of junction and the concentration of adjustment field limiting ring and the depth of the slot of matching and the thickness of slot oxidation, can realize the device structure and withstand voltage of full voltage platform, and one set of photoetching version can realize that the same size of different voltage classes schottky device makes, supports all voltage platforms, and the same terminal design can general different voltage same size schottky devices, need not change the version again, reduces the use amount of photoetching version.

While one embodiment of the present invention has been described in detail, the description is only a preferred embodiment of the present invention, and should not be considered as limiting the scope of the present invention. All the equivalent changes and improvements made according to the application scope of the present invention should still fall within the patent coverage of the present invention.

Claims (9)

1. A Schottky termination structure characterized in that: the epitaxial layer is arranged on one side of the substrate; and

a trench formed on the epitaxial layer by etching;

the field limiting ring is formed on the side wall of the groove through ion implantation;

the oxide layer is arranged on the side wall of the groove, the bottom of the groove and the corner of the groove;

a barrier metal formed on the epitaxial layer by deposition;

and the front metal is formed on the barrier metal and the oxide layer through deposition.

2. The schottky termination structure of claim 1 wherein: the groove is arranged at the end part of the epitaxial layer, and the cross section of the groove is L-shaped.

3. The schottky termination structure of claim 2 wherein: the length of the front metal at the bottom of the groove is smaller than that of the oxide layer at the bottom of the groove.

4. The schottky termination structure of claim 3 wherein: the bottom of the groove is of a field plate structure.

5. The schottky termination structure of any one of claims 1-4 wherein: the oxide layer is of a single-layer or multi-layer dielectric film structure, and the dielectric film is silicon oxide.

6. The schottky termination structure of claim 5 wherein: the depth of the field limiting ring is 0.3-10 um.

7. The schottky termination structure of claim 6 wherein: the width of the field limiting ring is 0.3-10 um.

8. The schottky termination structure of claim 7 wherein: the field limiting ring is a P-type impurity, and the doping concentration is 1.0E12-1.0E 18.

9. The schottky termination structure of any one of claims 6-8 wherein: and back metal is arranged on the other side of the substrate.

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