CN110291633A - For can parallelization integrated power chip method and electric power electronic module - Google Patents

For can parallelization integrated power chip method and electric power electronic module Download PDF

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Publication number
CN110291633A
CN110291633A CN201780086323.9A CN201780086323A CN110291633A CN 110291633 A CN110291633 A CN 110291633A CN 201780086323 A CN201780086323 A CN 201780086323A CN 110291633 A CN110291633 A CN 110291633A
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substrate
lamination
manufacturing
unit
sub
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CN110291633B (en
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弗里德瓦尔德·基尔
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Vidiko Institute
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Vidiko Institute
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/11—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/117—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/46—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids
    • H01L23/473—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements involving the transfer of heat by flowing fluids by flowing liquids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/60—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/05—Insulated conductive substrates, e.g. insulated metal substrate
    • H05K1/056—Insulated conductive substrates, e.g. insulated metal substrate the metal substrate being covered by an organic insulating layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10166—Transistor

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Geometry (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

The present invention relates to a kind of methods, comprising: 1) manufacture first substrate (EB1) and the second substrate, the manufacture includes use space reservation device (HM1, HM2), the first substrate and the second substrate are made up of the lamination insulation in the copper plates for forming substrate (MB1) and layer (PP, CP), in a substrate, which has matched profile at upper laminating surface at least one electronic chip sandwiched；2) it is stacked by the matching profile of substrate and engages substrate；And 3) pressure assembling is carried out to the substrate, to manufacture the lamination sub-unit for being used for integrated power electronic equipment.This method needs the technology using referred to as IMS type.

Description

For can parallelization integrated power chip method and electric power electronic module
Cross reference to related applications
The present invention claims submitted on December 12nd, 2016 application No. is the preferential of 1662335 french patent application Power, content (text, drawings and claims) are incorporated herein by reference.
Technical field
The present invention relates generally to field of power electronics.More particularly it relates to which a kind of be used for integrated power electronics core The method of piece, this method allow parallel production.The invention further relates to by implementing the manufactured power electronic equipment of the above method And module.
Background technique
Integrated electronic chip is substantially continuity process to manufacture circuit.When thus leading to manufacture that may be relatively long Between, and the manufacturing time generates significant impact to cost.It is well known that manufacturing process parallelization is for reducing manufacturing time With the solution for increasing yield, however if not promotion property technological progress, the parallelization of the manufacturing process is usually required Great amount of investment.
In numerous area of activities of such as transport, industry, illumination, heating etc., the electric power of generally existing such as power module Electronic circuit.With towards renewable and generate less CO2The energy of discharge carries out desired energy transition, power electronic technique It will further be popularized, and must cope with the limitation in ever-increasing economic and technical.For example, in transport field, vapour Restriction of the turner industry by extremely stringent emission standard, these standards have caused real technology by the electrification of vehicle It changes.The case where prevailing stringent weight limitation, volumetric constraint and cost limit in facing large-scale production industry Under, the electrified of vehicle needs to realize technological progress in the integrated approach of power electronic chip.
Under the current state of technology, it improves integrated level usually using the referred to as technology of HDI and reduces the ruler of power module Very little, HDI is " High Density Interconnect (high density interconnection) " in English.In general, in the referred to as printing of PCB The HDI technology realized on circuit is based on the setting optimization of the space of component, and the optimization of space setting is especially by using Thinner interconnection belt is carried out with the interconnection microvia for being known as " micropore ", and wherein PCB refers to " the Printed Circuit in English Board (printed circuit board) ".Using laser drill and the Transient liquid phase of such as soldering, referred to as TLP welding welds or gold The powder sintered various welding techniques of metal nano-particle.
It is also known that stack printed circuit board is to manufacture 3D framework.Therefore, application DE102014010373A1 is proposed A kind of electronic module comprising the first printed circuit board and the second printed circuit board, the first printed circuit board and the second printing electricity Road plate is stacked and respectively includes electronic building brick.Using sintering method plate to link together.In addition, application US2016/ 133558A1 describes a kind of power module comprising the central printed circuit board being clipped between two heat sinks.Electronic building brick It is mounted in median plate.
However, having in face of cost reduction and the raising of integrated level and compactedness, HDI technology needed for large-scale production Limitation.In fact, used certain technologies of such as laser drill can not make the parallelization of production process become simpler It is single, the obstruction of price reduction is formed instead.
Achievable integrated level is received through volumetric constraint occupied by band and micropore interconnection.These pass through band or micropore Interconnection introduces parasitic inductance, these parasitic inductances are mutually resisted with higher chopping frequency or switching frequency.It is generated to reduce Heat and protect the circuit from potential destructive overvoltage, need to reduce parasitic inductance.However, especially being converted in power The increase of switching frequency is conducive to compactedness in device.
Increasing for integrated level needs to improve the thermal confinement to component with the compactedness of electron power module.Need high-performance cold But to keep the temperature of active component and passive element lower than critical-temperature, thus reach thermal balance and guarantee power module can By property.For this purpose, the framework of power module and used technology must be allowed in the energy to dissipate closest to extraction at component.
It now appear that it is expected that propose a kind of new technology, integrated power electronic equipment of the technology in such as power module Progress is realized in parallel manufacture and in the integrated and compactedness of equipment of electronic chip.
Summary of the invention
According in a first aspect, this method is for manufacturing the present invention relates to a kind of method for integrated power electronic chip It is laminated sub-unit, which is used for integrated power electronic equipment.According to the present invention, this method comprises:
It manufactures first substrate and the second substrate, the manufacture includes use space reservation device, each of substrate passes through Inner insulating layer and layer are laminated on the plate for forming metallic substrates and is made, at least one electronic chip is arranged in the first base In any of plate and the second substrate, and first substrate and the second substrate manufacture have matched wheel at laminating surface thereon It is wide；
By having the upper surface of the first substrate of matching profile and the second substrate to stack and engage first substrate and the Two substrates；And
Pressure assembling is carried out to first substrate and the second substrate, to manufacture the lamination point for integrated power electronic equipment Assembly.
Specific features in accordance with the invention, space to be preserved device is for generating at least one position, and the position is at least One chip.
According to another special characteristic, the manufacture to first substrate and the second substrate further include using instruction and setting element, The instruction and setting element are for manufacturing at least one of internal layer.
According to another special characteristic, the lamination of inner insulating layer and layer to first substrate and the second substrate is in shape It is realized on plate at copper metallic substrates.
Pass through the technology shape of referred to as IMS type during manufacture first substrate and the second substrate according to another special characteristic At the inner insulating layer and layer of lamination.
According to another special characteristic, during manufacture first substrate and the second substrate, B rank prepreg dielectric part is to pass through Hollow punch mould punching and/or milling and/or knife are cut and are manufactured on the basis of B rank prepreg thin slice, and are arranged and exist In the corresponding position of substrate.
According to another special characteristic, during manufacture first substrate and the second substrate, current-carrying part is to pass through hollow punch Mould punching and/or milling and/or knife cut and on the basis of copper foil made of, and be arranged in the corresponding position of substrate.
According to another special characteristic, during manufacture first substrate and the second substrate, dielectric part and current-carrying part are logical Cross hollow punch mould punching and/or milling and/or knife is cut or is cut by laser and on the basis of copper-clad laminate made of, And it is arranged in the corresponding position of substrate.
According to another special characteristic, during manufacture first substrate and the second substrate, the formation of internal layer includes passing through photoetching Definitely define connecting pattern.
According to another special characteristic, during manufacture first substrate and the second substrate, the formation of internal layer is included in determining position Deposition first order interconnection materials are set, which includes the position for being exclusively used at least one electronic chip, is deposited by weldering Cream distributor carries out.
According to another special characteristic, the pressure assembling to first substrate and the second substrate includes by vacuum lamination furnace Reason.
According to another aspect, the invention further relates to a kind of integrated power electronic equipment of electric power electronic module form, this is set Standby includes the first lamination sub-unit and the second lamination sub-unit and central coolant liquid free air space, the first lamination sub-unit and Second lamination sub-unit is made by executing method as briefly described above, which is arranged in the first sub-unit And second between sub-unit, the first lamination sub-unit and the second lamination sub-unit are stacked and link together, and respectively include Form the first electronic power switch and the second electronic power switch of bridge arm.
According to special characteristic, electronic power switch is the transistor of MOSFET or IGBT type.
Detailed description of the invention
Read the following detailed description to multiple specific embodiments according to the present invention by referring to accompanying drawing, of the invention its He will more clearly show advantages and features, in the accompanying drawings:
Fig. 1 a and Fig. 1 b show two schematic diagrames of the transistor bridge arm with mosfet transistor and igbt transistor；
Fig. 2 to Figure 10 is simplified cross-sectional view, and it illustrates the steps of the method according to the present invention for integrated electronic chip Suddenly；And
Figure 11 to Figure 12 is simplified cross-sectional view, it illustrates for air cooled module and liquid refrigerating module according to this The first embodiment and second embodiment of the power module of invention.
Specific embodiment
Below under the background of manufacture transistors switch bridge arm or the power module of half-bridge form, describe according to the present invention The specific embodiment of method.
Two examples of power module are shown in Fig. 1 a and Fig. 1 b.These modules can be associated complete to be formed Switching bridge, or parallel connection is to transmit desired electric current.
As illustrated in figs. 1A and ib, these power modules are formed by transistors switch bridge arm or half-bridge.In general, bridge arm includes The top transistor and bottom transistor and relevant diode of " downside " and " upside " are known respectively as in English.Figure 1a shows the schematic diagram of the first bridge arm BM, and the first bridge arm BM is by mosfet transistor MTHSAnd MTLSAnd respectively with transistor Associated diode MDHSAnd MDLSComposition.Fig. 1 b shows the schematic diagram of the second bridge arm BI, and the second bridge arm BI is by IGBT crystal Pipe ITHSAnd ITLSAnd its associated diode IDHSAnd IDLSComposition.
In the following description, manufactured power module is considered as bridge arm BM as shown in Figure 1a, that is to say, that packet Include MTHSAnd MTLSTwo mosfet transistors, and diode MD associated with transistor respectivelyHSAnd MDLS.It is configured in part In, diode associated with transistor should be already integrated into the chip of transistor, so that the setting to these diodes It is no longer required.It should be noted that hereinafter, the two are all having the same referring to mark for manufactured power module and bridge arm Remember BM.It should also be noted that the description is also applied for the bridge arm BI of Fig. 1 b by replacing mosfet transistor with igbt transistor.
In general, power electronics manufacturing technology that is well-known and well grasping is used in the present invention, mainly from title For the technology of IMS (referring to " the Insulated Metal Substrate (insulating metal substrate) " in English).Therefore, in basis In method of the invention, the combination including the different manufacturing technologies such as lamination, photoetching, metal electrodeposition, wet etching can be used. The Transient liquid phase welding, metal nano-particle powder sintering or diffusion welding (DW) of referred to as TLP welding can be used in welding for component It connects.Hollow punch mould punching is also used, it is to be attached to be cut into insulating film or heat insulating lamella and copper film or copper foil Element, the element are attached in the fabrication process in the substrate of module.During being attached to the operation of substrate, it will also use and be used for The device and space to be preserved device for indicating and positioning.
Referring to Fig. 2 to Figure 10, will be described in the method according to the present invention for integrated power electronic chip now Related difference manufacturing step.These steps allow to manufacture the stacking internal layer being present in power module according to the present invention, And the general framework of sandwich.
Fig. 2 shows the substrate EB1 of the sub-unit of power module, are in the initial stage.
In the manufacturing step of Fig. 2, space to be preserved element HM1 and HM2 most start the lifting surface for being separately positioned on plate MB1 On SH1 and SH2, plate MB1 forms metallic substrates.Metallic substrates MB1 is preferably copper.
As shown in Figure 2, metallic substrates MB1 is formed in advance to be formed and be lifted surface HM1 and HM2 and position MP.Usually The preparatory sizing of metallic substrates MB1 is realized by mechanical removal material or by photoetching.
On substrate MB1, B rank prepreg dielectric part PPb is deposited at the corresponding position MP of substrate MB1.Here B Rank prepreg dielectric part PPb is usually the braided glass fibre dielectric for being coated with epoxy resin and Partial polymerization.Such as T Other dielectrics of é flon (registered trademark) or polyimides can be used for special applications.Dielectric part PPb can be by B rank Prepreg thin slice carries out hollow punch mould punching or is cut by milling or knife to realize.
In step shown in Fig. 3, space to be preserved element HM1 and HM2 is arranged in instruction and setting element LM1 and LM2 Two sides.Position of these elements LM1, LM2 as limitation against current-carrying part PPb and for limiting copper current-carrying part CP, should Current-carrying part CP partly covers dielectric part PPb.It is not retained in by the part NC that current-carrying part CP is covered shown in Fig. 4 The side-walls of position MP.
Acquisition current-carrying part CP on the basis of copper sheet is cut by hollow punch mould punching or by milling or knife.It is logical It crosses vacuum compacting or is handled by vacuum lamination furnace and realized on metallic substrates MB1 to layer where part PPb and part CP Lamination.In Fig. 3, dielectric part PPb is shown in the form of it aggregates into dielectric layer PP.
In modification, it is noted that can referred to as CCL (generation refer in English " Copper Clad Laminate (covers Copper-clad laminate) ") copper-clad laminate on the basis of obtain Fig. 3 multilayer board EB1.By dielectric layer and copper capping layer shape At laminated portion be cut into and be attached on the MP of position in laminate, if it is desired, position MP can coat tree in advance Rouge.The layer shape structure of laminated portion on metallic substrates MB1 is to be suppressed by vacuum or realized by the processing of vacuum lamination furnace.
In Fig. 4, instruction and setting element LM1 and LM2 are removed and make not shown by the part NC that current-carrying part CP is covered It is existing.
Lithography operations are shown in the step of Fig. 5 and Fig. 6, are used to accurately limit connecting pattern made of copper.At this Adjusting as the width of the current-carrying part CP1 for the side wall side in exemplary attached drawing, showing lifting surface SH2 a bit.
In Fig. 5, photoetching gum resin PS is coated on the upper laminating surface of substrate EB1.Then, by using silk-screen printing Mask is simultaneously exposed to ultraviolet radiation and limits in a usual manner and form the surface portion corroded by wet etching.
In fig. 5, it is shown that substrate EB1 prepares the wet etching for being used for copper.Remove metal part CP1a and therefore accurately Form connecting pattern.
In step 6, photoetching gum resin PS is removed by known method, such as washes or lead to by oxygen plasma, dry acid Cross solvent processing.As shown in fig. 6, connecting pattern includes the current-carrying part CP2 definitely defined after etching part CP1.
In step shown in fig. 7, it is related to forming position L1 and L2, is used to accommodate the chip and two of transistor MT respectively The chip of pole pipe MD.The space that element HM1 and HM2 are reserved is respectively dedicated position L1 and L2.
In Fig. 7 the step of, the dielectric part PPb1 of B rank prepreg is in the surface portion of substrate EB1 with multilayer form Deposition.Cavity and electrically insulative portion needed for the step allows to configure deposition interconnection materials and installation electronic chip.With with The part PPb of Fig. 2 is similarly implemented and node section PPb1 is arranged.
Position L1 includes two cavitys L10 and L11, is used to accommodate interconnection materials.Cavity L10 corresponds to element HM1 The space reserved, and it is used for the drain electrode (D in Fig. 1 a of substrate MB1 and transistor MTHSOr DLS) between electrical contact. Cavity L11 is formed by depositing node section PPb1, and the gate electrode for current-carrying part CP2 and transistor MT is (in Fig. 1 a GHSOr GLS) between electrical contact.
Position L2 includes cavity 20, passes through space to be preserved element HM2 completely and limits and be used for interconnection materials.Cavity L20 is for the electrical contact between substrate MB1 and the negative electrode (Fig. 1 a) of diode MD.
In Fig. 8 the step of, space to be preserved element HM1 and HM2 is removed, and by component after depositing interconnection materials The chip of MT and MD is arranged in position L1 and L2.
In fig. 8, the dielectric part PPb1 of B rank prepreg is shown as polymerizeing completely, and forms dielectric layer PP.However, It should be noted that the manufacturing step can also be carried out when part PPb1 not yet polymerize completely.
As shown in Figure 8, interconnection materials EI1 is deposited in cavity L10, cavity L11 and cavity L20.In general, electricity is mutually Even material EI1 is the soldering paste suitable for the interconnection of FLI type, which refers to " the First Level Interconnect in English (first order interconnection) ".The deposition of first order interconnection materials EI1 is realized by solder paste dispenser.
Fig. 9 shows the assembling of substrate EB1 with the substrate EB2 to match, and substrate EB1 passes through the manufacturing step of Fig. 2 to Fig. 8 It realizes.Substrate EB2 is manufactured according to the manufacturing step similar with the manufacturing step of substrate EB1.It should be noted that, it is preferable that according to Substrate EB1 and EB2 of the invention is manufactured parallel on different production lines, this allows significant reduction manufacturing time.
As shown in figure 9, the upper lamination surface profile of the upper lamination surface profile of substrate EB2 and substrate EB1 match and phase Fitting.
Substrate EB2 includes position L3 and L4, corresponds respectively to the position L1 and L2 of substrate EB1.The table of position L1 and L2 Face is covered with interconnection materials EI2, identical as the material EI1 of substrate EB1, and interconnection materials EI2 is used for transistor MT Source electrode (the S in Fig. 1 a of chip and diode MD chipHSOr SLS) and positive electrode (Fig. 1 a) be electrically connected respectively to plate BM2, should The metallic substrates of plate BM2 formation substrate EB2.
Substrate EB2 includes B rank prepreg dielectric part PPb2, is arranged to the dielectric part PP (PPb1) with substrate EB1 It is corresponding.
As shown in Figure 9, substrate EB1 and EB2 limits the chip of component MT and MD against each other and in its internal layer.Finally Assembling and realization lamination sub-unit are to be suppressed by vacuum or handled by vacuum lamination furnace to realize.In the final assembling phase Between, it is related to the final connection for polymerizeing and passing through interconnection materials of dielectric part.
Figure 10 shows the implementation modification of the assembling steps in Fig. 9.In the implementation modification, in the position with substrate EB2 In the case that L3 and L4 is aligned, first order interconnection materials EI2 deposits to the upper surface of electronic chip MT and MD.Then, pass through It is finally assembled with above for the identical mode of mode described in Fig. 9.
Above with reference to allowing to manufacture according to the method for the present invention described in Fig. 2 to Figure 10 there is sandwich switch to be laminated framework Power sub-unit or complete power electronic equipment.Compared with the known other technologies of such as HDI technology, propose here Method allows while reducing manufacturing time, improves performance, increases compactedness, and the reduction of the manufacturing time is by integrated chip mistake The parallelization of journey simultaneously utilizes caused by the technology for passing through verifying and economy of IMS type.Particularly, in no via hole or miniature mistake The optimization of the internal connectivity for the sub-unit realized in the case where hole allows to reduce parasitic inductance and further integrates.Due to component Two sides there are the copper of a large amount of high thermal conductivities, close to electronic building brick and the tools of electronic building brick two sides is set there are two copper plates The interlayer framework of (MB1, MB2) is greatly promoted the discharge of dissipation heat.
1 and Figure 12 referring to Fig.1, first that the power module of bridge arm form as in fig. la and lb will now be described are special Determine embodiment EM1 and the second specific embodiment EM2.
These power modules EM1 and EM2 passes through two lamination sub-unit BBHSAnd BBLSStacking building, by with above The mode referring to described in Fig. 2 to Figure 10 similarly mode come manufacture these lamination sub-unit BBHSAnd BBLS。
Usually, it is noted that lamination sub-unit according to the present invention is basic unit, can be assembled to constitute relatively Complicated integrated power electronic device.The assembling of the basic unit stacked to two usually goes forward side by side furnace processing and real under stress It is existing.Being mechanically and electrically between two units will be ensured by welding.
Module EM1 shown in Figure 11 is air cooled embodiment.If desired, by assembling multiple power modules The power converter that EM1 is formed can be equipped with heat dissipation device.Heat dissipation device includes one or more radiators, with copper Part MB1, MB2 electrical isolation thermal contact.Framework of the invention allows to efficiently extract the heat that dissipates by conventional radiator Amount, to avoid the device costly using such as phase-change cooling device in a certain number of applications.
The unit B B of Figure 10LSAnd BBHSBetween connection plane IP at be mechanically and electrically can be by referred to as TLP Transition liquid-phase welding, by sintering be attached or realized by other above-mentioned welding techniques.
As shown in figure 11, the top of module is arranged in herein equipped with control circuit CTRL in module EM1, and passes through Dielectric layer DLHSWith unit B BHSCopper part MB1 electrical isolation.Dielectric layer DLLSThe lower part of module is set and ensures unit B BLS The part electrical isolation.Circuit CTRL includes the multiple laminate layers realized according to above-mentioned technology.If desired, active block and nothing Source component can be built between the internal layer of circuit CTRL, or be surface mounted in a usual manner by soldering or conducting resinl On circuit.
Module EM2 shown in Figure 12 is the cooling embodiment of liquid, and it is suitable for powerful applications.
Similar to the module of Figure 11, module EM2 includes unit B BLSAnd BBHS, be arranged in module top control circuit CTRL and dielectric layer DLHSAnd DLHS, in addition to this, module EM2 further includes coolant liquid free air space CC.For under stress Cooling dielectric fluid can be used for example as heat-carrying coolant liquid.The middle section of module EM2 is arranged in space CC, respectively with list First BBLSAnd BBHSCopper plates MB1 and MB2 directly contact.
What the other embodiments of power module according to the present invention were certainly possible to, such as in the upper and lower part of module It further include the module of the coolant liquid cyclic space.Then, by each unit B BHS, BBLSTwo sides circulation coolant liquid come it is cold But unit B BLSAnd BBHS, further to extract heat.
The present invention is not limited to the specific embodiments of here as example description.Application according to the present invention, art technology Personnel can make the various modifications and variations belonged in attached claim scope.

Claims (13)

1. the method that one kind is used for integrated power electronic chip (MT, MD) is used to manufacture lamination sub-unit (BBHS、BBLS), institute Lamination sub-unit is stated for integrated power electronic equipment (EM1, EM2), which is characterized in that the described method includes:
It manufactures the first and second substrates (EB1, EB2), the manufacture includes use space reservation device (HM1, HM2), the base Each of plate (EB1, EB2) by formed metallic substrates (MB1, MB2) plate on lamination insulation and layer (PP, CP, EI) and be made, at least one described electronic chip (MT, MD) is arranged in first and second substrate (EB1, EB2) In any one, and first and second substrate (EB1, EB2) manufacture has matched profile at laminating surface thereon；
By the way that there is the upper surface of first and second substrate of matching profile to stack and engage first and second base Plate (EB1, EB2)；And
Pressure assembling is carried out to first and second substrate (EB1, EB2), to manufacture the lamination sub-unit (BBHS、BBLS)。
2. the method according to claim 1, wherein the space to be preserved device is for generating at least one position (L1, L2), the position are used at least one described chip (MT, MD).
3. method according to claim 1 or 2, which is characterized in that the system of first and second substrate (EB1, EB2) Making further includes using instruction and setting element (LM1, LM2), and the instruction and setting element are for manufacturing in the internal layer extremely It is one few.
4. according to the method in any one of claims 1 to 3, which is characterized in that manufacturing first and second substrate During (EB1, EB2), the lamination of insulation and layer (PP, CP, EI) to first and second substrate (EB1, EB2) is It is realized on the plate for forming copper metallic substrates (MB1, MB2).
5. method according to claim 1 to 4, which is characterized in that manufacturing first and second substrate During (EB1, EB2), insulation and the layer (PP, CP, EI) of the lamination are formed by the technology of referred to as IMS type.
6. the method according to any one of claims 1 to 5, which is characterized in that manufacturing first and second substrate During (EB1, EB2), B rank prepreg dielectric part (PPb) is cut by hollow punch mould punching and/or milling and/or knife And manufactured on the basis of B rank prepreg thin slice, and be arranged in the corresponding position (MP) of the substrate (EB1, EB2).
7. method according to any one of claim 1 to 6, which is characterized in that manufacturing first and second substrate During (EB1, EB2), current-carrying part (CP) is to be cut by hollow punch mould punching and/or milling and/or knife in copper foil On the basis of made of, and be arranged in the corresponding position (MP) of the substrate (EB1, EB2).
8. method according to any one of claim 1 to 7, which is characterized in that manufacturing first and second substrate During (EB1, EB2), dielectric and current-carrying part (PP, CP) be cut by hollow punch mould punching and/or milling and/or knife or Laser cutting and on the basis of copper-clad laminate (CCL) made of, and be arranged in the corresponding of the substrate (EB1, EB2) In position (MP).
9. method according to any one of claim 1 to 8, which is characterized in that manufacturing first and second substrate During (EB1, EB2), the formation of the internal layer includes definitely defining connecting pattern (CP, CP1, CP2) by photoetching.
10. method according to any one of claim 1 to 9, which is characterized in that manufacturing first and second substrate During (EB1, EB2), the formation of the internal layer is included in determining position (L10, L11, L20, L3, L4) deposition first order and is electrically interconnected Material (EI1, EI2, FLI), the determining position include the position for being exclusively used at least one electronic chip (MT, MD), institute Deposition is stated to carry out by solder paste dispenser.
11. method according to any one of claim 1 to 10, which is characterized in that first and second substrate The pressure assembling of (EB1, EB2) includes being handled by vacuum lamination furnace.
12. a kind of integrated power electronic equipment of electric power electronic module form, which is characterized in that including the first and second laminations point Assembly (BBHS、BBLS) and central coolant liquid free air space (EM2, CC), described first and second, which are laminated sub-unit, passes through execution Method according to any one of claim 1 to 11 is made, and the center coolant liquid free air space is arranged described first With the second sub-unit (BBHS、BBLS) between, the first and second laminations sub-unit (BBHS、BBLS) be stacked and link together, And respectively include being formed the first and second electronic power switch (MT of bridge arm (BM, BI)HS、MTLS；ITHS、ITLS)。
13. equipment according to claim 12, which is characterized in that the electronic power switch is MOSFET or IGBT type Transistor.
CN201780086323.9A 2016-12-12 2017-12-05 Method for parallelizable integrated power chip and power electronics module Active CN110291633B (en)

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PCT/FR2017/053392 WO2018109315A1 (en) 2016-12-12 2017-12-05 Parallelisable method for integrating power chips and power electronics modules

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FR3094567B1 (en) * 2019-03-28 2021-05-21 Inst Vedecom LOW COST MANUFACTURING PROCESS OF A MODULAR POWER SWITCHING ELEMENT

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US20200185365A1 (en) 2020-06-11
WO2018109315A1 (en) 2018-06-21
FR3060255A1 (en) 2018-06-15
EP3552235A1 (en) 2019-10-16
JP2020501381A (en) 2020-01-16

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