CN110277732A - VCSEL device and preparation method thereof with high dielectric constant limiting holes - Google Patents
VCSEL device and preparation method thereof with high dielectric constant limiting holes Download PDFInfo
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- CN110277732A CN110277732A CN201910640780.9A CN201910640780A CN110277732A CN 110277732 A CN110277732 A CN 110277732A CN 201910640780 A CN201910640780 A CN 201910640780A CN 110277732 A CN110277732 A CN 110277732A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/10—Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region
- H01S5/18—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities
- H01S5/183—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
- H01S5/18308—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL] having a special structure for lateral current or light confinement
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/10—Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region
- H01S5/18—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities
- H01S5/185—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only horizontal cavities, e.g. horizontal cavity surface-emitting lasers [HCSEL]
- H01S5/187—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only horizontal cavities, e.g. horizontal cavity surface-emitting lasers [HCSEL] using Bragg reflection
Abstract
The present invention is a kind of VCSEL device and preparation method thereof with high dielectric constant current-confining apertures.The epitaxial structure of the device successively includes substrate, buffer layer, nitride epitaxial DBR and N-type semiconductor transport layer along epitaxial growth direction；Wherein, N-type semiconductor transport layer is divided into two parts, and nitride epitaxial DBR is completely covered in lower layer；The upper layer of the N-type semiconductor transport layer is followed successively by multiple quantum well layer, P-type current barrier layer, P-type semiconductor transport layer；P-type heavily-doped semiconductor transport layer；The outside of P-type heavily-doped semiconductor transport layer upper surface is the high-k insulating layer of annular, and material is undoped HfO2Or Ta2O5.The production of the device with high dielectric constant current-confining apertures in the present invention compared to the device of tunnel junctions, it can reduce for nearly 40% process time, the big appointment of lasing threshold reduces 0.5mA, and the output power at 80mA, improves 14.3% compared to conventional device.
Description
Technical field
The present invention relates to vertical-cavity surface-emitting devices fields in semiconductor laser, specifically a kind of to have high dielectric
The preparation method of the VCSEL device of constant limiting holes.
Background technique
The concept of vertical cavity surface emitting laser (VCSELs) is set forth in by Kenichi Iga professor and his colleague for the first time
1977, and First equipment was realized in 1979.From then on, a quickly hair is presented in the Related Research Domain of VCSELs
The trend of exhibition, and be commercialized quickly in realization in 1994.Nowadays VCSEL has replaced edge-emitting laser and has applied the optical fiber in short distance
In communication, such as Etherloop and fiber channel (Fibre Channel).2004, VCSELs was used for optical computer for the first time
Mouse.On September 13rd, 2017, iPhone X publication, face recognition function use VCSEL technology, and apple is even more to pound 25.8 later
Hundred million yuan, power-assisted Finisar increases production VCSEL.
It is that can not obtain gain outside hole, so device setting current-confining apertures will since the light emitting region VCSEL is located in hole
Injection Current is effectively limited within aperture.But electric current p-type hole injection layer below aperture inevitably has extending transversely, leads
Active area has been caused to realize that lasing needs bigger threshold current density, it is extending transversely tight simultaneously under identical current density
Its maximum output of the device of weight is relatively small.Design for the limiting holes of VCSEL currently mainly has once following several sides
Method, first is that buried layer tunnel junctions are placed in hole injection layer, the width of tunnel junctions and consistent, the intermediate carrier of the size in aperture
Active area can be entered with tunnelling, edge forms approximate current limiting holes since high Schottky barrier cannot be introduced into active area
Structure, to realize very strong transverse current limitation (M.Ortsiefer, R.Shau, G.F.
G.Abstreiter,M.-C.Amann,Low-resistance InGa(Al)As tunnel junctions for long
wavelengthvertical-cavity surface-emitting lasers.Jpn.J.Appl.Phy.39,1727–1729
(2000).).Furthermore such as Chinese invention patent CN108923255A uses Al2O3As current limit pore structure, due to
The higher thermal conductivity of Al2O3, can be improved the thermal diffusivity of device, thus the performance of stabilizing device and service life.Above-mentioned buried layer tunnel
Although wear junction structure improves laterally limiting for electric current to a certain extent, device performance is made to have obtained certain promotion,
Their device architecture is complex, and the requirement for growth technique is excessively high, and general commercial production levels are relatively inaccessible to two
The standard that kind device is proposed.And utilize Al2O3When for current-confining apertures, although improving the heat dissipation of device, it is only sharp
, electric current insulator below hardly possible very little to the effect of electric current laterally limited is realized with the non-conductive property of insulator itself
Exempting from can horizontal proliferation.As shown in Figure 1, common practice may want that insulator is done to thickness to be gone to realize current limit, but insulator
The too thick heat dissipation and its performance that will affect device, so we need to start with from further aspect to solve transverse current diffusion
Problem.
The problem of spreading about electric current toward two sides, current solution are that the insulation limitation aperture layer of device architecture is to use
SiO2 and SiN, it is therefore an objective to the feature of its insulator is utilized, come realize by current convergence in the devices between prevent toward two sides spread
The problem of；But due to insulation thickness is limited and the mobility of electric current, however it remains electric current to two sides horizontal proliferation
The problem of, i.e., can not well by current convergence in the devices between.
Summary of the invention
It is an object of the present invention to provide a kind of with high dielectric constant current limit for deficiency present in current techniques
The VCSEL device in hole.The device is by the device limitation Porous materials of current main-stream VCSEL by SiO2Having changed into has high dielectric constant
Material Ta2O5, HfO2, by with the material Ta with high dielectric constant2O5, HfO2To replace SiO2, utilize electron electric power device
MIS in part is theoretical, is equivalent to below the insulator structure of itself and one layer of stealthy insulator (high resistance area) has been added to hinder again
The horizontal proliferation for keeping off electric current, while both having accomplished good conductive force, also corresponds to be covered the side of device,
Electric current will not then be flowed to two sides, realize good current limit.
The present invention solves technical solution used by the technical problem:
A kind of VCSEL device with high dielectric constant current-confining apertures；The epitaxial structure of the device is along epitaxial growth
Direction successively includes substrate, buffer layer, nitride epitaxial DBR and N-type semiconductor transport layer.
Wherein, N-type semiconductor transport layer is divided into two parts, and nitride epitaxial DBR is completely covered in lower layer, with a thickness of 1~5 μ
m；The projected area on upper layer is the 60~80% of lower layer's area, and identical with the center of lower layer, with a thickness of 0.1~2 μm.
The upper layer of the N-type semiconductor transport layer is followed successively by multiple quantum well layer, P-type current barrier layer, P-type and partly leads
Body transport layer, P-type heavily-doped semiconductor transport layer；The outside of P-type heavily-doped semiconductor transport layer upper surface is the height of annular
Dielectric constant, as current-confining apertures, material is undoped HfO2 or Ta2O5, with a thickness of 10~100nm, circle
The width of ring is 1~10 μm.
Current extending is covered on P-type heavily-doped semiconductor transport layer and high dielectric constant insulation current limiting holes；
Medium DBR is located on current extending, and projected area is the 0.5~0.9 of current extending area；The P-type Europe of circular ring shape
Nurse electrode is located at the outside of current extending, and width is 0.1~2 μm.
Circular N-type Ohmic electrode is located at the outside of N-type semiconductor transport layer lower layer expose portion, width 0.1
~1 μm.
The substrate is sapphire, SiC, Si, AlN, GaN or quartz glass.Substrate along epitaxial growth direction difference
It is segmented into polar surface [0001] substrate, semi-polarity face [11-22] substrate or non-polar plane [1-100] substrate.
The material of the buffer layer is Alx1Iny1Ga1-x1-y1N.Wherein, each component coefficient 0≤x1≤1,0≤y1 be should ensure that
≤ 1,1 >=1-x1-y1 >=0, with a thickness of 10~50nm.
The material of the nitride epitaxial DBR can by the high low-index material such as AlN/GaN, AlInN/GaN alternately and
At, thickness is respectively a quarter of the required wavelength of emission wavelength in the medium.
The material of the N-type semiconductor transport layer is Alx2Iny2Ga1-x2-y2N, wherein should ensure that each component coefficient 0≤
X2≤1,0≤y2≤1,1 >=1-x2-y2 >=0, with a thickness of 1~5 μm.
The multiple quantum well layer material is Alx3Iny3Ga1-x3-y3N/Alx4Iny4Ga1-x4-y4N, wherein should ensure that each component
Coefficient 0≤x3≤1,0≤y3≤1,1 >=1-x3-y3 >=0,0≤x4≤1,0≤y4≤1,1 >=1-x4-y4 >=0, what quantum was built
Forbidden bandwidth should be higher than that the forbidden bandwidth of Quantum Well, the number of Quantum Well are more than or equal to 1, Quantum Well Alx3Iny3Ga1-x3-y3N thickness
For 1~10nm, quantum builds Alx4Iny4Ga1-x4-y4N is with a thickness of 5~50nm.
The material of the P-type current barrier layer is Alx5Iny5Ga1-x5-y5N, wherein should ensure that 0≤x5 of each component coefficient≤
1,0≤y5≤1,1 >=1-x5-y5 >=0, with a thickness of 10~100nm.
The material of the P-type semiconductor transport layer is Alx6Iny6Ga1-x6-y6N, wherein should ensure that 0≤x6 of each component coefficient
≤ 1,0≤y6≤1,1 >=1-x6-y6 >=0, with a thickness of 50~250nm.
The material of the P-type heavily-doped semiconductor transport layer is Alx7Iny7Ga1-x7-y7N, wherein should ensure that each component system
Number 0≤x7≤1,0≤y7≤1,1 >=1-x7-y7 >=0, material doped is p-type heavy doping, doping concentration 1e25m3~
1e26m3, with a thickness of 10~50nm.
The material of the current extending can be ITO, Ni/Au, zinc oxide, graphene, aluminium or metal nanometer line, thickness
For 10~100nm.
The material of the medium DBR can be by Ta2O5/SiO2、TiO2/SiO2,Made of contour low-index material alternating,
Its thickness is respectively a quarter of the required wavelength of emission wavelength in the medium.
The material of the p-type Ohmic electrode is P-type Ohmic electrode Ni/Au, Cr/Au, Pt/Au, Ni/Al etc., P-type ohm
The projected area of electrode is the 5%~100% of current extending area.
The material of the N-type Ohmic electrode is N-type Ohmic electrode Al/Au, Cr/Au etc., wherein the throwing of N-type Ohmic electrode
Shadow area is the 5%~100% of the N-type semiconductor transport layer area of exposure.
The above-mentioned VCSEL device with high dielectric constant current-confining apertures, related raw material can pass through generality
Approach obtains, and the operating procedure in preparation method is that those skilled in the art are had.
The preparation method of the VCSEL device with high dielectric constant current-confining apertures, comprising the following steps:
The first step toasts substrate, by substrate surface first in MOCVD reacting furnace at 1250~1350 DEG C
Foreign matter be purged, then respectively grow GaN buffer layer, nitride epitaxial DBR, N-type GaN semiconductor transport layer, Quantum Well
Layer, P-type current barrier layer, P-type GaN semiconductor transport layer, P-type GaN heavily-doped semiconductor transport layer；
Second step is made in the P-type heavily-doped semiconductor transport layer that the first step obtains by lithography and etching technique
Step exposes 60~80%N- type semiconductor transport layer；
Third step, the deposition growing current-confining apertures structure sheaf in the P-type heavily-doped semiconductor transport layer that the first step obtains
With a thickness of 10~100nm, insulating material used in current limit pore structure is undoped HfO2；Followed by photoetching skill
Art etches circular pattern to insulating material, which covers annulus along the edge of P-type heavily-doped semiconductor transport layer
Width be 1~10 μm；
Current extending is deposited in 4th step on the current-confining apertures that third step obtains, and material is ITO, and passes through light
It carves and wet etching makes graphical current extending, positioned at the upper of P-type heavily-doped semiconductor transport layer and current-confining apertures
Side；
5th step, atomic layer deposition (ALD) the medium DBR on the current extending that the 4th step obtains；
6th step, vapor deposition and optical graving make P-type Ohmic electrode width and are and N-type Ohmic electrode width respectively；
Thus the VCSEL device with high dielectric constant current-confining apertures of the invention is made.
Substantive distinguishing features of the invention are as follows:
Realization of the invention is based on VCSEL laser Basic Design thinking, then MIS theory in power electronic component is set
The device for counting VCSEL, achieves unexpected effect.
Its theoretical mechanism are as follows: current techniques mainly use SiO2 (dielectric constant 3.9) or SiN, and (dielectric constant is
7.5) material as current-confining apertures, and it is proposed that be to use HfO2 (dielectric constant 25), Ta2O5 (dielectric constant
It is 26) two kinds of materials as limiting holes.
As shown in figures 1 and 2: if insulator dielectric constant is very big using HfO2 and Ta2O5, the electric field undertaken is got over instead
It is small, so the voltage undertaken is smaller.So, the voltage for being added in the two sides p-GaN is bigger.According in power electronic component theory
Known to MIS structure principle: the voltage of the two sides p-GaN is bigger, and hole (being similar to electronics) concentration inside p-GaN is smaller, because
It is depleted.In brief, carrier concentration is smaller, and electric conductivity is poorer, that is, is similar to a high resistance area.So electric current would not be horizontal
To flowing, only meeting straight line is injected downwardly into, that is, reaches the result that we want.
The beneficial effects of the present invention are:
(1) the VCSEL device for having high dielectric constant current-confining apertures in the present invention, has been embedded into VCSEL for insulator
Current extending in, this structure take full advantage of insulator in MIS structure share electric field ability and insulating material sheet
The related feature of the dielectric constant of body integrates the current-confining apertures of itself and VCSEL cleverly, so that below insulator
The degree that exhausts become strong, to reduce the horizontal proliferation of electric current, entire device is made to obtain better transverse current limitation,
To reduce the threshold current of VCSEL, the luminous efficiency of device is improved.There is high dielectric constant electric current in the present invention
The device of limiting holes can reduce for nearly 40% process time compared to the production of the device of tunnel junctions, the big appointment drop of lasing threshold
Low 0.5mA, and the output power at 80mA improves 14.3% compared to conventional device.
(2) in addition, the device design structure alleviates the transverse direction of p-type hole injection layer in VCSEL device to a certain extent
Potential difference weakens lateral carrier injection compared to low dielectric constant insulation limiting holes to a certain extent, equally also improves
The laterally limiting of electric current.
(3) there is the VCSEL device of high dielectric constant current-confining apertures in the present invention, manufacture craft is simple, and it is easily operated, it can
Repeated strong, production cost is low.
Detailed description of the invention
Explanation further is made to the present invention with reference to the accompanying drawing.
Fig. 1 is the material that current techniques mainly use SiO2 (dielectric constant 3.9) or SiN (dielectric constant 7.5)
Current-confining apertures schematic diagram；
Fig. 2 is that the present invention uses two kinds of material conducts of HfO2 (dielectric constant 25) or Ta2O5 (dielectric constant 26)
The schematic diagram of limiting holes.
Fig. 3 is that the epitaxial slice structure of the VCSEL device in method of the invention, with high dielectric constant current-confining apertures shows
It is intended to.
Fig. 4 is in P-type heavily-doped semiconductor transport layer, to be made by lithography and etching technique in method of the invention
Step exposes the epitaxial slice structure schematic diagram of N-type semiconductor transport layer.
Fig. 5 is in P-type heavily-doped semiconductor transport layer, to be insulated by one layer of deposition growing in method of the invention
Layer, and make the epitaxial slice structure schematic diagram of current-confining apertures by lithography.
Fig. 6 is to be shown in method of the invention by the epitaxial slice structure that lithography and etching makes graphical current extending
It is intended to.
Fig. 7 is the P-I curve and standard of the VCSEL device in method of the invention with high dielectric constant current-confining apertures
SiO2The comparison diagram of current-confining apertures P-I curve.
Fig. 8 is the VCSEL device isolation body lower section p-type in method of the invention with high dielectric constant current-confining apertures
The hole GaN cross direction profiles and standard SiO2The comparison diagram of the hole p-type GaN cross direction profiles below current-confining apertures insulator.
Wherein, 101. substrate, 102, buffer layer, 103. nitride epitaxial DBR, 104.N- type semiconductor transport layers, 105.
Multiple quantum well layer, 106.P- type current barrier layer, 107.P- type semiconductor transport layer, the transmission of 108.P- type heavily-doped semiconductor
Layer, 109. current-confining apertures, 110. current extendings, 111. medium DBR, 112.P- type Ohmic electrodes, 113.N- type ohm electricity
Pole.
Specific embodiment
Below with reference to examples and drawings, the invention will be further described, but not in this, as to the claim of this application
The restriction of protection scope.
Fig. 3 be embodiment 1 device architecture, along epitaxial growth direction successively include: substrate 101, buffer layer 102,
Nitride epitaxial DBR 103, N-type semiconductor transport layer 104, multiple quantum well layer 105, P-type current barrier layer 106, P-type half
Conductor propagation layer 107, P-type heavily-doped semiconductor transport layer 108, current-confining apertures 109, current extending 110, medium
DBR111, P-type Ohmic electrode 112 and N-type Ohmic electrode 113.
Embodiment illustrated in fig. 4 shows in method of the invention, in P-type heavily-doped semiconductor transport layer 108, passes through light
It carves and dry etch process makes step, the epitaxial slice structure of N-type semiconductor transport layer 104 is exposed, along epitaxial growth
Direction successively includes: substrate 101, buffer layer 102, nitride epitaxial DBR103, N-type semiconductor transport layer 104, multiple quantum wells
Layer 105, P-type current barrier layer 106, P-type semiconductor transport layer 107, P-type heavily-doped semiconductor transport layer 108.
Embodiment illustrated in fig. 5 shows in method of the invention, and life is deposited in P-type heavily-doped semiconductor transport layer 108
Grow tall dielectric constant insulation current-confining apertures 109, and makes the epitaxial slice structure of current-confining apertures by lithography, along epitaxial growth side
To successively including: substrate 101, buffer layer 102, nitride epitaxial DBR103, N-type semiconductor transport layer 104, multiple quantum well layer
105, P-type current barrier layer 106, P-type semiconductor transport layer 107, P-type heavily-doped semiconductor transport layer 108 and insulation current
Limiting holes 109.
Embodiment illustrated in fig. 6 shows in method of the invention, makes graphical current expansion by photoetching and wet etching
Layer epitaxial slice structure, along epitaxial growth direction successively include: substrate 101, buffer layer 102, nitride epitaxial DBR103,
N-type semiconductor transport layer 104, multiple quantum well layer 105, P-type current barrier layer 106, P-type semiconductor transport layer 107, P-type
Heavily-doped semiconductor transport layer 108, insulation current limiting holes 109 and current extending 110.
Curve shown in Fig. 7 show high Jie's dielectric constant insulators limiting holes have under lower threshold value and same current have it is higher
Output power, this is because reducing the horizontal proliferation of electric current after high dielectric constant insulator material is as limiting holes.
Curve shown in Fig. 8 shows that the electric field shared due to high Jie's dielectric constant insulators is small, so having more when applied voltage
Big voltage is added on p-type GaN, so that the hole at interface largely exhausts, therefore the hole concentration at the position almost falls to 0,
High resistance area is formed, plays the role of inhibition to the horizontal proliferation of electrode edge, to improve the performance of device.
Embodiment 1
The epitaxial structure of the VCSEL device with high dielectric constant current-confining apertures of the present embodiment, along epitaxial growth
Direction successively includes circular substrate 101, buffer layer 102, nitride epitaxial DBR103 and N-type semiconductor transport layer 104；Wherein,
N-type semiconductor transport layer 104 divides for two parts, and nitride epitaxial DBR103 is completely covered in lower layer, with a thickness of 2 μm；The throwing on upper layer
Shadow area is the 80% of lower layer's area, and identical with the center of lower layer, with a thickness of 0.5 μm；The N-type semiconductor transport layer
104 upper layer is followed successively by multiple quantum well layer 105, P-type current barrier layer 106, P-type semiconductor transport layer 107；P-type heavy doping
Semiconductor transport layer 108；The outside of 108 upper surface of P-type heavily-doped semiconductor transport layer is the high-k insulating layer of annular
It is undoped HfO as its material of current-confining apertures 1092109, with a thickness of 40nm, the width of annulus is 2.5 μm；Electric current expands
Exhibition layer 110 is covered on P-type heavily-doped semiconductor transport layer 108 and high dielectric constant insulation current limiting holes 109；Medium
DBR111 is located on current extending 110, and projected area is the 0.6 of 110 area of current extending；The P-type Europe of circular ring shape
Nurse electrode 112 is located at the outside of current extending 110, and width is 0.5 μm；Circular N-type Ohmic electrode 113 is located at N-type
The outside of 104 lower layer's expose portion of semiconductor transport layer, width are 0.5 μm.
The above-mentioned VCSEL device with high dielectric constant current-confining apertures, preparation method are as follows:
The first step toasts substrate 101, by substrate 101 in MOCVD reacting furnace under 1300 DEG C of hot environments
The foreign matter on surface is purged, and then grows GaN buffer layer 102 respectively；Extension AlN/GaN DBR103；N-type GaN semiconductor
Transport layer 104；10 couples of In0.07Ga0.93N/GaN multiple quantum well layer 105；P-type Al0.09Ga0.91N current barrier layer 106；P-type
GaN semiconductor transport layer 107；108 doping concentration of P-type GaN heavily-doped semiconductor transport layer is 5e25m3；
Second step passes through lithography and etching technique system in the P-type heavily-doped semiconductor transport layer 108 that the first step obtains
Make step, exposes N-type semiconductor transport layer 104；
Third step, the deposition growing current-confining apertures knot in the P-type heavily-doped semiconductor transport layer 108 that the first step obtains
Structure layer 109, insulating material used in current limit pore structure are undoped HfO2, with a thickness of 40nm.Followed by light
Lithography etches circular pattern to insulating material, the pattern along the edge of P-type heavily-doped semiconductor transport layer 108 and
Covering, width are 2.5 μm；
Current extending 110 is deposited in 4th step on the current-confining apertures that third step obtains, and material is ITO, with a thickness of
40nm.And graphical current extending is made by photoetching and wet etching, it is located at 108 He of P-type heavily-doped semiconductor transport layer
The top of current-confining apertures 109；
5th step, 10 couples of Ta of atomic layer deposition (ALD) on the current extending that the 4th step obtains2O5/SiO2Medium
DBR111, with a thickness of 1.27 μm；
6th step, is deposited and optical graving makes P-type Ohmic electrode 112 and N-type Ohmic electrode 113.
Thus the VCSEL device with high dielectric constant current-confining apertures of the invention is made.
Embodiment 2
The epitaxial structure of the VCSEL device with high dielectric constant current-confining apertures of the present embodiment, along epitaxial growth
Direction successively includes circular substrate 101, buffer layer 102, nitride epitaxial DBR103 and N-type semiconductor transport layer 104；Wherein,
N-type semiconductor transport layer 104 divides for two parts, and nitride epitaxial DBR103 is completely covered in lower layer, with a thickness of 2 μm；The throwing on upper layer
Shadow area is the 80% of lower layer's area, and identical with the center of lower layer, with a thickness of 0.5 μm；The N-type semiconductor transport layer
104 upper layer is followed successively by multiple quantum well layer 105, P-type current barrier layer 106, P-type semiconductor transport layer 107；P-type heavy doping
Semiconductor transport layer 108；The outside of 108 upper surface of P-type heavily-doped semiconductor transport layer is the high-k insulating layer of annular
109 as its material of current-confining apertures be undoped Ta2O5, with a thickness of 40nm, the width of annulus is 2.5 μm；Current extending
110 are covered on P-type heavily-doped semiconductor transport layer 108 and high dielectric constant insulation current limiting holes 109；Medium
DBR111 is located on current extending 110, and projected area is the 0.6 of current extending area；P-type ohm of circular ring shape
Electrode 112 is located at the outside of current extending 110, and width is 0.5 μm；Circular N-type Ohmic electrode 113 is located at N-type half
The outside of 104 lower layer's expose portion of conductor propagation layer, width are 0.5 μm.
The above-mentioned VCSEL device with high dielectric constant current-confining apertures, preparation method are as follows:
The first step toasts substrate 101, by substrate 101 in MOCVD reacting furnace under 1300 DEG C of hot environments
The foreign matter on surface is purged, and then grows GaN buffer layer 102 respectively；Extension AlN/GaN DBR103；N-type GaN semiconductor
Transport layer 104；10 couples of In0.07Ga0.93N/GaN multiple quantum well layer 105；P-type Al0.09Ga0.91N current barrier layer 106；P-type
GaN semiconductor transport layer 107；108 doping concentration of P-type GaN heavily-doped semiconductor transport layer is 5e25m3；
Second step passes through lithography and etching technique system in the P-type heavily-doped semiconductor transport layer 108 that the first step obtains
Make step, exposes N-type semiconductor transport layer 104；
Third step, the deposition growing current-confining apertures knot in the P-type heavily-doped semiconductor transport layer 108 that the first step obtains
Structure layer 109, insulating material used in current limit pore structure are undoped Ta2O5, with a thickness of 40nm.Followed by light
Lithography etches circular pattern to insulating material, the pattern along the edge of P-type heavily-doped semiconductor transport layer 108 and
Covering, width are 2.5 μm；
Current extending 110 is deposited in 4th step on the current-confining apertures that third step obtains, and material is ITO, with a thickness of
40nm.And graphical current extending is made by photoetching and wet etching, it is located at 108 He of P-type heavily-doped semiconductor transport layer
The top of current-confining apertures 109；
5th step, 10 couples of Ta of atomic layer deposition (ALD) on the current extending that the 4th step obtains2O5/SiO2Medium
DBR111, with a thickness of 1.27 μm；
6th step, is deposited and optical graving makes P-type Ohmic electrode 112 and N-type Ohmic electrode 113.
Thus the VCSEL device with high dielectric constant current-confining apertures of the invention is made.
The above-mentioned VCSEL device with high dielectric constant current-confining apertures, related raw material can pass through generality
Approach obtains, and the operating procedure in preparation method is that those skilled in the art are had.
In conjunction with each embodiment acquired results, it has been found that, should as the dielectric constant of insulator current-confining apertures becomes larger
The electric field that structure is shared becomes smaller, and the electric field of p-type GaN layer becomes larger and degree of exhaustion is caused to become larger, then inhibits p-type down to a certain degree
GaN's is extending transversely.The variation needs of specific width and thickness do appropriate excellent according to different device architectures, process
Change, so that current-confining apertures be made to play optimum efficiency.
From the embodiments above as can be seen that a kind of VCSEL with high dielectric constant current-confining apertures provided by the invention
Device, by being inserted into the insulation layer structure of high dielectric constant among current extending, high dielectric constant insulator itself is no
Aperture structure needed for electric conductivity forms device to the limitation of electric current, secondly by the metal electrode on the upside of insulator, insulation
Body itself, the p-type GaN layer on the downside of insulator forms MIS structure, when applying positive voltage in metal electrode side, under insulator
Side hole is depleted, and is formed depletion region, i.e. high resistance area, can be prevented the horizontal proliferation of electric current to a certain extent, identical additional
Under voltage, the bigger material of dielectric constant, the potential itself shared is smaller, then what the p-type GaN below insulator was shared
Potential is bigger, exhausts and is more obvious, secondly because the potential that high dielectric constant insulator is shared is small, so that the transverse potential of p-type GaN
Difference is also smaller, it is meant that the carrier horizontal proliferation as caused by transverse direction is poor is also smaller, this also improves the cross of carrier relatively
To limitation, to reduce the threshold current of VCSEL, the luminous efficiency of device is improved.
Mechanism of the invention are as follows: current techniques mainly use SiO2(dielectric constant is by (dielectric constant 3.9) or SiN
7.5) material as current-confining apertures, and it is proposed that be using HfO2(dielectric constant 25), Ta2O5Dielectric constant is
26) two kinds of materials are as limiting holes.It is as shown in Figure 7: if using HfO2And Ta2O5, insulator dielectric constant is very big, is undertaken
Voltage it is smaller instead.So, the voltage for being added in the two sides p-GaN is bigger.It can according to MIS structure principle in Semiconductor Physics
Know: the voltage of the two sides p-GaN is bigger, and semiconductor side p-GaN is depleted, i.e. hole concentration inside p-GaN become smaller close to
0.In brief, hole concentration is smaller, and electric conductivity is poorer, that is, is similar to a high resistance area.So electric current would not lateral flow,
The electric current of injection is only understood straight line and is injected downwardly into, that is, greatly reduces the waste of Injection Current.
Unaccomplished matter of the present invention is well-known technique.
Claims (6)
1. a kind of VCSEL device with high dielectric constant current-confining apertures, it is characterized in that the epitaxial structure of the device is along outer
Prolonging the direction of growth successively includes substrate, buffer layer, nitride epitaxial DBR and N-type semiconductor transport layer；
Wherein, N-type semiconductor transport layer is divided into two parts, and nitride epitaxial DBR is completely covered in lower layer, with a thickness of 1~5 μm；On
The projected area of layer is the 60~80% of lower layer's area, and identical with the center of lower layer, with a thickness of 0.1~2 μm；
The upper layer of the N-type semiconductor transport layer is followed successively by multiple quantum well layer, P-type current barrier layer, P-type semiconductor and passes
Defeated layer, P-type heavily-doped semiconductor transport layer；The outside of P-type heavily-doped semiconductor transport layer upper surface is the high dielectric of annular
Constant insulator layer, as current-confining apertures, material is undoped HfO2Or Ta2O5, with a thickness of 10~100nm, the width of annulus
Degree is 1~10 μm；
Current extending is covered on P-type heavily-doped semiconductor transport layer and high dielectric constant insulation current limiting holes；Medium
DBR is located on current extending, and projected area is the 0.5~0.9 of current extending area；P-type ohm electricity of circular ring shape
Pole is located at the outside of current extending, and width is 0.1~2 μm；
The circular N-type Ohmic electrode is located at the outside of N-type semiconductor transport layer lower layer expose portion, and width is
0.1~1 μm.
2. as described in claim 1 with the VCSEL device of high dielectric constant current-confining apertures, it is characterized in that the substrate is
Sapphire, SiC, Si, AlN, GaN or quartz glass；Substrate is segmented into polar surface along the difference in epitaxial growth direction
[0001] substrate, semi-polarity face [11-22] substrate or non-polar plane [1-100] substrate；
The material of the buffer layer is Alx1Iny1Ga1-x1-y1N.Wherein, each component coefficient 0≤x1≤1,0≤y1≤1,1 be should ensure that
>=1-x1-y1 >=0, with a thickness of 10~50nm；
Made of the material of the nitride epitaxial DBR can be replaced as the high low-index material such as AlN/GaN, AlInN/GaN,
Its thickness is respectively a quarter of the required wavelength of emission wavelength in the medium；
The material of the N-type semiconductor transport layer is Alx2Iny2Ga1-x2-y2N, wherein it should ensure that each component coefficient 0≤x2≤1,
0≤y2≤1,1 >=1-x2-y2 >=0, with a thickness of 1~5 μm.
3. as described in claim 1 with the VCSEL device of high dielectric constant current-confining apertures, it is characterized in that the Multiple-quantum
Well layer material is Alx3Iny3Ga1-x3-y3N/Alx4Iny4Ga1-x4-y4N, wherein should ensure that each component coefficient 0≤x3≤1,0≤y3
≤ 1,1 >=1-x3-y3 >=0,0≤x4≤1,0≤y4≤1,1 >=1-x4-y4 >=0, the forbidden bandwidth that quantum is built should be higher than that quantum
The forbidden bandwidth of trap, the number of Quantum Well are more than or equal to 1, are less than or equal to 10；Quantum Well Alx3Iny3Ga1-x3-y3N with a thickness of 1~
10nm, quantum build Alx4Iny4Ga1-x4-y4N is with a thickness of 5~50nm；
The material of the P-type current barrier layer is Alx5Iny5Ga1-x5-y5N, wherein it should ensure that each component coefficient 0≤x5≤1,0
≤ y5≤1,1 >=1-x5-y5 >=0, with a thickness of 10~100nm；
The material of the P-type semiconductor transport layer is Alx6Iny6Ga1-x6-y6N, wherein it should ensure that each component coefficient 0≤x6≤1,
0≤y6≤1,1 >=1-x6-y6 >=0, with a thickness of 50~250nm.
4. as described in claim 1 with the VCSEL device of high dielectric constant current-confining apertures, it is characterized in that the P-type weight
The material of doped semiconductor transport layer is Alx7Iny7Ga1-x7-y7N, wherein should ensure that each component coefficient 0≤x7≤1,0≤y7≤
1,1 >=1-x7-y7 >=0, material doped is p-type heavy doping, and the material of the P-type heavily-doped semiconductor transport layer is
Alx7Iny7Ga1-x7-y7N, wherein should ensure that each component coefficient 0≤x7≤1,0≤y7≤1,1 >=1-x7-y7 >=0 is material doped
For p-type heavy doping, doping concentration 1e25m3~1e26m3, with a thickness of 10~50nm；
The material of the current extending can be ITO, Ni/Au, zinc oxide, graphene, aluminium or metal nanometer line, with a thickness of 10
~500nm；
The material of the medium DBR can be by Ta2O5/SiO2、TiO2/SiO2,It is thick made of contour low-index material alternating
Degree is respectively a quarter of the required wavelength of emission wavelength in the medium.
5. as described in claim 1 with the VCSEL device of high dielectric constant current-confining apertures, it is characterized in that the p-type Europe
The material of nurse electrode is P-type Ohmic electrode Ni/Au, Cr/Au, Pt/Au or Ni/Al, and the projected area of P-type Ohmic electrode is electricity
Flow the 5%~100% of extension layer area；
The material of the N-type Ohmic electrode is N-type Ohmic electrode Al/Au or Cr/Au, wherein the perspective plane of N-type Ohmic electrode
Product is the 5%~100% of exposed N-type semiconductor transport layer area.
6. the preparation method of the VCSEL device with high dielectric constant current-confining apertures as described in claim 1, it is characterized in that
The following steps are included:
The first step toasts substrate, by the different of substrate surface first in MOCVD reacting furnace at 1250~1350 DEG C
Object is purged, then respectively grow GaN buffer layer, nitride epitaxial DBR, N-type GaN semiconductor transport layer, quantum well layer,
P-type current barrier layer, P-type GaN semiconductor transport layer, P-type GaN heavily-doped semiconductor transport layer；
Second step makes step by lithography and etching technique in the P-type heavily-doped semiconductor transport layer that the first step obtains,
Expose 60~80%N- type semiconductor transport layer；
Third step, the deposition growing current-confining apertures Laminate construction thickness in the P-type heavily-doped semiconductor transport layer that the first step obtains
For 10~100nm, insulating material used in current limit pore structure is undoped HfO2；Followed by photoetching technique pair
Insulating material etches circular pattern, which covers the width of annulus along the edge of P-type heavily-doped semiconductor transport layer
Degree is 1~10 μm；
Current extending is deposited in 4th step on the current-confining apertures that third step obtains, and material is ITO, and by photoetching and
Wet etching makes graphical current extending, positioned at the top of P-type heavily-doped semiconductor transport layer and current-confining apertures；
5th step, atomic layer deposition (ALD) the medium DBR on the current extending that the 4th step obtains；
6th step, vapor deposition and optical graving make P-type Ohmic electrode width and are and N-type Ohmic electrode width respectively；
Thus the VCSEL device with high dielectric constant current-confining apertures of the invention is made.
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| CN113097864A (en) * | 2021-06-10 | 2021-07-09 | 常州纵慧芯光半导体科技有限公司 | Vertical-cavity surface-emitting laser array and preparation method thereof |
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