CN110265872A - A kind of bottom emissive type VCSEL chip and its manufacturing method - Google Patents
A kind of bottom emissive type VCSEL chip and its manufacturing method Download PDFInfo
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- CN110265872A CN110265872A CN201910527624.1A CN201910527624A CN110265872A CN 110265872 A CN110265872 A CN 110265872A CN 201910527624 A CN201910527624 A CN 201910527624A CN 110265872 A CN110265872 A CN 110265872A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/10—Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region
- H01S5/18—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities
- H01S5/183—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
- H01S5/18305—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL] with emission through the substrate, i.e. bottom emission
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/10—Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region
- H01S5/18—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities
- H01S5/183—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
- H01S5/18361—Structure of the reflectors, e.g. hybrid mirrors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/10—Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region
- H01S5/18—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities
- H01S5/185—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only horizontal cavities, e.g. horizontal cavity surface-emitting lasers [HCSEL]
- H01S5/187—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only horizontal cavities, e.g. horizontal cavity surface-emitting lasers [HCSEL] using Bragg reflection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S2304/00—Special growth methods for semiconductor lasers
Abstract
The present invention relates to laser chip technical fields, more particularly to a kind of bottom emissive type VCSEL chip and its manufacturing method, VCSEL chip includes GaAs substrate and the epitaxial structure positioned at the one side of substrate GaAs, GaAs substrate bottom etching goes out light hole, N-contact layers are vapor-deposited in light hole periphery on GaAs substrate, epitaxial structure includes N-DBR structure, oxide layer, Quantum Well, P-DBR structure and ohmic contact layer, ohmic contact layer, P-DBR structure, Quantum Well and AlGaAs are etched to N-DBR structure upper surface and form table top, ohmic contact layer is corresponding with light hole position, growth has ODR layers on ohmic contact layer, specular layer is vapor-deposited on ODR layers, table top, which is upwardly on specular layer, is covered with SiNx layer, SiNx layer It is etched with contact hole in light hole corresponding position on specular layer, P-contact layers are coated on SiNx layer, P-contact layers of filling contact hole.The structure design of VCSEL chip of the invention does not influence luminescence generated by light test, improves testing efficiency, reduces subsequent rejection rate, reduces the waste of raw material.
Description
Technical field
The present invention relates to laser chip technical field more particularly to a kind of bottom emissive type VCSEL chip and its manufacturers
Method.
Background technique
VCSEL is the abbreviation of vertical-cavity surface-emitting laser, refers to vertical-cavity surface-emitting
Laser, resonant cavity are to form two distribution Bragg reflectors with high reflectivity using on the both sides up and down of active area
(Dis tribute Bragg Reflector, abbreviation DBR) is constituted, and laser is along material epitaxy direction of growth Vertical Launch.With
Edge-emitting laser (Edge Emitting Laser, abbreviation EEL) is compared, and VCSEL has circular light spot, is easily carried out with optical fiber
Coupling, it is not necessary to which technique production and detection can be completed in dissociation, it is easy to accomplish the advantages such as large scale array and photoelectricity are integrated.
It is more that general bottom emissive type VCSEL extension DBR can grow into P-DBR ratio N-DBR logarithm, so that it is anti-to reach P-DBR
Rate ratio N-DBR high is penetrated, but such design, when carrying out PL (luminescence generated by light) test, light beam can not be normal through DBR layer to quantum
Trap, so that effective PL (luminescence generated by light) test can not be carried out.Can not carry out PL test just can not confirm whether extension parameter meets
Subsequent job requirement can only lean on after epitaxial wafer is made into chip and carry out the confirmation of extension parameter, in production if chips is waited to be made into
Tested again afterwards, then because in production the problem of cannot be resolved in time, rejection rate can not have always been high any more, greatly
It is big to waste raw material and improve the cost of production.
Summary of the invention
In view of this, being prepared into the object of the present invention is to provide a kind of bottom emissive type VCSEL chip and its manufacturing method
To VCSEL chip structure design do not influence luminescence generated by light test, improve testing efficiency, reduce subsequent rejection rate, subtract
The waste of raw material is lacked.
The present invention solves above-mentioned technical problem by following technological means:
One aspect of the present invention is to provide a kind of bottom emissive type VCSEL chip, including GaAs substrate and is located at GaAs and serves as a contrast
The epitaxial structure of bottom side, the GaAs substrate bottom etching go out light hole, are deposited on the GaAs substrate in light hole periphery
There are N-contact layers, the epitaxial structure includes the N-DBR structure, oxide layer, Quantum Well, P-DBR being sequentially depositing from the bottom to top
Structure and ohmic contact layer, the ohmic contact layer, P-DBR structure, Quantum Well and AlGaAs are etched to table in N-DBR structure
Face forms table top, and the ohmic contact layer is corresponding with light hole position, and the size dimension of the ohmic contact layer and light out
Hole it is identical, growth has ODR layers on the ohmic contact layer, it is ODR layers described on be vapor-deposited with specular layer, the table top is upwardly into mirror
SiNx layer is covered in surface layer, the SiNx layer is etched with contact hole, the SiNx in light hole corresponding position on specular layer
P-contact layers are coated on layer, the P-contact layers of filling contact hole.
Further, the N-DBR structure includes 35 pairs of DBR layers of overlapping growth, and the P-DBR structure includes overlapping growth
28 pairs of DBR layers.
Further, the generation material of the DBR layer is AlGaAs.
Further, the material of the N-contact uses AuGe and Au material, and the P-contact uses Ti, Pt and Au
Material.
Further, described ODR layers includes 10 pairs of ODR units for being overlapped growth, and the ODR unit includes overlapping growth
ITO layer and SiO2Layer, the ITO layer and SiO2The thickness of layer is λ/4n.
Further, the mirror surface layer material is Au.
Further, the oxide layer includes conductive structure and the oxidation structure for surrounding the conductive structure, the conductive knot
Structure uses Al0.98GaAs grows to be formed.
It is another aspect of the invention to provide a kind of above-mentioned manufacturing methods of bottom emissive type VCSEL chip, including
Following steps:
GaAs substrate is provided；
On gaas substrates first grow 35 pairs using AlGaAs the N-DBR structure of material, then grow one layer with
Al0.98GaAs layers, secondly grown quantum trap, then grows 28 pairs using AlGaAs the P-DBR structure of material, finally grows one layer
GaAs is as ohmic contact layer；
ICP etches ohmic contact layer, P-DBR structure, Quantum Well, conductive structure to N-DBR body structure surface, and dry ecthing is put into effect
Then face is again etched ohmic contact layer, etch light hole size, and by Al0.98GaAs layers of progress partial oxidation are formed
Conductive structure and oxidation structure；
Alternating growth 10 is to ITO and SiO on ohmic contact layer after the etching2, as ODR layers；
Etch 9 layers of ITO layer and 10 layers of SiO2ITO layer to the bottom forms important actor, reuses vapor deposition board on important actor
One layer of specular layer is deposited；
SiNx layer is grown from N-DBR body structure surface to mirror surface layer surface, corresponding ohmic contact layer position etches SiNx layer shape
P-contact layers are formed with contact hole evaporation metal at contact hole, then on SiNx layer；
By GaAs substrate thinning and light hole is etched, forms N- in evaporation metal outside light hole on gaas substrates
Contact layers.
Further, the position of the ohmic contact layer, contact hole and light hole is corresponding, the size dimension of the contact hole and
The size dimension of light hole is all the same.
Bottom emissive type VCSEL chip of the invention still uses N-DBR reflectivity to be greater than P-DBR in epitaxial growth
Design, do not influence luminescence generated by light PL test, but N-DBR and P-DBR is few compared with conventional growth logarithm when epitaxial growth, when purpose
Emissivity is excessively high in order to prevent causes subsequent ODR system that can not be more than N-DBR emissivity.Bottom emissive type VCSEL of the invention
The reflectivity of ODR layer and Au specular layer cooperation P-DBR in chip is higher than N-DBR, so that without inverting growth N-DBR and P-
DBR also can reach bottom light-out effect.The structure design of bottom emissive type VCSEL chip of the invention does not influence luminescence generated by light survey
Examination, improves testing efficiency, reduces subsequent rejection rate, reduce the waste of raw material.
Detailed description of the invention
The chip structure schematic diagram of a kind of position Fig. 6 bottom emissive type VCSEL chip of the invention and its manufacturing method；
Fig. 1-Fig. 6 is each step in a kind of bottom emissive type VCSEL chip of the invention and its manufacturing method preparation method
Corresponding structural schematic diagram；
Wherein, GaAs substrate 100, N-DBR structure 110, Al0.98GaAs layer 12, oxide layer 120, conductive structure 121, oxygen
Change structure 122, Quantum Well 130, P-DBR structure 140, ohmic contact layer 150, N-contact layer 210, P-contact layer 220,
Table top 3, light hole 4, ODR layer 500, specular layer 600, SiNx layer 700.
Specific embodiment
Below with reference to the drawings and specific embodiments, the present invention is described in detail, it is clear that described embodiment is only
It is merely some embodiments of the present application, instead of all the embodiments, based on the embodiment in the application, the common skill in this field
Art personnel every other embodiment obtained without making creative work belongs to the model of the application protection
It encloses.In addition, it is necessary to illustrate, the technological parameter for not carrying out particular determination in the present invention is all made of VCSEL chip common process
Parameter.
As shown in fig. 6, a kind of bottom emissive type VCSEL chip of the invention, including GaAs substrate 100 and it is located at GaAs and serves as a contrast
The epitaxial structure of 100 side of bottom, 100 bottom etching of GaAs substrate have a light hole 160, in outside light hole 160 on GaAs substrate 100
It encloses and is vapor-deposited with N-contact layer 210, N-contact layers generate the material used and can be but not limited to AuGe and Au, epitaxy junction
Structure includes that the N-DBR structure 110 being sequentially depositing from the bottom to top, oxide layer 120, Quantum Well 130, P-DBR structure 140 and ohm connect
Contact layer 150, specifically, N-DBR structure 110 includes 35 pairs of DBR layers of overlapping growth, P-DBR structure 140 includes overlapping growth
28 pairs of DBR layers, the generation material of DBR layer are AlGaAs；Oxide layer 120 includes conductive structure 121 and encirclement conductive structure 121
Oxidation structure 122, conductive structure 121 use Al0.98GaAs grows to be formed, and oxidation structure 122 is by conductive structure, that is, Al0.98GaAs
Raw oxidation-treated rear formation, the Quantum Well of the present embodiment use regular quantum well structure.
Ohmic contact layer 150, P-DBR structure 140, Quantum Well 130 and oxide layer 120 are etched in N-DBR structure 110
Surface formed table top 3, ohmic contact layer 130 is corresponding with 4 position of light hole, and the size dimension of ohmic contact layer 150 with out
Unthreaded hole 4 it is identical, on ohmic contact layer 130 growth have ODR layer 500, specifically, ODR layer 500 include be overlapped grow 10 pairs
ODR unit, ODR unit include the ITO layer and SiO of overlapping growth2Layer, ITO layer and SiO2The thickness of layer is λ/4n, λ therein
For the target wavelength of VCSEL chip.It is vapor-deposited with specular layer 600 on ODR layer 500, the raw material that specular layer 600 uses includes but unlimited
In Au, table top 4, which is upwardly on specular layer 600, is covered with SiNx layer 700, and 700 part of SiNx layer covers specular layer 600, and in mirror
It is etched with contact hole in 4 corresponding position of light hole in surface layer 600, P-contact layer 220, P- is coated on SiNx layer 700
The raw material that contact layer 220 uses includes but is not limited to Ti, Pt and Au material, and P-contact layer 220 covers N-DBR structure
110 or more structure, and filling contact hole.
The reflectivity of ODR layer and Au specular layer cooperation P-DBR in the VCSEL chip of above-described embodiment description is higher than N-
DBR, so that also can reach bottom light-out effect without inverting growth N-DBR and P-DBR.The design of its structure does not influence luminescence generated by light
Test, improves testing efficiency, reduces subsequent rejection rate, reduce the waste of raw material.
The preparation method of above-mentioned bottom emissive type VCSEL chip, specific as follows:
S1: such as Fig. 1, providing GaAs substrate 100, grows 35 pairs first on GaAs substrate 100 using AlGaAs material
Then N-DBR structure 110 grows one layer of Al0.98Oxide layer 120 when GaAs layer 12 is as subsequent chip manufacturing, secondly according to
Conventional method grown quantum trap 130 then grows 28 pairs using AlGaAs the P-DBR structure 140 of material, finally grows one layer
GaAs is as ohmic contact layer 150；
S2: such as Fig. 2, ohmic contact layer 150, P-DBR structure 140, Quantum Well 130, conductive structure 120 are etched using ICP
To 110 surface of N-DBR structure, dry ecthing goes out table top 3, is then etched again to ohmic contact layer 150, and etching light hole 4 is big
It is small, and according to conventional wet oxidation method by Al0.98GaAs layer 12 carries out partial oxidation, forms conductive structure 121 and oxidation knot
Structure 122；
S3: such as Fig. 3, alternating growth 10 is to ITO and SiO on the ohmic contact layer 150 after etching2, as ODR layer 500,
ITO layer and SiO2The thickness of layer is λ/4n, and λ therein is the target wavelength of VCSEL chip；
S4: such as Fig. 4,9 layers of ITO layer and 10 layers of SiO are etched2ITO layer to the bottom forms important actor, leaves basecoat
ITO layer retains whole face as current extending, reuses vapor deposition board and one layer of specular layer 600 is deposited on important actor；
S5: such as Fig. 5, SiNx layer 700, corresponding Ohmic contact are grown from 110 surface of N-DBR structure to 600 surface of specular layer
Etching SiNx layer 700 in 150 position of layer forms contact hole, then is formed on SiNx layer 700 with contact hole evaporation metal Ti, Pt, Au
P-contact layer 220；
S6: such as Fig. 6, being thinned to 120um for GaAs substrate 100, and etch light hole 4, in out on GaAs substrate 100
Unthreaded hole outer evaporation metal AuGe and Au form N-contact layer 210.
The bottom emissive type VCSEL chip that above-mentioned manufacturing method manufactures, still uses N-DBR anti-in epitaxial growth
The design that rate is greater than P-DBR is penetrated, does not influence luminescence generated by light PL test, but N-DBR and P-DBR are compared with conventional growth when epitaxial growth
Logarithm is few, and emissivity is excessively high in order to prevent when purpose causes subsequent ODR system that can not be more than N-DBR emissivity.
The above examples are only used to illustrate the technical scheme of the present invention and are not limiting, although referring to preferred embodiment to this hair
It is bright to be described in detail, those skilled in the art should understand that, it can modify to technical solution of the present invention
Or equivalent replacement should all cover without departing from the objective and range of technical solution of the present invention in claim of the invention
In range.Technology not described in detail in the present invention, shape, construction portion are well-known technique.
Claims (9)
1. a kind of bottom emissive type VCSEL chip, which is characterized in that the extension including GaAs substrate and positioned at the one side of substrate GaAs
Structure, the GaAs substrate bottom etching have a light hole, are vapor-deposited with N-contact in light hole periphery on the GaAs substrate
Layer, the epitaxial structure includes the N-DBR structure being sequentially depositing from the bottom to top, oxide layer, Quantum Well, P-DBR structure and ohm
Contact layer, the ohmic contact layer, P-DBR structure, Quantum Well and oxide layer are etched to N-DBR structure upper surface and form platform
Face, the ohmic contact layer is corresponding with light hole position, and the size dimension of the ohmic contact layer is identical as light hole,
Growth has ODR layers on the ohmic contact layer, it is ODR layers described on be vapor-deposited with specular layer, the table top, which is upwardly on specular layer, to be covered
It is stamped SiNx layer, the SiNx layer is etched with contact hole in light hole corresponding position on specular layer, coats on the SiNx layer
There are P-contact layers, the P-contact layers of filling contact hole.
2. a kind of bottom emissive type VCSEL chip according to claim 1, which is characterized in that the N-DBR structure includes
35 pairs of DBR layers of growth are overlapped, the P-DBR structure includes 28 pairs of DBR layers of overlapping growth.
3. a kind of bottom emissive type VCSEL chip according to claim 2, which is characterized in that the generation material of the DBR layer
Material is AlGaAs.
4. a kind of bottom emissive type VCSEL chip according to claim 1, which is characterized in that the material of the N-contact
Material uses AuGe, Au material, and the P-contact uses Ti, Pt and Au material.
5. a kind of bottom emissive type VCSEL chip according to claim 1, which is characterized in that described ODR layers includes overlapping
10 pairs of ODR units of growth, the ODR unit include the ITO layer and SiO of overlapping growth2Layer, the ITO layer and SiO2The thickness of layer
Degree is λ/4n.
6. a kind of bottom emissive type VCSEL chip according to claim 1, which is characterized in that the mirror surface layer material is
Au。
7. -6 any a kind of bottom emissive type VCSEL chip according to claim 1, which is characterized in that the oxide layer
Oxidation structure including conductive structure and the encirclement conductive structure, the conductive structure use Al0.98GaAs grows to be formed.
8. a kind of manufacturing method of bottom emissive type VCSEL chip, which comprises the steps of:
GaAs substrate is provided；
35 pairs are grown first on gaas substrates using AlGaAs the N-DBR structure of material, grow one layer then with Al0.98GaAs
Layer, secondly grown quantum trap, then grows 28 pairs using AlGaAs the P-DBR structure of material, finally grows one layer of GaAs conduct
Ohmic contact layer；
ICP etches ohmic contact layer, P-DBR, Quantum Well, conductive structure to N-DBR body structure surface, and dry ecthing goes out table top, then
Ohmic contact layer is etched again, etches light hole size, and by Al0.98GaAs layers of progress partial oxidation form conductive knot
Structure and oxidation structure；
Alternating growth 10 is to ITO and SiO on ohmic contact layer after the etching2, as ODR layers；
Etch 9 layers of ITO layer and 10 layers of SiO2ITO layer to the bottom forms important actor, reuses vapor deposition board and one is deposited on important actor
Layer specular layer；
SiNx layer is grown from N-DBR body structure surface to mirror surface layer surface, corresponding ohmic contact layer position etching SiNx layer formation connects
Contact hole, then P-contact layers are formed with contact hole evaporation metal on SiNx layer；
By GaAs substrate thinning and light hole is etched, forms N-contact in evaporation metal outside light hole on gaas substrates
Layer.
9. a kind of manufacturing method of bottom emissive type VCSEL chip according to claim 8, which is characterized in that the Europe
The position of nurse contact layer, contact hole and light hole is corresponding, and the size dimension of the contact hole and the size dimension of light hole are homogeneous
Together.
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| CN113314945A (en) * | 2021-07-30 | 2021-08-27 | 华芯半导体研究院(北京)有限公司 | VCSEL chip with back side radiating function and preparation method and application thereof |
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Application publication date: 20190920 |
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