CN110231794A - Serial communication controller based on safe cpu chip - Google Patents
Serial communication controller based on safe cpu chip Download PDFInfo
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- CN110231794A CN110231794A CN201910614498.3A CN201910614498A CN110231794A CN 110231794 A CN110231794 A CN 110231794A CN 201910614498 A CN201910614498 A CN 201910614498A CN 110231794 A CN110231794 A CN 110231794A
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- 238000004891 communication Methods 0.000 title claims abstract description 77
- 238000006243 chemical reaction Methods 0.000 claims abstract description 25
- 230000015654 memory Effects 0.000 claims description 26
- 238000012545 processing Methods 0.000 claims description 8
- 238000000034 method Methods 0.000 claims description 7
- 230000008569 process Effects 0.000 claims description 6
- 230000005540 biological transmission Effects 0.000 abstract description 21
- 238000005516 engineering process Methods 0.000 abstract description 4
- 239000000203 mixture Substances 0.000 abstract description 2
- 230000000694 effects Effects 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0423—Input/output
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/24—Pc safety
- G05B2219/24215—Scada supervisory control and data acquisition
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- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Automation & Control Theory (AREA)
- Storage Device Security (AREA)
Abstract
The present invention provides a kind of serial communication controllers based on safe cpu chip, are related to Serial Communication Control Technology field, mainly solve in the prior art serial communication data transmission it is dangerous, the technical issues of leading to loss of data, be stolen.The present invention is by safe cpu controller and the level shifter interface module being connected with safe cpu controller, serial parallel conversion module, input module, output module, and there are also the serial communication module being connected with the level switch module, power circuit compositions.The present invention carries out encryption and decryption to data, has ensured the safety of transmission data, has prevented network attack from making loss of data, being stolen, be provided with practical, convenient advantage, moreover it is possible to increase operating rate, improve working efficiency.
Description
Technical field
The present invention relates to Serial Communication Control Technology field more particularly to a kind of serial communications based on safe cpu chip
Controller.
Background technique
With the development of computer network and microcomputer grading distribution application system, the function of communication is more and more important.
Communication refers to that computer and extraneous information transmit, and both includes the transmission between computer and computer, also include computer with
Transmission between external equipment, such as terminal, printer and disk equipment.In the communications field, by biography every time in data communication
The data bits sent, communication mode can be divided into: parallel communications and serial communication.
Serial communication refer between main frame and peripheral hardware and between host system and host system data it is serial
Transmission.By data line, one ground of data is successively transmitted, each data occupies a regular time length.Its
Only need several lines that can exchange information between system, especially suitable for computer and computer, computer and peripheral hardware
Between telecommunication.
Although serial communication saves wiring, provide convenience for telecommunication, its transmission mode is easy to cause
Loss of data is revealed, is stolen, and missing, the imperfection of data are caused, and influences use, the judgement of equipment and artificial subsequent operation.
Summary of the invention
The one of purpose of the present invention is solved to propose a kind of serial communication controller based on safe cpu chip
Serial communication data transmission is dangerous in the prior art, the technical issues of lead to loss of data, be stolen.The present invention is preferably real
Many beneficial effects can be reached by applying in scheme, be specifically shown in and be set forth below.
To achieve the above object, the present invention provides following technical schemes:
A kind of serial communication controller based on safe cpu chip of the invention, including safe cpu controller and with safety
Level shifter interface module that cpu controller is connected, serial parallel conversion module, there are also be connected with the level switch module
Serial communication module.
Further, the safe cpu controller monitors serial communication mould for the data in encryption and decryption serial communication
Block, level shifter interface module, serial parallel conversion module operating status and process processing；
The serial communication module is connected for providing serial communication interface with external equipment, and then acquires, transmission
Serial communication data；
The level shifter interface module when for being connected with external equipment, carries out level conversion；
The serial parallel conversion module, using shift register, for realizing the serial parallel for transmitting data in serial communication
Conversion.
Further, further include power circuit, provide power supply for serial communication controller.
Further, the safe cpu controller includes safe cpu chip, memory module, safe cpu chip and storage
Module is connected；
The safe cpu chip monitors serial communication module, level conversion for the data in encryption and decryption serial communication
Interface module, serial parallel conversion module operating status and process processing；
The memory module, for storing code key, the operation information of the data in serial communication, encryption and decryption.
Further, the safe cpu chip, including processor core and the cache mould being connected with processor core
Block, Memory control module, clock module.
Further, the processor core is not limited to a processor core.
Further, the processor core supports MIPS64 instruction set and LISA64 instruction set.
Further, the cache module includes the privately owned first-level instruction caching of 64KB and 64KB of each processor core
Privately owned level one data caching, all processor cores share the L2 cache of 1MB.
Further, the memory module includes random access memory ram, read only memory ROM, flash memories
FLASH。
Further, further include the input module being connected with safe cpu controller, be used for incoming serial communication controler
Number and/or analogue data.
It further, further include the output module being connected with safe cpu controller, for exporting serial communication controller
Number and/or analogue data.
Serial communication controller provided by the invention based on safe cpu chip at least has following advantageous effects:
The present invention is mainly by safe cpu controller and the level shifter interface module being connected with safe cpu controller, string
Parallel transformation module, there are also the serial communication module being connected with level switch module compositions.The safe CPU control
Device uses safe cpu chip, for the data in encryption and decryption serial communication, monitors serial communication module, level shifter interface
Module, serial parallel conversion module, input module, output module operating status and process processing.Safe cpu controller and safety
Cpu chip is in the case of ensureing data stabilization transmission, moreover it is possible to carry out encryption and decryption to data, providing safety for data transmission can
The guarantee barrier leaned on, makes data be not easy to be stolen, lose, and improves the speed and safety of data transmission.
The level shifter interface when for being connected with multiple external equipments, carrying out level conversion, making the present invention and its
His equipment carries out safe and reliable, compatible connection.The serial parallel conversion module, using shift register, for the number in transmission
According to serial-parallel conversion has been carried out, have the characteristics that quick, practical.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments of invention for those of ordinary skill in the art without creative efforts, can be with
It obtains other drawings based on these drawings.
Fig. 1 is overall structure diagram of the invention.
The safe cpu controller of 1- in figure, 2- level shifter interface module, 3- serial communication module, 4- serial parallel modulus of conversion
Block, 5- input module, 6- output module, 7- power circuit；The safe cpu chip of 11-, 12- memory module.
Specific embodiment
To make the object, technical solutions and advantages of the present invention clearer, technical solution of the present invention will be carried out below
Detailed description.Obviously, described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.Base
Embodiment in the present invention, those of ordinary skill in the art are obtained all without making creative work
Other embodiment belongs to the range that the present invention is protected.
The present invention is a kind of serial communication controller based on safe cpu chip, by safe cpu controller 1 and with safety
Level shifter interface module 2 that cpu controller 1 is connected, serial parallel conversion module 4, input module 5, output module 6, also
The serial communication module 3 being connected with the level switch module 2, power circuit 7 form.The power circuit 7 is serial logical
Believe that controller provides power supply.
The safe cpu controller 1 includes safe cpu chip 11, memory module 12, safe cpu chip 11 and storage mould
Block 12 is connected.
The safe cpu controller 1 and safe cpu chip 11, for the data in encryption and decryption serial communication, monitoring is serial
Communication module 3, level shifter interface module 2, serial parallel conversion module 4, input module 5,6 operating status of output module and process
Processing.The safe cpu controller 1 and safe cpu chip 11 have ensured the safe transmission of data of the present invention, also prevent to this
Invention carries out network attack, reduces the influence that data are stolen, steal, abusing, and improves the performance of transmission data.
The memory module 12, for storing code key, the operation information of the data in serial communication, encryption and decryption.It is described to deposit
Storing up module 12 includes random access memory ram, read only memory ROM, flash memories FLASH.
The safe cpu chip 11, including processor core and the cache module being connected with processor core, memory control
Molding block, clock module."Longxin" chip can be used in the safe cpu chip, other chips can also be used.
The processor core is not limited to a processor core, supports MIPS64 instruction set and LISA64 instruction set.Multiprocessing
Device core significantly reduces the power consumption in safe cpu chip work, and processing operating rate is fast, improves efficiency.
The cache module includes the privately owned first-level instruction caching of 64KB and the privately owned level-one of 64KB of each processor core
Data buffer storage, all processor cores share the L2 cache of 1MB.Its hit rate is higher, improves work effect for safe cpu chip
Rate.
The Memory control module uses DDR2 and/or DDR3 controller.DDR is a kind of memory generated after SDRAM
Technology, DDR, English original meaning are " DoubleDataRate ", are exactly Double Data transmission mode.SDRAM used in we are daily
It is all " forms data transmission mode " that the characteristic of this memory is in a memory clock cycle, in a square wave rising edge
It carries out once-through operation (reading or writing), and DDR then refers to a kind of new design, in a memory clock cycle, in square wave
Once-through operation is carried out when rising edge, and once-through operation is also done in the failing edge of square wave, why in a clock cycle, DDR
The task that two periods of SDRAM could complete can then be completed, thus theoretically the DDR memory of same rate compared with SDR memory,
Performance will exceed one times.Therefore, DDR2 or DDR3 has higher external transfer rate, more advanced address/command and control
The topology framework of bus processed further decreases energy consumption while guaranteeing performance.
The frequency of the clock module is 1GHz, then makes the speed of present invention transmission data fast, high-efficient.
The serial communication module 3 is connected for providing serial communication interface with external equipment, and then acquires, transmission
Serial communication data.Such as: serial communication module 3 can be RS-232, RS-422, RS-485 interface.
The level shifter interface module 2 when for being connected with external equipment, carries out level conversion, is various serial
Communication interface has carried out level reconciliation, more harmonious, identical transmission data.
The serial parallel conversion module 4, using shift register, for realizing the serial parallel for transmitting data in serial communication
Conversion.Therefore, the data transmission that can meet serial communication device and parallel communication device simultaneously has serial communication and leads to parallel
Two kinds of features of letter reduce single transmission data bring trouble.
The input module 5, number and/or analogue data for incoming serial communication controler.
The output module 6, for exporting the number and/or analogue data of serial communication controller.
The above description is merely a specific embodiment, but scope of protection of the present invention is not limited thereto, any
Those familiar with the art in the technical scope disclosed by the present invention, can easily think of the change or the replacement, and should all contain
Lid is within protection scope of the present invention.Therefore, protection scope of the present invention should be based on the protection scope of the described claims.
Claims (10)
1. a kind of serial communication controller based on safe cpu chip, which is characterized in that including safe cpu controller and with peace
Level shifter interface module that full cpu controller is connected, serial parallel conversion module, there are also be connected with the level switch module
The serial communication module connect；
The safe cpu controller monitors serial communication module, level conversion connects for the data in encryption and decryption serial communication
Mouth mold block, serial parallel conversion module operating status and process processing；
The serial communication module is connected for providing serial communication interface with external equipment, and then acquires, transmits serially
Communication data；
The level shifter interface module when for being connected with external equipment, carries out level conversion；
The serial parallel conversion module, using shift register, for realizing the serial parallel conversion for transmitting data in serial communication.
2. serial communication controller according to claim 1, which is characterized in that further include power circuit, be serial communication
Controller provides power supply.
3. serial communication controller according to claim 1, which is characterized in that the safe cpu controller includes safety
Cpu chip, memory module, safe cpu chip are connected with memory module；
The safe cpu chip monitors serial communication module, level shifter interface for the data in encryption and decryption serial communication
Module, serial parallel conversion module operating status and process processing；
The memory module, for storing code key, the operation information of the data in serial communication, encryption and decryption.
4. serial communication controller according to claim 3, which is characterized in that the safe cpu chip, including processor
Core and the cache module being connected with processor core, Memory control module, clock module.
5. serial communication controller according to claim 4, which is characterized in that the processor core is not limited to a processing
Device core.
6. serial communication controller according to claim 5, which is characterized in that the processor core supports MIPS64 instruction
Collection and LISA64 instruction set.
7. serial communication controller according to claim 3, which is characterized in that the cache module includes each place
The privately owned first-level instruction caching of 64KB and the privately owned level one data caching of 64KB, all processor cores for managing device core share the second level of 1MB
Caching.
8. serial communication controller according to claim 1, which is characterized in that the memory module includes that arbitrary access is deposited
Reservoir RAM, read only memory ROM, flash memories FLASH.
9. serial communication controller according to claim 1, which is characterized in that further include being connected with safe cpu controller
The input module connect, number and/or analogue data for incoming serial communication controler.
10. serial communication controller according to claim 1, which is characterized in that further include being connected with safe cpu controller
The output module connect, for exporting the number and/or analogue data of serial communication controller.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910614498.3A CN110231794A (en) | 2019-07-09 | 2019-07-09 | Serial communication controller based on safe cpu chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910614498.3A CN110231794A (en) | 2019-07-09 | 2019-07-09 | Serial communication controller based on safe cpu chip |
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| Publication Number | Publication Date |
|---|---|
| CN110231794A true CN110231794A (en) | 2019-09-13 |
Family
ID=67857937
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910614498.3A Pending CN110231794A (en) | 2019-07-09 | 2019-07-09 | Serial communication controller based on safe cpu chip |
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Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0193305A2 (en) * | 1985-02-13 | 1986-09-03 | Texas Instruments Incorporated | System interface for coupling standard microprocessor to a communications adapter |
| JPH052478A (en) * | 1991-06-26 | 1993-01-08 | Nec Corp | Program protecting system |
| WO2004021159A1 (en) * | 2002-08-30 | 2004-03-11 | Laboratories For Information Technology | A wireless communication host controller interface device |
| CN101154207A (en) * | 2006-09-29 | 2008-04-02 | 上海海尔集成电路有限公司 | Operating method for configured interface of microcontroller |
| CN101714917A (en) * | 2009-08-24 | 2010-05-26 | 黑龙江大学 | Chaotic key-based data encryption transmission card |
| CN101958789A (en) * | 2010-09-17 | 2011-01-26 | 北京航空航天大学 | High-speed data encryption/decryption module in communication link |
| CN105159200A (en) * | 2015-09-21 | 2015-12-16 | 郑州精益达汽车零部件有限公司 | Overall vehicle controller based on function safety |
| CN105553617A (en) * | 2015-12-21 | 2016-05-04 | 大连三高集团有限公司 | Serial port communication data analysis method |
| CN210402052U (en) * | 2019-07-09 | 2020-04-24 | 四川米众网络科技股份有限公司 | Serial communication controller based on safe CPU chip |
-
2019
- 2019-07-09 CN CN201910614498.3A patent/CN110231794A/en active Pending
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0193305A2 (en) * | 1985-02-13 | 1986-09-03 | Texas Instruments Incorporated | System interface for coupling standard microprocessor to a communications adapter |
| JPH052478A (en) * | 1991-06-26 | 1993-01-08 | Nec Corp | Program protecting system |
| WO2004021159A1 (en) * | 2002-08-30 | 2004-03-11 | Laboratories For Information Technology | A wireless communication host controller interface device |
| CN101154207A (en) * | 2006-09-29 | 2008-04-02 | 上海海尔集成电路有限公司 | Operating method for configured interface of microcontroller |
| CN101714917A (en) * | 2009-08-24 | 2010-05-26 | 黑龙江大学 | Chaotic key-based data encryption transmission card |
| CN101958789A (en) * | 2010-09-17 | 2011-01-26 | 北京航空航天大学 | High-speed data encryption/decryption module in communication link |
| CN105159200A (en) * | 2015-09-21 | 2015-12-16 | 郑州精益达汽车零部件有限公司 | Overall vehicle controller based on function safety |
| CN105553617A (en) * | 2015-12-21 | 2016-05-04 | 大连三高集团有限公司 | Serial port communication data analysis method |
| CN210402052U (en) * | 2019-07-09 | 2020-04-24 | 四川米众网络科技股份有限公司 | Serial communication controller based on safe CPU chip |
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