CN110223990B - 顶栅结构及其制备方法、阵列基板、显示设备 - Google Patents
顶栅结构及其制备方法、阵列基板、显示设备 Download PDFInfo
- Publication number
- CN110223990B CN110223990B CN201910527753.0A CN201910527753A CN110223990B CN 110223990 B CN110223990 B CN 110223990B CN 201910527753 A CN201910527753 A CN 201910527753A CN 110223990 B CN110223990 B CN 110223990B
- Authority
- CN
- China
- Prior art keywords
- layer
- gate
- gate insulating
- insulating layer
- interlayer dielectric
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 22
- 238000002360 preparation method Methods 0.000 title abstract description 6
- 239000010410 layer Substances 0.000 claims description 228
- 239000011229 interlayer Substances 0.000 claims description 31
- 238000000034 method Methods 0.000 claims description 12
- 239000010409 thin film Substances 0.000 claims description 10
- 229910052751 metal Inorganic materials 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 7
- 239000000463 material Substances 0.000 claims description 6
- 230000003647 oxidation Effects 0.000 claims description 6
- 238000007254 oxidation reaction Methods 0.000 claims description 6
- 230000008569 process Effects 0.000 claims description 6
- 230000001590 oxidative effect Effects 0.000 claims description 4
- 229910044991 metal oxide Inorganic materials 0.000 claims description 3
- 150000004706 metal oxides Chemical group 0.000 claims description 3
- 230000007547 defect Effects 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 9
- LYCAIKOWRPUZTN-UHFFFAOYSA-N Ethylene glycol Chemical compound OCCO LYCAIKOWRPUZTN-UHFFFAOYSA-N 0.000 description 6
- 238000010438 heat treatment Methods 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 6
- 229920001621 AMOLED Polymers 0.000 description 5
- 230000037303 wrinkles Effects 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 239000003792 electrolyte Substances 0.000 description 3
- 239000010408 film Substances 0.000 description 3
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000009471 action Effects 0.000 description 2
- 238000004220 aggregation Methods 0.000 description 2
- 230000002776 aggregation Effects 0.000 description 2
- NGPGDYLVALNKEG-UHFFFAOYSA-N azanium;azane;2,3,4-trihydroxy-4-oxobutanoate Chemical compound [NH4+].[NH4+].[O-]C(=O)C(O)C(O)C([O-])=O NGPGDYLVALNKEG-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000007743 anodising Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1237—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a different composition, shape, layout or thickness of the gate insulator in different devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78636—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with supplementary region or layer for improving the flatness of the device
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
- H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Geometry (AREA)
- Thin Film Transistor (AREA)
Abstract
本发明实施例提供一种顶栅结构及其制备方法、阵列基板、显示设备。顶栅结构包括栅绝缘层以及形成于所述栅绝缘层之上的栅极层，所述栅极层覆盖部分栅绝缘层，将另一部分栅绝缘层暴露形成栅绝缘层凸部，其特征在于，还包括形成于所述栅极层之上的补偿层，所述补偿层将所述栅绝缘层凸部覆盖；本发明有效降低DGS不良，提升产品良率。
Description
技术领域
本发明涉及显示技术领域，具体涉及一种顶栅结构及其制备方法、阵列基板、显示设备。
背景技术
目前AMOLED(Active-matrix organic light-emitting diode，中译：有源矩阵有机发光二极体或主动矩阵有机发光二极体)产品正向着高清、大尺寸和高刷新频率进行。这就对AMOLED驱动电路的TFT有了更高的要求。目前用于AMOLED驱动电路的TFT结构主要有蚀阻挡层结构(ESL)、顶栅结构(Top Gate)、背沟道刻蚀结构(BCE)。其中Top Gate能够有效的降低寄生电容，刷新频率更好；沟道更短，尺寸更小，更能满足AMOLED发展的需要，故TopGate结构是未来研发的一个重点方向。
顶栅结构薄膜晶体管技术中薄膜晶体管栅极与源漏极层(SD)无重叠，因此寄生电容非常低，同时由于布局灵活，所以在高分辨率、高刷新率、窄边框、低功耗的大尺寸OLED产品应用方面更具优势。然而，现有技术的顶栅结构中，在层间电介质层(Inter LayerDielectrics)与源漏极层(SD)的交叠处会出现褶皱，导致栅极层(Gate)与源漏极层(SD)之间的层间电介质层由于覆盖能力差导致厚度变薄，这种褶皱在源漏极层沉积后会形成类似尖端现象，引发电流聚集从而引起Heating(避雷针作用)，在层间电介质层最薄的区域发生相对较高的发热现象，发热引起层间电介质层空隙变大或者引起应力部分变形，导致发生DGS(Data Gate Short，栅线和数据线短接)不良。
发明内容
本发明实施例所要解决的技术问题是，提供一种顶栅结构及其制备方法、阵列基板、显示设备，有效降低DGS不良，提升产品良率。
为了解决上述技术问题，本发明实施例提供了一种顶栅结构，包括栅绝缘层以及形成于所述栅绝缘层之上的栅极层，所述栅极层覆盖部分栅绝缘层，将另一部分栅绝缘层暴露形成栅绝缘层凸部，还包括形成于所述栅极层之上的补偿层，所述补偿层将所述栅绝缘层凸部覆盖。
可选地，所述补偿层的材质为金属氧化物。
可选地，所述栅极层的材质为金属。
可选地，还包括形成于所述补偿层之上的层间电介质层。
可选地，还包括形成于所述层间电介质层之上的源漏极层。
可选地，所述补偿层的厚度为0.1um-1um。
本发明实施例还提供了一种阵列基板，包括前述顶栅结构。
本发明实施例还提供了一种显示设备，包括前述的阵列基板。
为了解决上述技术问题，本发明实施例还提供了一种顶栅结构的制备方法，包括：
形成栅绝缘层；
在所述栅绝缘层之上形成栅极层，所述栅极层覆盖部分栅绝缘层，将另一部分栅绝缘层暴露形成栅绝缘层凸部；
在栅极层之上形成覆盖所述栅绝缘层凸部的补偿层。
可选地，所述在栅极层之上形成覆盖所述栅绝缘层凸部的补偿层，包括：
通过阳极氧化工艺将部分栅极层氧化，使氧化后的部分栅极层向外延伸覆盖所述栅绝缘层凸部，形成所述补偿层。
本发明实施例提供了一种顶栅结构及其制备方法、阵列基板、显示设备，通过在栅极层之上形成补偿层，补偿栅绝缘层与栅极层存在的长度差，即使补偿层将栅绝缘层凸部覆盖，从而消除层间电介质层与源漏极层交叠处的褶皱，改善栅极层与源漏极层之间的搭接形貌，有效降低DGS(Data Gate Short，栅线和数据线短接)不良，提升产品良率。
当然，实施本发明的任一产品或方法并不一定需要同时达到以上所述的所有优点。本发明的其它特征和优点将在随后的说明书实施例中阐述，并且，部分地从说明书实施例中变得显而易见，或者通过实施本发明而了解。本发明实施例的目的和其他优点可通过在说明书、权利要求书以及附图中所特别指出的结构来实现和获得。
附图说明
附图用来提供对本发明技术方案的进一步理解，并且构成说明书的一部分，与本申请的实施例一起用于解释本发明的技术方案，并不构成对本发明技术方案的限制。附图中各部件的形状和大小不反映真实比例，目的只是示意说明本发明内容。
图1为现有顶栅结构的结构示意图；
图2为本发明实施例顶栅结构的结构示意图；
图3为本发明实施例形成栅绝缘层后的示意图；
图4为本发明实施例形成栅极层后的示意图；
图5为本发明实施例形成层间电介质层后的示意图；
图6为本发明实施例形成源漏极层后的示意图。
附图标记说明:
1—栅绝缘层； 2—栅极层； 3—层间电介质层；
4—源漏极层； 5—栅绝缘层凸部； 6—褶皱；
7—补偿层。
具体实施方式
下面结合附图和实施例对本发明的具体实施方式作进一步详细描述。以下实施例用于说明本发明，但不用来限制本发明的范围。需要说明的是，在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互任意组合。
图1为现有顶栅结构的结构示意图。如图1所示，现有顶栅结构包括栅绝缘层1、形成于栅绝缘层1之上的栅极层2、形成于栅极层2之上的层间电介质层3以及形成于层间电介质层3之上的源漏极层4，在层间电介质层3与源漏极层4的交叠处存在褶皱6。
经本申请发明人研究发现，现有顶栅结构为了减低TFT阈值电压的均匀性易受短沟道效应影响的问题，在顶栅结构的氧化物薄膜晶体管制备过程中，要保证栅绝缘层1的长度比栅极层2的长度长，即栅极层2覆盖部分栅绝缘层1，将另一部分栅绝缘层1暴露形成栅绝缘层凸部5。栅绝缘层凸部5是导致层间电介质层3与源漏极层4的交叠处形成褶皱6的原因。褶皱6会导致栅极层2与源漏极层4之间的层间电介质层3由于覆盖能力差导致厚度变薄，这种褶皱6在源漏极层4沉积后会形成类似尖端现象，引发电流聚集从而引起Heating(避雷针作用)，在层间电介质层3最薄的区域发生相对较高的发热现象，发热引起层间电介质层3空隙变大或者应力部分变形，容易发生DGS不良。
图2为本发明实施例顶栅结构的结构示意图。如图2所示，本发明实施例提供一种顶栅结构，包括栅绝缘层1以及形成于栅绝缘层1之上的栅极层2，栅极层2覆盖部分栅绝缘层1，将另一部分栅绝缘层1暴露形成栅绝缘层凸部5，即栅绝缘层1的长度比栅极层2的长度长。本发明实施例的顶栅结构还包括补偿层7，补偿层7形成于栅极层2之上，将栅绝缘层凸部5覆盖，补偿栅绝缘层1与栅极层2存在的长度差，从而消除层间电介质层与源漏极层交叠处的褶皱，改善栅极层与源漏极层之间的搭接形貌，有效降低DGS不良，提升产品良率。
第一实施例
下面通过本实施例顶栅结构的制备过程进一步说明本实施例的技术方案。
图2～6为本实施例顶栅结构制备过程的示意图。顶栅结构的制备过程包括：
(1)形成栅绝缘层。形成栅绝缘层包括：在基底上形成有源层，在有源层之上形成覆盖有源层的栅绝缘层1，如图3所示。
(2)形成栅极层。形成栅极层包括：在形成前述图案的基底上，沉积第一金属薄膜，通过构图工艺对第一金属薄膜进行构图，形成设置在栅绝缘层1上的栅极层2。其中，栅极层2覆盖部分栅绝缘层1，将另一部分栅绝缘层1暴露形成栅绝缘层凸部5，即栅绝缘层1的长度比栅极层2的长度长。如图4所示。实施例中，栅极层2的材质为金属，比如，栅极层2的材质为铝、铜等。
(3)形成补偿层。形成补偿层包括：在形成前述图案的基底上，通过阳极氧化工艺将部分栅极层2氧化，使氧化后的部分栅极层向外延伸覆盖栅绝缘层凸部5，形成补偿层7。具体地，以栅极层2的材质为铝，补偿层7的材质为氧化铝为例。在形成前述图案的基底上，将部分栅极层2进行阳极氧化包括：配制阳极氧化所需要的电解液，电解液为酒石酸铵、乙二醇和水的混合溶液。其中，酒石酸铵：乙二醇：水＝2wt.％:68wt.％:30wt.％。将电解池中放入上述电解液，再将形成前述图案的基底放入电解池中的阳极处，然后，在电解池的阳极施加一个恒定的电压，对形成前述图案基底上的部分栅极层2进行氧化，使栅极层2的表面氧化生成氧化铝，生成的氧化铝会不断的向外生长延伸，将暴露出的栅绝缘层凸部5覆盖，形成补偿层7，如图2所示。实施例中，补偿层7的厚度为0.1um-1um。
(4)形成层间电介质层。形成层间电介质层包括：在形成前述图案的基底上，采用等离子体增强化学的气相沉积法(Plasma Enhanced Chemical Vapor Deposition)，形成在补偿层7之上的层间电介质层3，如图5所示。其中，层间电介质层3的材质为氧化硅或氮化硅。
(5)形成源漏极层。形成源漏极层包括：在形成前述图案的基底上，采用磁控溅射设备，在层间电介质层3之上沉积第二金属薄膜，形成设置在层间电介质层3上的源漏极层4，如图6所示。其中，源漏极层4的材质为金属，例如，源漏极层4的材质为铝或铜。
本发明实施例通过将部分栅极层进行阳极氧化，使氧化后的部分栅极层覆盖栅绝缘层凸部，形成补偿层，补偿栅绝缘层与栅极层存在的长度差。从而消除层间电介质层与源漏极层交叠处的褶皱，改善栅极层与源漏极层之间的搭接形貌，有效降低DGS不良，提升产品良率。
此外，由于氧化部分栅极层形成的补偿层为金属氧化物，属于绝缘体，且层间电介质层的材质为氧化硅或氮化硅等绝缘体，补偿层的材质和层间电介质层的材质性能相似，补偿层的存在不会对顶栅结构的特性造成影响。因此，本发明实施例即提升产品良率又不会对顶栅结构的特性造成影响。
第二实施例
基于前述实施例的技术构思，本发明还提供了一种顶栅结构的制备方法，包括：
S1、形成栅绝缘层；
S2、在所述栅绝缘层之上形成栅极层，所述栅极层覆盖部分栅绝缘层，将另一部分栅绝缘层暴露形成栅绝缘层凸部；
S3、在栅极层之上形成覆盖所述栅绝缘层凸部的补偿层。
其中，步骤S2包括：
通过阳极氧化工艺将部分栅极层氧化，使氧化后的部分栅极层向外生长延伸覆盖栅绝缘层凸部，形成补偿层，以补偿栅绝缘层与栅极层存在的长度差。
第三实施例
基于前述实施例的技术构思，本发明还提供了一种阵列基板，包括第一实施例的顶栅结构。该阵列基板通过在栅极层之上形成补偿层，补偿栅绝缘层与栅极层存在的长度差，即使补偿层将栅绝缘层凸部覆盖，从而消除层间电介质层与源漏极层交叠处的褶皱，改善栅极层与源漏极层之间的搭接形貌，有效降低DGS(Data Gate Short，栅线和数据线短接)不良，提升产品良率。
第四实施例
基于前述实施例的技术构思，本发明还提供了一种显示设备，包括第三实施例的阵列基板。本发明实施例的显示设备可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。本发明实施例的显示设备能够有效降低DGS不良，提升产品良率。
在本发明实施例的描述中，需要理解的是，术语“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。
在本发明实施例的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本发明中的具体含义。
虽然本发明所揭露的实施方式如上，但所述的内容仅为便于理解本发明而采用的实施方式，并非用以限定本发明。任何本发明所属领域内的技术人员，在不脱离本发明所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本发明的专利保护范围，仍须以所附的权利要求书所界定的范围为准。
Claims (7)
1.一种顶栅结构的薄膜晶体管，包括有源层，位于所述有源层上的栅绝缘层以及形成于所述栅绝缘层之上的栅极层，所述栅极层覆盖部分栅绝缘层，将另一部分栅绝缘层暴露在所述栅极层的侧边形成栅绝缘层凸部，其特征在于，还包括形成于所述栅极层之上的补偿层，所述补偿层是在形成所述栅绝缘层和所述栅极层之后对所述栅极层的表面进行氧化处理，使得所述栅极层在氧化过程中向外生长并覆盖所述栅绝缘层凸部；还包括位于所述栅极层上方的层间电介质层以及位于所述层间电介质层上的源漏极层，所述源漏极层位于所述层间电介质层覆盖所述栅极层和所述栅绝缘层的区域。
2.根据权利要求1所述的顶栅结构的薄膜晶体管，其特征在于，所述补偿层的材质为金属氧化物。
3.根据权利要求1所述的顶栅结构的薄膜晶体管，其特征在于，所述栅极层的材质为金属。
4.根据权利要求1所述的顶栅结构的薄膜晶体管，其特征在于，所述补偿层的厚度为0.1um-1um。
5.一种阵列基板，其特征在于，包括如权利要求1～4任一所述的顶栅结构的薄膜晶体管。
6.一种显示设备，其特征在于，包括如权利要求5所述的阵列基板。
7.一种顶栅结构的薄膜晶体管的制备方法，其特征在于，包括：
在基底上形成有源层，在所述有源层之上形成覆盖所述有源层的栅绝缘层；
在所述栅绝缘层之上形成栅极层，所述栅极层覆盖部分栅绝缘层，将另一部分栅绝缘层暴露在所述栅极层的侧边形成栅绝缘层凸部；
通过阳极氧化工艺将部分栅极层氧化，使氧化后的部分栅极层向外延伸覆盖所述栅绝缘层凸部，形成补偿层；
在所述补偿层上形成层间电介质层；
在所述层间电介质层上形成源漏极层，所述源漏极层位于所述层间电介质层覆盖所述栅极层和所述栅绝缘层的区域。
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910527753.0A CN110223990B (zh) | 2019-06-18 | 2019-06-18 | 顶栅结构及其制备方法、阵列基板、显示设备 |
| PCT/CN2020/074429 WO2020253246A1 (zh) | 2019-06-18 | 2020-02-06 | 顶栅结构及其制备方法、阵列基板、显示设备 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910527753.0A CN110223990B (zh) | 2019-06-18 | 2019-06-18 | 顶栅结构及其制备方法、阵列基板、显示设备 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110223990A CN110223990A (zh) | 2019-09-10 |
| CN110223990B true CN110223990B (zh) | 2022-03-08 |
Family
ID=67817721
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910527753.0A Active CN110223990B (zh) | 2019-06-18 | 2019-06-18 | 顶栅结构及其制备方法、阵列基板、显示设备 |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN110223990B (zh) |
| WO (1) | WO2020253246A1 (zh) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110223990B (zh) * | 2019-06-18 | 2022-03-08 | 京东方科技集团股份有限公司 | 顶栅结构及其制备方法、阵列基板、显示设备 |
| CN112909019B (zh) * | 2021-01-19 | 2023-06-06 | 鄂尔多斯市源盛光电有限责任公司 | 阵列基板、阵列基板的制备方法及显示装置 |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0225426A2 (en) * | 1981-12-16 | 1987-06-16 | THORN EMI North America Inc. | A method of fabricating a MOS transistor on a substrate |
| JPH02159730A (ja) * | 1988-12-14 | 1990-06-19 | Sony Corp | 薄膜トランジスタの形成方法 |
| CN1081022A (zh) * | 1992-03-27 | 1994-01-19 | 株式会社半导体能源研究所 | 一种半导体器件及其制造方法 |
| CN1088315A (zh) * | 1992-11-07 | 1994-06-22 | 株式会社金星社 | 薄膜晶体管液晶显示器用的信号线装置及其制造的方法 |
| CN1121617A (zh) * | 1994-06-02 | 1996-05-01 | 株式会社半导体能源研究所 | 有源矩阵显示器和电光元件 |
| CN1571165A (zh) * | 1993-09-20 | 2005-01-26 | 株式会社半导体能源研究所 | 具有薄膜晶体管的半导体器件 |
| CN1933114A (zh) * | 1993-10-01 | 2007-03-21 | 株式会社半导体能源研究所 | 半导体器件及其制造方法 |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05267666A (ja) * | 1991-08-23 | 1993-10-15 | Semiconductor Energy Lab Co Ltd | 半導体装置とその作製方法 |
| JP3173760B2 (ja) * | 1994-11-11 | 2001-06-04 | 株式会社半導体エネルギー研究所 | 半導体装置の作製方法 |
| JPH114006A (ja) * | 1998-05-07 | 1999-01-06 | Semiconductor Energy Lab Co Ltd | 絶縁ゲイト型電界効果半導体装置の作製方法 |
| KR101675113B1 (ko) * | 2010-01-08 | 2016-11-11 | 삼성전자주식회사 | 트랜지스터 및 그 제조방법 |
| US8936973B1 (en) * | 2013-11-14 | 2015-01-20 | Cbrite Inc. | Anodization of gate with laser vias and cuts |
| CN110223990B (zh) * | 2019-06-18 | 2022-03-08 | 京东方科技集团股份有限公司 | 顶栅结构及其制备方法、阵列基板、显示设备 |
-
2019
- 2019-06-18 CN CN201910527753.0A patent/CN110223990B/zh active Active
-
2020
- 2020-02-06 WO PCT/CN2020/074429 patent/WO2020253246A1/zh active Application Filing
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0225426A2 (en) * | 1981-12-16 | 1987-06-16 | THORN EMI North America Inc. | A method of fabricating a MOS transistor on a substrate |
| JPH02159730A (ja) * | 1988-12-14 | 1990-06-19 | Sony Corp | 薄膜トランジスタの形成方法 |
| CN1081022A (zh) * | 1992-03-27 | 1994-01-19 | 株式会社半导体能源研究所 | 一种半导体器件及其制造方法 |
| CN1088315A (zh) * | 1992-11-07 | 1994-06-22 | 株式会社金星社 | 薄膜晶体管液晶显示器用的信号线装置及其制造的方法 |
| CN1571165A (zh) * | 1993-09-20 | 2005-01-26 | 株式会社半导体能源研究所 | 具有薄膜晶体管的半导体器件 |
| CN1933114A (zh) * | 1993-10-01 | 2007-03-21 | 株式会社半导体能源研究所 | 半导体器件及其制造方法 |
| CN1121617A (zh) * | 1994-06-02 | 1996-05-01 | 株式会社半导体能源研究所 | 有源矩阵显示器和电光元件 |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110223990A (zh) | 2019-09-10 |
| WO2020253246A1 (zh) | 2020-12-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110729313B (zh) | 显示面板、显示面板制备方法、显示装置 | |
| US11462602B2 (en) | Array substrate, manufacturing method thereof, and display device | |
| US11488988B2 (en) | Display backplane and manufacturing method thereof, and display panel | |
| CN110223990B (zh) | 顶栅结构及其制备方法、阵列基板、显示设备 | |
| US11133363B2 (en) | Array substrate and manufacturing method thereof, and display device | |
| US11791414B2 (en) | TFT device, manufacturing method thereof, and array substrate | |
| CN111863839B (zh) | 一种阵列基板、其制备方法及显示面板 | |
| CN210723028U (zh) | 显示面板、显示装置 | |
| WO2024066137A1 (zh) | 阵列基板、显示面板及阵列基板的成型方法 | |
| CN105428367A (zh) | 像素结构及其制造方法 | |
| US11004980B2 (en) | Thin film transistor having vertical channel and manufacturing method therefor, array substrate, display panel and display device | |
| EP3588563A1 (en) | Array substrate and method for manufacturing same | |
| CN104201151A (zh) | 薄膜晶体管阵列基板及其像素暗点化处理方法 | |
| CN104409462A (zh) | 阵列基板及其制造方法、显示装置 | |
| CN110707106A (zh) | 薄膜晶体管及制备方法、显示装置 | |
| JP3137839B2 (ja) | アクティブマトリクス回路 | |
| CN212084945U (zh) | 一种具有双层绝缘层的面板结构 | |
| US11329074B2 (en) | Array substrate, manufacturing method thereof, and display panel | |
| CN114883346A (zh) | 阵列基板及其制作方法、显示面板 | |
| US11488989B2 (en) | Capacitor, array substrate and method for manufacturing the same, and display panel | |
| CN114203787A (zh) | 一种显示面板及其制备方法 | |
| CN111599686A (zh) | 一种具有双层绝缘层的面板结构及制作方法 | |
| US10164028B2 (en) | Thin film transistor, manufacturing method therefor, oxide back plate and display apparatus | |
| CN220491890U (zh) | 显示面板与显示装置 | |
| US20220173125A1 (en) | Array substrate and preparation method thereof, display panel and display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |