CN110176871B

CN110176871B - Gate driver for switching converter to minimize body diode power loss

Info

Publication number: CN110176871B
Application number: CN201910131053.XA
Authority: CN
Inventors: A·V·特斯尔甘诺维奇; L·A·内曼; M·A·萨塔尔; V·特兹卡诺维
Original assignee: IXYS LLC
Current assignee: IXYS LLC
Priority date: 2018-02-21
Filing date: 2019-02-21
Publication date: 2021-06-11
Anticipated expiration: 2039-02-21
Also published as: EP3570440A1; TW201937837A; US20190260281A1; EP4057509B1; KR20200145797A; CN110176871A; EP4057509A1; EP3570440B1; JP6855522B2; CN113315403A; KR102195552B1; JP7039744B2; TWI748662B; US10439483B2; CN113315403B; TWI709293B; JP2022001009A; KR102467987B1; TW202118208A; KR20190100861A

Abstract

The present disclosure relates to a gate driver for a switching converter that minimizes body diode power loss. In a switching converter with an inductive load, current may flow through the body diode of the transistor even if the gate of the transistor is controlled to keep the transistor off. Then, when the other transistor of the switching leg is turned on, a reverse recovery current flows in a reverse direction through the body diode. To reduce switching losses associated with such currents, the gate driver integrated circuit detects when the current flowing through the body diode rises above a threshold current. Then, the gate driver integrated circuit controls the transistor to turn on. Then, when turning on the further transistor of the switching leg, the gate driver first turns off the transistor. When the gate-source voltage of the off transistor drops below the threshold voltage, then the gate driver integrated circuit allows and controls the other transistor to turn on.

Description

Gate driver for switching converter to minimize body diode power loss

Technical Field

The described embodiments relate to a gate driver for driving a gate of a power transistor, such as a power field effect transistor (so-called MOSFET).

Background

Switching power converters have several types of power losses. To illustrate this, a specific type of switching converter is briefly described herein. It is a DC-AC switching converter commonly referred to as an "inverter". The inverter receives the DC supply voltage and outputs a sinusoidal AC voltage or current. Various circuit topologies for inverters exist, but fig. 1A illustrates one example of a portion of one exemplary inverter circuit. The inverter circuit involves so-called "high-side" transistors called QHS and so-called "low-side" transistors called QLS. Each of these transistors is an N-channel field effect transistor, sometimes commonly referred to as an N-channel MOSFET (metal oxide semiconductor field effect transistor). Each of these transistors is implemented as part of a semiconductor die. There is an intrinsic body diode as part of that die. The diode may be shown with the symbol of an N-channel transistor, or may not be shown at all, but it is present with the transistor. In the inverter circuit, a first DC supply voltage is present at node N1 and a second, higher DC supply voltage is present at node N2. The node GND is a ground node. Reference symbol L identifies a first winding (primary side winding) of the transformer. The magnetic core of the transformer and the second winding (secondary side winding) of the transformer are not shown. The general purpose of the inverter circuit is to generate an AC current flowing through the first winding L. This causes a similar AC current to flow in the second winding of the transformer and this AC current in the second winding is passed through the load. Control and drive circuitry to control the high-side and low-side transistors is not shown.

In the first half-cycle, in which the output sinusoidal AC current flows in the winding L, the high-side transistor is controlled to be off. This is indicated in fig. 1A, 1B, 1C and 1D by the word "off" appearing next to the high-side transistor QHS. On the other hand, the low-side transistor QLS is turned on and off in such a manner that a sinusoidal AC current flows through the first winding. Then, in the second half period of the sinusoidal AC current, the low-side transistor QLS is controlled to turn off. The operation of the inverter circuit in this latter half period is not shown. In the latter half period of the sinusoidal AC current, the high-side transistor QHS is turned on and off in such a manner that the sinusoidal AC current flows.

Fig. 1A, 1B, 1C, and 1D illustrate current flow during an exemplary first half-cycle of a sinusoidal AC current. Fig. 1A illustrates a first case. The low-side transistor QLS is controlled to be on. Causing current to flow as indicated by arrow a. Current flows from node N1 through winding L, through transistor QLS, and to ground node GND. After a period of time, the low-side transistor QLS is turned off. This creates the situation shown in FIG. 1B. Since the current in the inductance of the first winding L cannot be stopped instantaneously and because it cannot flow through the blocked low-side transistor QLS either, it flows in the path shown by the arrow B. The high-side transistor QHS is turned off, but current B flows through the body diode DHS until the node N2. After a certain time, the low-side transistor QLS is turned on again. Then, a current flows as indicated by an arrow C in fig. 1C. The low-side transistor QLS is turned on and conducting so current flows from node N1 through winding L, through the low-side transistor QLS, and to ground node GND. However, when the low-side transistor QLS is turned on for the first time, a reverse voltage is applied to the body diode DHS of the high-side transistor. This causes a short burst of reverse recovery current to flow through the body diode DHS. This burst of reverse recovery current flows in path C shown in fig. 1C. Once this reverse recovery current has stopped, current flows as shown in fig. 1D.

The current flowing through the body diode DHS may cause power losses in the switching converter. The surge of reverse recovery current shown in fig. 1C is a large current, although of relatively short duration, and occurs during the time when a large reverse voltage is present across the body diode. The energy loss is represented by the instantaneous current flowing through the body diode DHS multiplied by the integral over time of the instantaneous voltage drop across the body diode DHS. This is due to the energy loss caused by the flow of the reverse recovery current. In addition, there is an energy loss because a forward current flows through the body diode DHS. When the current B shown in fig. 1B flows through the body diode DHS, there is a voltage drop of about 1 volt across the body diode DHS. The energy loss is represented by the instantaneous current flowing through the body diode DHS multiplied by the integral of the instantaneous voltage drop across the body diode DHS.

Disclosure of Invention

In a first novel aspect, a gate driver integrated circuit has a high side gate driver and a low side gate driver. The gate driver integrated circuit controls a high side N-channel field effect transistor and a low side N-channel field effect transistor of the DC-AC inverter circuit. The high-side transistor and the low-side transistor are part of a switching or phase leg circuit. The source of the high-side transistor is coupled to the drain of the low-side transistor at a central switch node SW. One end of the large inductor or transformer winding is also coupled to the central switch node SW.

The gate driver integrated circuit has a VHSC1 input terminal that receives the high side driver digital control signal on that terminal. When this VHSC1 input signal is driven to a high digital logic level, the high side transistor will turn on. The gate driver integrated circuit also has a VLSC1 input terminal that receives the low side driver digital control signal on this terminal. When this VLSC1 input signal is driven to a high digital logic level, the low side transistor will turn on. The VHSC1 and VLSC1 input signals are digital logic signals that are typically supplied by a microcontroller integrated circuit to the VHSC1 and VLSC1 input terminals of the gate driver integrated circuit, respectively.

This current condition is detected when one of the transistors is controlled by the microcontroller to be off and non-conductive, but when current flows through the body diode of the transistor due to an inductive load. The driver integrated circuit controls the transistor to turn on if the current through the body diode is detected to exceed a predetermined current threshold. The transistor is turned on by the gate driver integrated circuit even if the input digital control signal received from the microcontroller indicates that the microcontroller wishes the transistor to be turned off. Otherwise the current through the body diode flows through the parallel connected conducting transistors. Then, when the other transistor of the switching branch is controlled by the microcontroller to be turned on, the gate driver integrated circuit detects this and first takes action to turn off the turned-on transistor. The gate driver integrated circuit monitors the gate-source voltage of the transistor being turned off. When the gate driver integrated circuit detects that the gate-source voltage of the transistor has dropped below a predetermined threshold voltage, then the gate driver integrated circuit controls the other transistor of the switching branch to switch on and become conductive. In this way, a through-current is avoided that might otherwise flow in the current path through the conductive high-side transistor and then through the conductive low-side transistor. Monitoring the gate-source voltage of the transistor that is turned off allows optimizing the turn-on timing of the other transistor.

By turning on the transistor during the time that current would otherwise flow through its body diode, power loss in the body diode is reduced. Otherwise the magnitude of the reverse recovery current that occurs when the subsequent diode commutates is reduced. Also, the forward conduction losses through the diode are reduced because some of the forward current that would otherwise flow through the body diode with a larger voltage drop will flow through the conducting transistor with a smaller voltage drop due to the parallel coupled conducting transistors. Both effects (i.e. shunting of some forward current across a small voltage drop of the pass transistor and reduction of the magnitude of the reverse recovery current in the body diode) act to reduce losses in the body diode.

If the body diode of the high-side transistor conducts current due to the manner in which the high-side and low-side transistors are controlled, the novel gate driver integrated circuit controls the high-side transistor to turn on and conduct during these times. The gate driver integrated circuit operates to reduce losses in the body diode of the high-side transistor. On the other hand, if the body diode of the low-side transistor conducts current due to the manner in which the high-side and low-side transistors are controlled, the novel gate driver integrated circuit controls the low-side transistor to turn on and conduct during these times. The gate driver integrated circuit operates to reduce losses in the body diode of the low-side transistor.

In another novel aspect, the gate driver integrated circuit has only one gate driver circuit. The gate driver circuit is used to drive a power field effect transistor that is part of another semiconductor die. The body diode of the power field effect transistor is also part of another semiconductor die. The gate driver integrated circuit includes a driver digital control signal input terminal, a driver output terminal, a gate driver circuit, body diode current monitoring means, and means for turning off the power field effect transistor. The gate driver circuit outputs a gate driver output signal to the driver output terminal and drives the gate of the power field effect transistor in such a way as to turn on the power field effect transistor if a digital signal of a predetermined digital logic value is present on the driver digital control signal input terminal. The body diode current monitoring means is for determining when the current flowing through the body diode rises above a predetermined threshold current during the gate driver circuit controlling the power field effect transistor to turn off, and for causing the power field effect transistor to turn on in response to the determination such that the power field effect transistor turns on even if there is no digital signal of a predetermined digital logic value on the driver digital control signal input terminal. The means for turning off the power field effect transistor is for turning off the power field effect transistor in response to a transition of the second digital control signal. The transition of the second digital control signal occurs during a time when the power field effect transistor is on but the digital signal on the driver digital control signal input terminal is not a predetermined digital logic value. For example, the second digital control signal may be a digital control signal for controlling another external discrete power field effect transistor device. For example, the second digital control signal may be received onto the gate driver integrated circuit through a dedicated input terminal.

Further details and embodiments, as well as methods and techniques, are described in the detailed description below. This summary is not intended to be limiting of the invention. The invention is defined by the claims.

Drawings

The figures illustrate embodiments of the invention in which like numerals represent like parts.

Fig. 1A (prior art) is a diagram illustrating current flow in a DC-AC inverter circuit when a low-side transistor is turned on and conducting.

Fig. 1B (prior art) is a diagram illustrating current flow in the DC-AC inverter circuit of fig. 1A when the low-side transistor is off.

Fig. 1C (prior art) is a diagram illustrating current flow in the inverter circuit of fig. 1A when the low-side transistor is turned on again.

Fig. 1D (prior art) is a graph illustrating current flow in the inverter circuit of fig. 1A at a time after reverse recovery current flow in the body diode of the high-side transistor subsides.

Figure 2 is a diagram of a switching DC-AC inverter circuit including a novel driver integrated circuit, in accordance with one novel aspect.

Fig. 3 is a block diagram of a low side driver logic circuit of the driver integrated circuit of fig. 2.

Fig. 4 is a block diagram of a high-side driver logic circuit of the driver integrated circuit of fig. 2.

Fig. 5 is a waveform diagram illustrating an operation of the DC-AC inverter circuit of fig. 2.

Fig. 6 is a simplified waveform diagram illustrating in more detail the time period between time T2 and time T6 of fig. 5. The waveform diagram is a simplification. To understand the waveform more accurately, the circuit should be fabricated and then the actual signal in the actual circuit monitored and checked with test equipment.

Fig. 7 is a flow chart of method 100 in which the high-side transistor QHS is turned on to shunt current around the body diode D1 of the high-side transistor QHS and reduce losses due to reverse recovery current flowing through the body diode D1.

Fig. 8 is a flow chart of a method 200 in which the low-side transistor QLS is turned on to shunt current around the body diode D2 of the low-side transistor QLS and reduce losses due to reverse recovery current flowing through the body diode D2.

Fig. 9 is a diagram illustrating a serial digital interface through which the driver integrated circuit 3 receives a multi-bit digital control value from the microcontroller, wherein the multi-bit digital control value controls a threshold voltage (e.g., threshold voltage 62) and a threshold current (e.g., threshold current 61).

Detailed Description

Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings. The terms "digital logic level" and "digital logic value" are used interchangeably in this patent document.

Figure 2 is a diagram of DC-AC inverter circuitry 1 in accordance with one novel aspect. The DC-AC inverter system 1 includes a microcontroller integrated circuit 2, a driver integrated circuit 3, a low-side transistor device 4, a high-side transistor device 5, a transformer including a first winding 6 and a second winding 7, a first voltage source 8, a second voltage source 9, a high-side current sense resistor 10, a current-limiting gate resistor 11 for the high-side transistor device, a low-side current sense resistor 12, and a current-limiting gate resistor 13 for the low-side transistor device.

The low side transistor device 4 and the high side transistor device 5 are the same device. In one example, these devices are examples of MMXT 132N5OP3 devices available from IXYS Corporation of 1590Buckeye Drive, Milpitas, California. The low-side transistor device 4 includes a low-side N-channel field effect transistor QLS14 and a smaller current sensing N-channel field effect transistor QLSs 15. Reference numeral 16 identifies the body diode D2 of the low side transistor 14. Reference numeral 17 identifies the body diode D2S of the current sense transistor 15. The gates of

transistors

14 and 15 are coupled together. The drains of

transistors

14 and 15 are coupled together. The current sense transistor 15 is much smaller than the main transistor 14. The current sense transistor 15 is provided on the same semiconductor die as the primary low side transistor such that the current flowing through the current sense transistor 15 will be proportional to the current flowing through the primary low side transistor 14.

The high-side transistor device 5 includes a high-side N-channel field effect transistor 18 and a smaller current sensing N-channel field effect transistor 19. Reference numeral 20 identifies the body diode D1 of the high-side transistor 18. Reference numeral 21 identifies the body diode D1S of the current sense transistor 19. The gates of transistors 18 and 19 are coupled together. The drains of transistors 18 and 19 are coupled together.

The first voltage source 8 provides a +200DC voltage on node 22. This +200V is relative to the ground potential at ground node GND 23. The first voltage source 8 may for example be a stack of batteries or another voltage source with large capacitors coupled in parallel. The second voltage source 9 provides a +200DC voltage on node 24. This +200V is relative to the +200V potential on node 22. Thus, a DC potential of +400V exists on node 24 relative to ground potential on ground node GND 23. The second voltage source 9 may for example be a stack of batteries or another voltage source with large capacitors coupled in parallel.

The drain of high-side transistor 18 is coupled to node 24. The source of the high-side transistor 18 is coupled to the drain of the low-side transistor 14 at the SW node 25. The source of the low-side transistor 14 is coupled to the ground node GND 23. First end 6A of winding 6 is coupled to switch node SW25 and is part of switch node SW 25. A second end 6B of winding 6 is coupled to node 22 and is part of node 22.

The driver integrated circuit 3 includes a low side gate driver logic circuit 26, a high side gate driver logic circuit 27, a low side gate driver circuit 28, a high side gate driver circuit 29, a high side current sense comparator 32, a high side voltage sense comparator 33, a low side current sense comparator 30, a low side voltage sense comparator 31, voltage reference circuits 34-37, level shifting circuits 38-40, a VLSC1 low side driver digital control signal input terminal 41, VHSC1 high side driver digital control signal input terminal 42, ground terminal 43, low side current sense input terminal 44, low side driver output terminal 45, low side voltage sense input terminal 46, low side driver supply voltage terminal 47, SW node terminal 48, high side current sense input terminal 49, high side driver output terminal 50, high side voltage sense input terminal 51, and high side driver supply voltage terminal 52. These terminals are package terminals of a semiconductor device package containing the circuitry of the driver integrated circuit 3. For each package terminal, there is an associated integrated circuit die terminal (e.g., bond pad). The terminal symbols in fig. 2 represent the package terminals and their associated integrated circuit die terminals.

In operation, the driver circuit integrated circuit 3 receives a digital low-side control signal VLSC1 from the microcontroller 2. When this VLSC1 low side driver control signal has a low digital logic level, then the microcontroller 2 controls the low side gate driver circuit 28 to drive a positive voltage onto the gate of the low side transistor QLS14, causing the low side transistor QLS14 to turn on and conduct. Likewise, driver integrated circuit 3 receives a digital high side control signal VHSC1 from microcontroller 2. When this VHSC1 control signal has a high digital logic level, then the microcontroller 2 controls the high-side gate driver circuit 29 to drive a positive voltage onto the gate of the low-side transistor QHS18, causing the high-side transistor QHS18 to turn on and conduct.

When this VLSC1 low-side driver digital control signal received from the microcontroller 2 has a low digital logic level, it may be assumed that the driver integrated circuit 3 will always control the low-side gate driver circuit 28 to drive a low voltage onto the gate of the low-side transistor QLS14, such that the low-side transistor QLS14 is off and non-conductive, but this is not always true in accordance with the present invention. As explained in further detail below, the driver integrated circuit 3 detects whether there is a forward current flowing through the body diode 16 of the low-side transistor 14 and in that condition drives a high voltage onto the gate of the low-side transistor QLS14, causing the low-side transistor QLS14 to turn on. Thus, the low side transistor QLS14 is turned on even if the VLSC1 low side driver digital control signal received from the microcontroller 2 is at a low digital logic level. The turning on of the low-side transistor QLS14 shunts current around the body diode 16 and reduces the voltage drop that would otherwise be across the body diode 16 during this period, thereby reducing power consumption in the body diode 16. If the body diode 16 is then rapidly commutated, then the low-side transistor QLS14 is turned on, which also helps to reduce the magnitude of the reverse recovery current. However, the low-side transistor QLS14 is controlled so that it is not turned on and turned on during the time that the high-side transistor QHS18 is controlled to be turned on and turned on.

Similarly, when the VLHC1 high-side driver digital control signal received from the microcontroller 2 has a low digital logic level, it may be assumed that the driver integrated circuit 3 will always control the high-side gate driver circuit 29 to drive a low voltage onto the gate of the high-side transistor QHS18, such that the high-side transistor QHS18 is off and not conductive, but this is not always true in accordance with the present invention. As explained in further detail below, the driver integrated circuit 3 detects whether there is a forward current flowing through the body diode 20 of the high-side transistor 18 and, in that condition, drives a high voltage onto the gate of the high-side transistor QHS18, causing the high-side transistor QHS18 to turn on. Thus, the high-side transistor QHS18 is turned on even if the VHSC1 high-side driver digital control signal received from microcontroller 2 is at a low digital logic level. The turning on of the high-side transistor QHS18 shunts current around the body diode 20 and reduces the voltage drop that would otherwise be across the body diode 20 during this period, thereby reducing power consumption in the body diode 20. If the body diode 20 is then rapidly commutated, then the high-side transistor QHS18 is turned on to also help reduce the magnitude of the reverse recovery current. However, the high-side transistor QHS18 is controlled so that it is not turned on and turned on during the time when the low-side transistor QLS14 is controlled to be turned on and turned on.

Fig. 3 is a block diagram of one example of circuitry of the LS driver logic 26. The LS driver logic 26 includes a delay circuit 80, two falling

edge detection circuits

81 and 82, a rising edge detection circuit 83, two or

gates

84 and 85, and a flip-flop 86. The rising edge and falling edge detection circuits are one-shot circuits.

Fig. 4 is a block diagram of one example of circuitry for HS driver logic 27. HS driver logic 27 includes a delay circuit 90, a falling edge detection circuit 91, two rising

edge detection circuits

92 and 93, two or

gates

94 and 95, and a flip-flop 96. The rising edge and falling edge detection circuits are one-shot circuits.

Fig. 5 is a waveform diagram illustrating an operation of the DC-AC inverter circuit of fig. 2. The top waveform 55 represents the desired sinusoidal AC current driven through the winding 6 by the DC-AC inverter circuit. The winding current is also referred to as the inductor current and is denoted as IL. A second waveform VLSC 156 represents the VLSC1 low side driver digital control signal received by driver integrated circuit 3 at terminal VLSC 141. Third waveform VHSC 157 represents the VHSC1 digital control signal received by driver integrated circuit 3 on terminal VHSC 142. The bottom waveform 58 represents the actual AC current driven through the winding 6 by the DC-AC inverter circuit. The actual inductor current IL does not have a perfect sinusoidal waveform, but it approximates a sinusoidal waveform. During the first half cycle 59 of the inductor current sine wave, the VLSC1 low side driver control signal transitions up and down under the control of microcontroller 2, but the VHSC1 control signal remains at a digital logic low level. Note that when the VLSC1 low side driver control signal is at a digital logic high level, then the magnitude of the inductor current IL in the bottom waveform rises. Note that when the VLSC1 low side driver control signal is at a digital logic low level, then the magnitude of the inductor current IL in the bottom waveform drops. The timing and duty cycle of the pulses of the VLSC1 low-side driver control signal are such that the inductor current generated in bottom waveform 58 approximates an ideal sine wave shape.

During the second half 60 of the inductor current sine wave, the VHSC1 control signal transitions up and down under the control of microcontroller 2, but the VLSC1 low side driver control signal remains at a digital logic low level. Note that when VHSC1 control signal is at a digital logic high level, then the magnitude of inductor current IL in the bottom waveform drops. Note that when VHSC1 control signal is at a digital logic low level, then the magnitude of inductor current IL in the bottom waveform rises. VHSC1 controls the timing and duty cycle of the pulses of the signal so that the resulting inductor current has a desired sinusoidal shape.

FIG. 6 shows the time period between time T1 and time T6 in more detail. The upper two waveforms of fig. 6 represent digital control signals VHSC1 and VLSC1 received by driver integrated circuit 3 from microcontroller 2. Because the time period between T1 and T6 occurs during the first half-cycle 59 of the output inductor current IL, the microcontroller 2 maintains the high-side control signal VHSC1 at a digital logic low level. The fourth waveform labeled VLSC2 is the voltage signal output by the low side driver logic circuit 26 onto the input lead of the low side gate driver circuit 28. When the low-side driver digital control signal VLSC1 is at the high digital logic level between times T2 and T3, the low-side gate driver circuit 28 drives a 12-volt VGs voltage onto the gate of the low-side transistor QLS 14. Therefore, the low-side transistor QLS14 is turned on and turned on. Accordingly, the inductor current IL rises between times T2 and T3, as shown by the fifth waveform labeled "inductor current (IL)". However, at time T3, microcontroller 2 transitions the VLSC1 low-side driver control signal to a digital logic low level. This falling edge is detected by a falling edge detector 82 in the LS driver logic 26. The detection of the falling edge is indicated in fig. 6 by the arrow labeled with a circled "1". The pulse shown in the third waveform illustrates the signal FED82 output by this falling edge detector 82. As a result of this detection, the low side driver logic 26 outputs a digital logic low signal VLSC2 to the low side gate driver circuit 28. The low side gate driver circuit 28 in turn drives the gate voltage VGs on the low side transistor QLS14 to zero volts. This is indicated in fig. 6 by the arrow labeled "2" with a circle. When the voltage on the gate of the low-side transistor QLS14 is driven low, the low-side transistor QLS14 is turned off. This is indicated in fig. 6 by the arrow labeled "3" with a circle. The current IQLS through the low-side transistor QLS, represented by the sixth waveform, drops to zero. However, the current IL flowing through the large inductance of the transformer winding 6 cannot be stopped immediately, so the current IL is diverted from the SW node 25 up to the high-side transistor device 5. The high-side transistor QHS18 is off at this time, so current flows through the body diode D120 and to the node 24. This sudden increase in current IQHS flowing from the SW node 25 up to the high-side transistor device 5 is indicated in fig. 6 by the arrow marked with a circled "4". The current rise at time T3 is shown in the waveform labeled IQHS. When this current IQHS exceeds the predetermined threshold current 61, then the comparator 32 outputs a digital logic high signal. This signal is the signal icophs after level shifting by the level shift circuit 38. The rising edge of signal icophs is detected by rising edge detector 93 in high side driver logic 27. This is indicated in fig. 6 by the arrow labeled "5" with a circle. The rising edge detector 93 detects the rising edge of the signal icophs and outputs a high pulse of the signal RED 93. Signal RED93 is supplied onto the set input lead of flip-flop 96 so that flip-flop 96 in high side driver logic 27 is set and high side driver logic circuit 27 asserts its output signal VHSC2 to a high digital logic level. This is indicated in fig. 6 by the arrow labeled "6" with a circle. The high-side gate driver circuit 29, in turn, drives a 12 volt gate Voltage (VGs) onto the gate of the high-side transistor QHS 18. This is indicated in fig. 6 by the arrow labeled "7" with a circle. The 12 volt VGs voltage on the gate of the high side transistor 18 (relative to the voltage on the SW node) causes the high side transistor QHS18 to turn on. This is indicated in fig. 6 by the arrow labeled with the circled "8". The high-side transistor QHS18 conducts current as indicated by the iqhs (nfet) waveform. This current reduces the magnitude of the current flowing through body DIODE D120 as shown by the bottom waveform labeled IQHS (DIODE). It is noted that as the current IQHS (nfet) increases, the current IQHS (diode) decreases in a corresponding manner. The high-side transistor QHS18 is controlled to be on and conductive even if the incoming digital control signal VHSC1 on terminal 42 is at a digital logic low level.

This condition continues until microcontroller 2 asserts the low side driver digital control signal VLSC1 to a digital logic high level at time T4. The driver integrated circuit 3 detects the rising edge of the low side driver digital control signal VLSC1 but does not immediately control the low side transistor QLS14 transition. More precisely, it first controls the high-side transistor QHS18 to turn off. First, the rising edge detector 92 in the high side driver logic 27 detects the rising edge of the VLSC1 low side driver control signal. This is indicated in fig. 6 by the arrow labeled "9" with a circle. The pulse shown in the seventh waveform RED92 of fig. 6 represents the pulse output by this rising edge detector 92. In response, high side driver logic 27 forces the VHSC2 control signal to a digital logic low level. This is indicated in fig. 6 by the arrow labeled "10" with a circle. This causes the voltage on the gate of the high-side transistor 18 to decrease. This is indicated in fig. 6 by the arrow labeled "11" with a circle. The voltage signal VGHS at the gate of the high-side transistor 18 decreases at a rate determined by the resistance of the resistor 11 and the gate-source capacitance of the high-side transistor device 5. Due to the resistor 11 and the gate capacitance of the high-side transistor, the voltage of the signal VHSGDOS on terminal 50 is different from the voltage of the signal VGHS on the gate of the high-side transistor QHS 18. When the voltage of the signal VGHS on the gate of the high-side transistor QHS18 decreases, the current flowing through the high-side transistor QHS18 decreases. This is indicated in fig. 6 by the arrow labeled "12" with a circle. When the voltage VGHS on the gate of the high-side transistor QHS18 falls below the predetermined threshold voltage 62, then the comparator 33 asserts its output signal to a high digital logic level. After level shifting, this signal is the digital signal VCOMPHS. This low-to-high signal transition of the digital signal VCOMPHS causes the flip-flop 86 to be clocked at a digital high value. Thus, control signal VLSC2 transitions to a high digital logic value. This is indicated in fig. 6 by the arrow labeled "13" with a circle. This turns on the low-side transistor QLS14 and redirects the inductor current IL from the SW node 25 down through the low-side transistor QLS14 to the ground node GND 23. This is indicated in fig. 6 by the arrow labeled "14" with a circle. From time T5 to time T6, the current flowing through the low-side transistor QLS14 increases, as shown by the waveform labeled IQLS in fig. 6.

Thus, when the low-side transistor QLS14 is first controlled to turn off during the first half-cycle 59, a rapid increase in the current flowing through the body diode D120 of the high-side transistor is detected. This detection is used as a trigger to turn on the high-side transistor QHS 18. Otherwise the current through the body diode D120 passes through the high-side transistor QHS 18. This reduces power losses that would otherwise occur in the body diode D120. The high-side transistor QHS18 continues to be controlled to turn on and conduct until the driver integrated circuit 3 receives a rising edge of the VLSC1 low-side driver digital control signal from the microcontroller 2. In response to this rising edge of the VLSC1 low-side driver digital control signal received from the microcontroller 2, the driver integrated circuit 3 first controls the high-side transistor QHS18 to turn off. When the gate-source voltage of the high-side transistor QHS18 drops below the threshold voltage, then the driver integrated circuit 3 can turn on the low-side transistor QLS14 without causing a breakdown problem. Thus, in response to detecting that the VGs gate voltage on the high-side transistor QHS18 has fallen below the threshold voltage, the driver integrated circuit 3 controls the low-side transistor QLS14 to turn on. Thereafter, the low-side transistor QLS14 is controlled to remain on and conductive as long as the VLSC1 low-side driver digital control signal received from microcontroller 2 continues to be high at the digital logic high value.

Fig. 7 is a flow chart of the method 100 set forth in the waveform diagram of fig. 6. This method 100 involves operation of the driver integrated circuit 3 during the first half cycle 59 of the sinusoidal AC output current IL. Initially, at a time such as time T3 in fig. 6, the low-side transistor QLS14 is turned on. The VHSC1 high side driver digital control signal is at a digital logic low level and remains at this level throughout method 100 of fig. 7. Microcontroller 2 then de-asserts the low-side driver control signal VLSC1 to a digital logic low level. This causes the low-side transistor QLS14 to turn off and redirect the flow of the inductor current IL from the SW node 25 up to the high-side transistor device 5. Therefore, the current IQHS increases. When the current IQHS exceeds the threshold current as detected by the comparator 32 (step 101), the driver integrated circuit 3 controls the high-side transistor QHS18 to turn on (step 102). In the example of fig. 2, this detection is done indirectly by detecting whether the current flowing through sense body diode D1S 21 exceeds a threshold current. The high-side transistor QHS is controlled to be on by the driver integrated circuit 3 even if the microcontroller 2 holds the VHSC1 signal at a digital logic low level. The driver integrated circuit 3 continues to control the high-side transistor QHS18 to remain on and conductive as long as the microcontroller 2 continues to control the low-side transistor QLS14 to remain off. This shunts current around the body diode D120. The shunt current flows through the high-side transistor QHS. When the microcontroller 2 then asserts the VLSC1 low-side driver digital control signal to a digital logic high level when the low-side transistor QLS14 is turned on (step 103), then the driver integrated circuit 3 first controls the high-side transistor QHS18 to turn off (step 104). When it is detected by comparator 33 that the voltage VGs on the gate of high-side transistor QHS18 has dropped below the threshold voltage (step 105), driver integrated circuit 3 asserts a "low-side gate driver output signal" (vlsgos) onto terminal 45. This turns on the low-side transistor QLS14 (step 106). As long as the microcontroller 2 continues to assert the VLSC1 low-side driver control signal to a digital logic high level, the driver integrated circuit 3 continues to drive the high gate-source voltage signal VGLS onto the gate of the low-side transistor QLS 14. When microcontroller 2 then deasserts the VLSC1 low side driver control signal to a digital logic low level (step 107), driver integrated circuit 3 controls low side transistor QLS14 to turn off (step 108), and steps 101 through 108 repeat.

In addition to reducing power losses during the first half cycle 59 of fig. 5, the driver integrated circuit 3 also operates in a similar manner to reduce losses during the second half cycle 60 of fig. 5. During the trailing half cycle 60, the microcontroller 2 holds the VLSC1 low side driver digital control signal at a fixed digital logic low level. However, microcontroller 2 pulses the VHSC1 digital control signal so that inductor current IL has the sinusoidal waveform shown in fig. 5. During this second half period 60, the high-side transistor QHS18 is turned on under the control of the microcontroller 2 to drive the current IL through the winding 6. This pulse of current is in the opposite direction of the arrow denoted IL in fig. 2, and the pulse of current is therefore considered a negative IL current. Thus, the IL waveform appearing in the second half cycle 60 of fig. 5 involves the inductor current IL being negative. After this negative IL current pulse through the high-side transistor QHS18, the high-side transistor QHS18 turns off. This causes the flow of negative current to be redirected. It is redirected such that it flows from ground node GND23 up through the body diode D216 of the low-side transistor QLS14, to SW node 25, and then through the winding 6 of the transformer to node 22. In one novel aspect, the driver integrated circuit 3 controls the low-side transistor QLS14 to be turned on during this time. Thus, some current that would otherwise flow through the body diode D216 flows through the turned-on low-side transistor QLS 14. Then when the microcontroller 2 asserts the VHSC1 digital control signal to turn on the high-side transistor QHS18, the driver integrated circuit 3 does not immediately drive the 12-volt VGs signal onto the gate of the high-side transistor QHS18, but the low-side driver logic 26 first turns off the low-side transistor QLS 14. The driver integrated circuit 3 monitors the gate voltage signal vgls (vgs) on the gate of the low-side transistor QLS 14. When it is detected that the gate voltage VGs on the gate of the low side transistor QLS14 has dropped below the voltage threshold 62, then the high side driver logic 27 controls the high side transistor QHS18 to turn on.

The flow chart of fig. 7 addresses the condition where microcontroller 2 holds the VHSC1 signal at a digital logic low. If microcontroller 2 asserts the VHSC1 signal to a digital logic high, the low-to-high transition will pass through delay element 90 of high-side driver logic 27 and will pass through OR gate 95, and will clock flip-flop 96. Since a digital "1" is present at the D input of flip-flop 96, flip-flop 96 will be clocked at a digital logic high level and the VHSC2 signal will be asserted as a digital logic high level. This will pass through the high side driver 29 and will pass from the driver integrated circuit 3 and will turn on the high side transistor QHS. In the case where the low-side transistor QLS is controlled by the driver integrated circuit 3 to be on (to shunt current around its body diode D2, although VLSC1 is low), the delay in turning on the high-side transistor QHS provides time for the low-side transistor QLS to turn off, as described above. In one embodiment, the driver integrated circuit 3 allows the high-side transistor QHS to turn on only when VGS on the low-side transistor QLS is below a threshold voltage.

Fig. 8 is a flow chart of a method 200 of operation of the driver integrated circuit 3 in a condition where the microcontroller turns on and off the high-side transistor but keeps the VLSC1 low. Initially, the microcontroller 2 controls the high-side transistor QHS18 to turn on and conduct. The VLSC1 low side driver digital control signal is at a digital logic low level and remains at this level throughout the method 200 of fig. 8. Microcontroller 2 then de-asserts digital control signal VHSC1 to a digital logic low level. In response to this, the driver integrated circuit 3 controls the high-side transistor QHS18 to turn off. The turning off of the high-side transistor QHS18 causes the flow of the inductor current IL to be redirected. The flow of inductor current passes from ground node GND23 up through the body diode D116 of the low-side transistor QLS14 to SW node 25 and then through winding 6 to node 22. This current flow is opposite to the arrow for the IQLS current, and therefore this current flow is considered a negative IQLC current. When the current IQLS exceeds the threshold current as detected by the comparator 30 (step 201), the driver integrated circuit 3 controls the low-side transistor QLS14 to be turned on (step 202). In the example of fig. 2, this detection is done indirectly by detecting whether the current flowing through the body diode D2S 17 of the sense transistor exceeds a proportional threshold current. The driver integrated circuit 3 continues to control the low-side transistor QLS14 to remain on and conductive as long as the microcontroller 2 continues to control the high-side transistor QHS18 to remain off. This shunts current around the body diode D216. When the microcontroller 2 asserts the VHSC1 high-side driver digital control signal to a digital logic high level that turns on the high-side transistor QHS18 (step 203), the driver integrated circuit 3 first controls the low-side transistor QLS14 to turn off (step 204). When it is detected by comparator 31 that the voltage signal vgls (vgs) on the gate of low-side transistor QLS14 has dropped below the threshold voltage (step 205), then driver integrated circuit 3 asserts a "high-side gate driver output signal" (VHSGDOS) onto terminal 50. This turns on the high-side transistor QHS18 (step 206). As long as microcontroller 2 continues to assert the VHSC1 high-side driver digital control signal to a digital logic high level, driver integrated circuit 3 continues to drive the 12 volt gate-source voltage VGs onto the gate of high-side transistor QHS 18. When microcontroller 2 then de-asserts the VHSC1 high-side driver digital control signal to a digital logic low level, then driver integrated circuit 3 controls high-side transistor QHS18 to turn off (step 208), and steps 201 through 208 repeat.

The flow chart of figure 8 is for a condition where microcontroller 2 holds the VLSC1 signal at a digital logic low. If microcontroller 2 asserts the VLSC1 signal as a digital logic high, the low-to-high transition will pass through delay element 80 of low side driver logic 26 and will pass through or gate 84, and will clock flip-flop 86. Because a digital "1" is present on the D input of flip-flop 86, flip-flop 86 will be clocked at a digital logic high level and the VLSC2 signal will be asserted as a digital logic high level. This will pass through the low side driver 28 and will pass from the driver integrated circuit 3 and will turn on the low side transistor QLS. In the case where the high-side transistor QHS is controlled to turn on by the driver integrated circuit 3 (to shunt current around its body diode D1, although VHSC1 is low), the delay in turning on the low-side transistor QLS provides time for the high-side transistor QHS to turn off, as described above. In one embodiment, the driver integrated circuit 3 only allows the low-side transistor QLS to turn on if VGs on the high-side transistor QHS is below a threshold voltage.

The microcontroller can control the high-side driver and the low-side driver in a complex manner based on many different sensor inputs including the sensed current and the sensed voltage. Thus, it may be considered that a clocked digital microcontroller may perform the functions of the novel driver integrated circuit 3. However, this is not always the case. In one embodiment, the microcontroller controlling the high side driver and the low side driver of the gate driver integrated circuit 3 is clocked at a relatively slow clock rate. Such relatively slow clocking of the microcontroller 3 is desirable for several reasons. Thus, the microcontroller 3 is not able to make the necessary current and/or voltage detections and make decisions based on the detections and control the high-side and low-side drivers to respond as quickly as necessary. Thus, the novel gate driver integrated circuit 3 includes comparators 30-33 and associated circuitry, thereby enabling the driver integrated circuit 3 to detect and respond to detection faster and in the analog domain. The signal propagation indicated by arrows "1" to "8" and arrows "9" to "14" in fig. 6 is not slowed down by having to wait for the clock edges of the digital clock signal. The gate driver integrated circuit 3 does not include any clocked digital processor that fetches and executes instructions.

Fig. 9 illustrates digital interface logic 63 and associated

terminals

64 and 65 of the driver integrated circuit 3 of fig. 2.

Terminals

64 and 65 and digital interface logic 63 are not shown in the simplified diagram of fig. 2. Digital interface logic 63 includes I for receiving serial information from microcontroller 2²A C interface, four multi-bit digital control registers, and four corresponding digital-to-analog converters (DACs). Each of the voltage reference circuits 34-37 is one of these multi-bit control registers and its associated DAC. The multi-bit digital control values stored in the register are supplied to the DAC so that the DAC in turn outputs the desired reference voltage. Microcontroller 2 supplies digital signals in serial fashion onto terminals SDA 64 and SCL 65 to write a multi-bit digital voltage control value into each of the four control registers to control and set each reference voltage output by voltage reference circuits 34-37. Conductor 68 is coupled to the inverting input lead of comparator 33. Conductor 69 is coupled to the non-inverting input lead of comparator 32. Conductor 70 is coupled to the non-inverting input lead of comparator 31. Conductor 71 is coupled to the non-inverting input lead of comparator 30. The vertical dashed line 72 represents the left boundary of the driver integrated circuit 3 in fig. 2. The reference voltages output by the voltage reference circuits 34-37 are thus programmable by the microcontroller 2.

Although certain specific embodiments are described above for instructional purposes, the teachings of this patent document have general applicability and are not limited to the specific embodiments described above. While this novel gate driver is most advantageously disposed on a separate integrated circuit from the microcontroller, the novel gate driver may also be disposed on the same integrated circuit with the microcontroller. Thus, various modifications, adaptations, and combinations of the various features of the described embodiments can be practiced without departing from the scope of the invention as set forth in the claims.

Claims

1. A method involving driving a high-side transistor and a low-side transistor, wherein a source of the high-side transistor is coupled to a drain of the low-side transistor at a node, wherein a drain of the high-side transistor is coupled to a voltage source, wherein a source of the low-side transistor is coupled to ground, wherein a diode is disposed in parallel with the high-side transistor, the method comprising the steps of:

(a) receiving a high side driver digital control signal, wherein the high side driver digital control signal has a first digital logic value;

(b) driving a high-side HS gate signal onto the gate of the high-side transistor in response to receiving the high-side driver digital control signal of the first digital logic value in (a) such that the high-side transistor is controlled to be off;

(c) determining that a current through the diode rises and exceeds a threshold current, wherein the determination of (c) occurs when the high-side driver digital control signal is at a first digital logic value;

(d) in response to the determination of (c), driving an HS gate signal onto the gate of the high-side transistor such that the high-side transistor is turned on;

(e) receiving a low side driver digital control signal, wherein the low side driver digital control signal has a first digital logic value;

(f) detecting a transition of the low side driver digital control signal from a first digital logic value to a second digital logic value, wherein the transition of the low side driver digital control signal from the first digital logic value to the second digital logic value in (f) is after the determination of (c);

(g) in response to the detection of (f), driving an HS gate signal onto the gate of the high-side transistor, such that the high-side transistor is turned off;

(h) determining that the gate-source voltage of the high-side transistor has dropped below a threshold voltage, wherein in (h) the gate-source voltage of the high-side transistor drops below the threshold voltage in response to the driving of the HS gate signal in (g);

(i) in response to the determination of (h), driving a low-side LS gate signal onto the gate of the low-side transistor such that the low-side transistor is controlled to turn on; and

(j) driving an LS gate signal onto the gate of the low-side transistor so that the low-side transistor remains on as long as the low-side driver digital control signal remains at the second digital logic value, wherein the high-side driver digital control signal remains at the first digital logic value and does not transition the digital value to the second digital logic value at any time during steps (c) through (j).

2. The method of claim 1, wherein the high-side transistor is an N-channel field effect transistor, and wherein the diode is a body diode of the N-channel field effect transistor.

3. The method of claim 2, wherein the high-side transistor is disposed on the semiconductor die with a current sense transistor, wherein the current sense transistor has a body diode coupled between a source and a drain of the current sense transistor, wherein a gate of the high-side transistor is coupled to the gate of the current sense transistor, wherein a drain of the high-side transistor is coupled to the drain of the current sense transistor, and wherein the determining of (c) involves detecting a current through the body diode of the current sense transistor during the time that the current sense transistor is controlled to be off.

4. The method of claim 1, wherein the determining of (c) involves determining that a second current exceeds a threshold current, wherein the second current is indicative of a current through a diode.

5. The method of claim 1, wherein steps (a) through (j) are performed by a gate driver integrated circuit, wherein the gate driver integrated circuit does not include any digital processor that fetches and executes instructions, wherein the high side driver digital control signal is received in (a) onto a first package terminal of the gate driver integrated circuit, and wherein the low side driver digital control signal is received in (e) onto a second package terminal of the gate driver integrated circuit.

6. A gate driver integrated circuit comprising:

a high side driver digital control signal input terminal;

a high side driver output terminal;

a high-side gate driver circuit outputting a high-side gate driver output signal to a high-side driver output terminal;

a low side driver digital control signal input terminal;

a low side driver output terminal;

a low side gate driver circuit outputting a low side gate driver output signal to a low side driver output terminal;

a high side current sense input terminal;

a high side voltage sense input terminal;

a low side current sense input terminal;

a low side voltage sense input terminal;

a high-side driver logic circuit that supplies a control signal to the high-side gate driver circuit and receives a high-side driver digital control signal from a high-side driver digital control signal input terminal;

a low side driver logic circuit to supply control signals to the low side gate driver circuit and to receive low side driver digital control signals from the low side driver digital control signal input terminal;

a high side current sense circuit receiving a signal from the high side current sense input terminal and supplying the signal to the high side driver logic circuit;

a high side voltage sense circuit receiving a signal from the high side voltage sense input terminal and supplying the signal to the low side driver logic circuit;

a low side current sense circuit receiving a signal from a low side current sense input terminal and supplying the signal to a low side driver logic circuit; and

a low side voltage sense circuit that receives signals from the low side voltage sense input terminal and supplies signals to the high side driver logic circuit, and wherein the gate driver integrated circuit does not include any digital processor that fetches and executes instructions.

7. The gate driver integrated circuit of claim 6, wherein the high-side current sensing circuit is a high-side current sensing comparator, wherein the high-side voltage sensing circuit is a high-side voltage sensing comparator, wherein the low-side current sensing circuit is a low-side current sensing comparator, and wherein the low-side voltage sensing circuit is a low-side voltage sensing comparator.

8. The gate driver integrated circuit of claim 7, further comprising:

a switch node input terminal;

a first reference voltage circuit supplying a first reference voltage to the high-side voltage sensing comparator, wherein the first reference voltage is relative to a voltage on the switch node input terminal;

a ground node input terminal; and

a second reference voltage circuit to supply a second reference voltage to the low side voltage sense comparator, wherein the second reference voltage is a voltage on the input terminal relative to the ground node.

9. A gate driver integrated circuit adapted to drive a low side gate signal onto a gate of a low side transistor and adapted to drive a high side gate signal onto a gate of a high side transistor, wherein the high side transistor has a body diode, the gate driver integrated circuit comprising:

a high side driver digital control signal input terminal;

a high side driver output terminal;

a low side driver digital control signal input terminal;

a low side driver output terminal;

a low side gate driver circuit outputting a low side gate driver output signal onto a low side driver output terminal;

body diode current monitoring means for determining when the current through the body diode of the high-side transistor rises above a predetermined threshold current during the time that the high-side gate driver circuit controls the high-side transistor to turn off, and for turning the high-side transistor on in response to the determination;

a high side driver logic device for detecting a transition of the low side driver digital control signal on the low side driver digital control signal input terminal during a time when the high side transistor is on, and for causing the high side transistor to turn off in response; and

VGs monitoring means for detecting when the gate-source voltage on the high side transistor falls below a predetermined threshold voltage and in response causing the low side gate driver circuit to turn on the low side transistor.

10. The gate driver integrated circuit of claim 9, wherein the body diode current monitoring device comprises a first comparator, wherein the first comparator outputs a first comparator output signal that is communicated to the high side driver logic device, wherein the VGs monitoring device comprises a second comparator, wherein the second comparator outputs a second comparator output signal that is communicated to the low side driver logic circuit, wherein the high side driver logic device receives the high side driver digital control signal from the high side driver control signal input terminal, and wherein the gate driver integrated circuit does not include any digital processor that fetches and executes instructions.

11. The gate driver integrated circuit of claim 10, wherein the body diode current monitoring device further comprises a current sense input terminal and a reference voltage circuit, wherein the first differential input lead of the first comparator is coupled to the current sense input terminal, and wherein the second differential input lead of the first comparator is coupled to the reference voltage circuit.

12. The gate driver integrated circuit of claim 10, wherein the VGs monitoring device further comprises a voltage sense input terminal and a reference voltage circuit, wherein a first differential input lead of the second comparator is coupled to the voltage sense input terminal, and wherein a second differential input lead of the second comparator is coupled to the reference voltage circuit.

13. The gate driver integrated circuit of claim 9, wherein the VGs monitoring means is for detecting when the gate-source voltage on the high-side transistor falls below a predetermined threshold voltage and such fall in the gate-source voltage is due to the high-side driver logic means turning the high-side transistor off, and wherein the high-side transistor is turned on and on during a time when a digital logic low value is present on the high-side driver digital control signal input terminal just prior to such turning off.

14. The gate driver integrated circuit of claim 9, further comprising:

a serial digital interface circuit through which the gate driver integrated circuit receives a multi-bit digital control value, wherein the multi-bit digital control value sets a predetermined threshold current.

15. The gate driver integrated circuit of claim 9, further comprising:

a serial digital interface circuit through which the gate driver integrated circuit receives a multi-bit digital control value, wherein the multi-bit digital control value sets a predetermined threshold voltage.

16. A gate driver integrated circuit adapted to drive a low side gate signal onto a gate of a low side transistor and adapted to drive a high side gate signal onto a gate of a high side transistor, wherein the high side transistor has a body diode, the gate driver integrated circuit comprising:

a high side driver digital control signal input terminal;

a high side driver output terminal;

a high-side gate driver circuit outputting a high-side gate driver output signal onto the high-side driver output terminal, wherein the high-side gate driver circuit drives the gate of the high-side transistor to turn on the high-side transistor if a digital signal of a predetermined digital logic value is present on the high-side driver digital control signal input terminal;

a low side driver digital control signal input terminal;

a low side driver output terminal;

body diode current monitoring means for determining when the current through the body diode of the high-side transistor rises above a predetermined threshold current during the time that the high-side gate driver circuit controls the high-side transistor to turn off, and for turning on the high-side transistor in response to the determination, so that the high-side transistor turns on even if there is no digital signal of a predetermined digital logic value on the high-side driver digital control signal input terminal; and

means for turning off the high-side transistor such that the high-side transistor and the low-side transistor are not simultaneously turned on and conducting, and wherein the gate driver integrated circuit does not include any digital processor that fetches and executes instructions.

17. The gate driver integrated circuit of claim 16, wherein the means for turning off the high-side transistor detects when a digital signal on the low-side driver digital control signal input terminal transitions a digital logic value and in response turns off the high-side transistor, and wherein the means for turning off the high-side transistor supplies a control signal to the high-side gate driver circuit.

18. The gate driver integrated circuit of claim 17, wherein the body diode current monitoring means comprises a high side current sense input terminal.

19. The gate driver integrated circuit of claim 16, wherein the predetermined digital logic value is a digital logic high value.

20. The gate driver integrated circuit of claim 16, wherein the predetermined digital logic value is a digital logic low value.

21. The gate driver integrated circuit of claim 16, further comprising:

a body diode current monitoring means for determining when the current through the body diode of the low side transistor rises above a predetermined threshold current during the time when the low side gate driver circuit controls the low side transistor to turn off, and for turning the low side transistor on in response to the determination.

22. The gate driver integrated circuit of claim 16, wherein the body diode current monitoring means determines when the current through the body diode of the high-side transistor rises above a predetermined threshold current by indirectly determining when the other current rises above the other predetermined threshold current.

23. The gate driver integrated circuit of claim 16, further comprising:

a low side driver logic circuit to supply control signals to the low side gate driver circuit and to receive low side digital input control signals from the low side driver digital control signal input terminal.

24. A gate driver integrated circuit for driving a power field effect transistor, wherein the power field effect transistor is part of a semiconductor die, and wherein a body diode is also part of the semiconductor die, the gate driver integrated circuit comprising:

a driver digital control signal input terminal;

a driver output terminal;

a gate driver circuit outputting a gate driver output signal onto the driver output terminal, wherein the gate driver circuit drives the gate of the power field effect transistor to turn on the power field effect transistor if a digital signal of a predetermined digital logic value is present on the driver digital control signal input terminal;

body diode current monitoring means for determining when the current through the body diode rises above a predetermined threshold current during the time that the gate driver circuit controls the power field effect transistor to turn off, and for turning on the power field effect transistor in response to the determination, so that the power field effect transistor turns on even if there is no digital signal of a predetermined digital logic value on the driver digital control signal input terminal; and

means for turning off the power field effect transistor in response to a transition of a second digital control signal, wherein the transition of the second digital control signal occurs during a time when the power field effect transistor is on and the digital signal on the driver digital control signal input terminal is not at the predetermined digital logic value, and wherein the gate driver integrated circuit does not include any digital processor that fetches and executes instructions.