CN110148389A - Shift register, gate drivers, display panel and display device - Google Patents
Shift register, gate drivers, display panel and display device Download PDFInfo
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- CN110148389A CN110148389A CN201910491124.7A CN201910491124A CN110148389A CN 110148389 A CN110148389 A CN 110148389A CN 201910491124 A CN201910491124 A CN 201910491124A CN 110148389 A CN110148389 A CN 110148389A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3266—Details of drivers for scan electrodes
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
Abstract
The present invention relates to shift register, gate drivers, display panel and display devices.Shift register includes input circuit (410), the first output circuit (420) and the second output circuit (430) for exporting the first and second gate drive signals respectively.Second output circuit includes control sub-circuit (431) and output sub-circuit (432).Controlling sub-circuit includes the first transistor, is configured to respond to second clock signal and is in second electrical level and opens with by its first extremely received reference voltage supplies to second node (N2), so that second node is in significant level.Output sub-circuit is configured to respond to the level of second node effectively and by the second reference voltage supplies to second output terminal (Gout_N).The type of the first transistor is consistent with the type for the transistor that second grid driving signal to be driven.Thus, it is possible to eliminate or alleviate the bootstrapping phenomenon of second grid drive signal waveform.
Description
Technical field
The present invention relates to field of display technology more particularly to a kind of shift register, gate drivers, display panels and aobvious
Showing device.
Background technique
Existing gate driving (also referred to as gate driving array, GOA) circuit is operable to generate and to display panel
Pixel array supplies gate drive signal.In application scenes, it is desirable that the same GOA circuit can export simultaneously N-type with
And p-type waveform to be to drive corresponding pixel array, and does not interfere with each other between two kinds of waveforms.
In existing circuit design, when GOA circuit output gate drive signal, in output end it sometimes appear that bootstrapping
Phenomenon is not able to satisfy actual demand so that gate drive signal is unable to reach desired waveform.Also, N-type and p-type waveform
Output it sometimes appear that can not jump simultaneously, thus nonsynchronous phenomenon.These affect the pixel that GOA circuit is driven
Pixel in array charges normal, and causes to show quality decline.
Summary of the invention
In a first aspect, the present invention provides a kind of shift registers.The shift register includes input terminal, the first clock
End, second clock end, the first reference voltage end, the second reference voltage end, the first output end and second output terminal.The shift LD
Device further includes input circuit, the first output circuit and the second output circuit.Input terminal is configured as receiving input signal.When first
Zhong Duan is configured as receiving the first clock signal.Second clock end is configured as receiving second clock signal.First reference voltage
End is configured as being applied the first reference voltage.Second reference voltage end is configured as being applied the second reference voltage.First is defeated
Outlet is configured as output first gate driving signal.Second output terminal is configured as output second grid driving signal.Input
Circuit is configured to respond to the first clock signal and input signal is effectively supplied to first node.First output circuit is matched
Be set to the first output end export first gate driving signal, and be configured to respond to first clock signal effectively and incite somebody to action
First reference voltage supplies are to the first output end, and are in significant level in response to the first node and believe second clock
Number it is supplied to first output end.When the second clock signal is in the first level, the first gate driving signal
Effectively.Second output circuit is configured as exporting second grid driving signal in second output terminal.The second output circuit packet
Include control sub-circuit and output sub-circuit.Control sub-circuit is configured as based on the first clock signal and second grid driving signal
To control the level of second node.Output sub-circuit is configured to respond to the first gate driving signal effectively and by first
Reference voltage supplies to the second output terminal, and in response to second node level effectively and by the second reference voltage supplies
To second output terminal.Controlling sub-circuit includes the first transistor.The first transistor is configured to respond to second clock letter
It number opens in second electrical level with by the first extremely received reference voltage supplies to second node, so that at the second node
In significant level.The type one of the type of the first transistor and the second grid driving signal transistor to be driven
It causes.
Optionally, which includes the grid for being connected to second clock signal end, is connected to the first and second ginsengs
It examines one in voltage end the first pole and is connected to the second pole of second node.The control sub-circuit further includes the second crystalline substance
Body pipe.Second transistor includes the grid for being connected to first output end, is connected to first and second reference voltage end
In another the first pole and be connected to the second pole of the second node.
Optionally, the output sub-circuit further include: third transistor comprising be connected to the grid of the second node
Pole, the first pole for being connected to second reference voltage end and the second pole for being connected to the second output terminal；With the 4th crystalline substance
Body pipe comprising be connected to the grid of first output end, the first pole for being connected to first reference voltage end and company
It is connected to the second pole of the second output terminal.
Optionally, the output sub-circuit further includes capacitor comprising connects one end and the connection of the second node
The other end of the second output terminal.
Optionally, the first gate driving signal is configured to drive P-type transistor, the second grid driving signal
It is configured to drive N-type transistor, and the first transistor is N-type transistor.
Optionally, the first transistor includes indium gallium zinc oxide (IGZO) thin film transistor (TFT).
Optionally, first output circuit includes: control sub-circuit, and it is effective to be configured to respond to the first clock signal
And by the second reference voltage supplies to third node；With output sub-circuit, it is configured to respond to first node and is in effectively electricity
It puts down and second clock signal is supplied to the first output end, and be in significant level in response to third node and referred to first
Voltage is supplied to the first output end.
Optionally, the input circuit includes: the 5th transistor comprising be connected to first clock end grid,
It is connected to the first pole of the input terminal and is connected to the second pole of first node.
Optionally, the control sub-circuit of first output circuit includes: the 6th transistor comprising is connected to described
The grid of one node, the first pole for being connected to first clock end and the second pole for being connected to third node；With the 7th crystalline substance
Body pipe comprising be connected to the grid of first clock end, the first pole for being connected to second reference voltage end and company
It is connected to the second pole of the third node.
Optionally, the output sub-circuit of first output circuit includes: the 8th transistor comprising is connected to described
The grid of three nodes, the first pole for being connected to first reference voltage end and it is connected to the second of first output end
Pole；With the 9th transistor comprising be connected to the grid of fourth node, the first pole for being connected to the second clock end and company
It is connected to the second pole of first output end.
In second aspect, the present invention provides a kind of gate drivers.The gate drivers include: M cascade as above
The shift register, M are the integer more than or equal to 2.First of m-th of shift register in M shift register is defeated
Outlet is connected to the input terminal of the m+1 shift register in M shift register, and m is integer and 1≤m≤M-1.
In the third aspect, the present invention provides a kind of display panels.The display panel includes: the first reference voltage line,
Two reference voltage lines, the first clock line, second clock line and gate drivers as described above.First reference voltage line is configured
At transmitting the first reference voltage.Second reference voltage line is configured to transmit the second reference voltage.First clock line is configured to
Transmit the first clock signal.Second clock line is configured to transmit second clock signal.First, second clock signal has opposite
Phase
In fourth aspect, the present invention provides a kind of display devices.Display device includes display panel as described above, timing control
Device and voltage generator processed.Sequence controller is configured to control the operation of the display panel, wherein the sequence controller
Be configured to supply respectively to first clock line and the second clock line first clock signal and it is described second when
Clock signal.Voltage generator is configured under the control of the sequence controller to the first scanning voltage line, described
Two scanning voltage lines, first reference voltage line and second reference voltage line supply respectively first scanning voltage,
Second scanning voltage, first reference voltage and second reference voltage.
Detailed description of the invention
According to the embodiment being described below, these and other aspects of the invention will be apparent it is clear, and
It will be elucidated with reference to the embodiment being described below.
Fig. 1 is the circuit diagram of one of the relevant technologies shift register；
Fig. 2 is the example timing diagram for shift register shown in FIG. 1；
Fig. 3 is the simulation waveform of the output of shift register shown in FIG. 1；
Fig. 4 is the schematic block diagram of shift register according to an embodiment of the present invention；
Fig. 5 is the circuit diagram of the exemplary circuit of shift register shown in Fig. 4；
Fig. 6 is the example timing diagram for shift register as shown in Figure 5；
Fig. 7 is the circuit diagram of another exemplary circuit of shift register shown in Fig. 4；
Fig. 8 is the simulation waveform of the output of shift register shown in fig. 5；
Fig. 9 is the block diagram of the gate drivers of embodiment according to the present invention；And
Figure 10 is the block diagram of the display device of embodiment according to the present invention.
Specific embodiment
It will be appreciated that although term first, second, third, etc. can be used to describe various component, assembly units herein
And/or part, but these component, assembly units and/or part should not be limited by these terms.These terms are only used to one
Component, assembly unit or part are mutually distinguished with another component, assembly unit or part.Therefore, first element discussed below, component or portion
Second element, part or part can be referred to as without departing from the teachings of the present invention by dividing.
Term used herein is merely for for the purpose of describing particular embodiments and being not intended to limit the present invention.As herein
Used in, singular "one", " one " and "the" be intended to also include plural form, unless context clearly separately has finger
Show.It will be further appreciated that term " includes " and/or "comprising" indicate when used in this manual mentioned feature,
The presence of entirety, step, operations, elements, and/or components, but it is not excluded for multiple such feature, entirety, step, operation, members
Part, component and/or the presence of its group or other one or more features, entirety, step, operation, component, assembly unit and/or its
The presence of group.As used in this article, term "and/or" includes associated listing any of one or more of project
With whole combinations.
It will be appreciated that when element is referred to as " being connected to another element " or " being coupled to another element ", it can
To be directly connected to another element or be directly coupled to another element, or may exist intermediary element.On the contrary, working as element
When referred to as " being directly connected to another element " or " being directly coupled to another element ", exist without intermediary element.
Unless otherwise defined, all terms (including technical terms and scientific terms) used herein have and the present invention
The normally understood identical meanings of those of ordinary skill in the art institute.It will be further appreciated that such as those usually make
Term defined in dictionary etc should be interpreted as having and it is in related fields and/or this specification context
The consistent meaning of meaning, and will not idealization or it is too formal in the sense that explain, unless clear herein
Ground is so defined.
Term " significant level " as used herein refers to that related circuit element is activated (for example, transistor is opened
Open) locating for level, and as used herein term " inactive level " refer to involved in circuit element it is disabled (for example,
Transistor is closed) locating for level.For n-type transistor, significant level is high level, and inactive level is low electricity
It is flat.For p-type transistor, significant level is low level, and inactive level is high level.It will be appreciated that effectively electric
Flat or inactive level and high level or low level are not intended to refer to some specific level, but may include an electricity
Flat range.In addition, term " level " intention is interchangeably used with " current potential ", " voltage level ".
Term " clock signal is effective " as used herein refers to that related clock signal is in defined operating voltage.
Also, term " disabling clock signals " as used herein refers to that related clock signal is not in defined operating voltage.
In the examples below, in the case where not clearly stating, it is assumed that mentioned transistor be p-type transistor but
It is, it should be understood that the p-type transistor in embodiment can be replaced n-type transistor, and correspondingly, n-type transistor can be replaced p
Transistor npn npn, and the operating voltage of each reference voltage and clock signal also correspondingly changes.In the case where n-type transistor,
Gate turn-on voltage has high level, and shutdown voltage has low level.In embodiments, each transistor can for example be taken thin
The form of film transistor is typically formed as so that their the first, second electrode is interchangeably used.Also contemplate it
His embodiment.
Fig. 1 is the circuit diagram of shift register 100 in the related technology.As shown in Figure 1, the shift register 100 includes
Transistor T1-T12 and capacitor C1-C3.When the shift register 100 is connected to input terminal GI, the first clock end CK, second
Clock end CB is connected to the first reference voltage end and the second reference voltage end to receive corresponding signal respectively, to be applied
With corresponding first reference voltage and the second reference voltage.First reference voltage can be high voltage VH, and the second reference voltage
It can be low-voltage VL, or vice versa.Can the shift register 100 further include the first output end Gout and second output
Gout_N is held, for exporting the gate drive signal with N-type and p-type waveform respectively.
Fig. 2 shows the example timing diagrams for shift register 100, wherein assuming the crystal in shift register 100
Pipe is p-type transistor, and gate turn-on voltage has low level, and shutdown voltage has high level.In the exemplary timing diagram
When giving the second of the input signal on input terminal GI, the first clock signal on the first clock end CK and second clock end CB
Clock signal.In this illustration, because the type of transistor is consistent, input signal, the first clock signal and second clock
Signal can effectively refer to that it is in the first level (such as low level), and can refer to it in vain and be in second electrical level (such as high electricity
It is flat).Correspondingly, the first output end Gout exports the effective p-type waveform of low level, and second output terminal Gout_N exports high level
Effective N-type waveform.In timing shown in Fig. 2, the first clock signal CK and second clock signal CB period having the same
With opposite phase, and between its timing may exist timing allowance (margin).As shown in Fig. 2, the presence of timing allowance makes
It obtains in the interval of time before second clock signal CB reaches operation level, the first clock signal CK is in inoperative electricity
It is flat.
From figure 2 it can be seen that the first output end Gout exports low level in the P3 stage, so that transistor T4 is opened, from
And the high level of the first reference voltage is supplied to second output terminal Gout_N.First output end Gout exports low level, also makes
It obtains transistor T2 to open, so that the high level of the first reference voltage is supplied to node N2, so that T3 is closed.Therefore second
Output end Gout_N is in high level.At the end of the P3 stage, transistor T2 is closed, so that node N2 is in suspended state.?
The P4 stage, so that node N2 voltage increases, transistor T3 can not be just since second clock signal CB from low level becomes high level
It is normally open, cause second output terminal Gout_N that can not export low-voltage in time.Until in P5 stage the first clock signal CK from height
Level becomes low level, and transistor T1 is opened, and just makes the reduction of node N2 voltage, and then open transistor T3, in the second output
Low-voltage is exported on the Gout_N of end.Moreover, in the P5 stage, since transistor T1 and T3 are p-type transistor, and p-type transistor
There are threshold voltages to lose (Vth Loss) under negative voltage, so the output on second output terminal Gout_N has bootstrapping now
As.That is, the output level on second output terminal Gout_N is by the low level of slightly above the second reference voltage, and it is unable to reach institute
Desired significant level.
Fig. 3 outputs simulation waveform of shift register when according to sequential operation shown in Fig. 2.As shown in figure 3,
In the N-type waveform of second output terminal Gout_N output, the high level on second output terminal Gout_N cannot after the P3 stage
It is enough to become low level in time, but slowly decline.Make in this way, when driving the grid of transistor to open in pixel circuit,
Its switching transistor controlled is all not completely turned off, thus has seriously affected charging normal for pixel (Pixel) point.This
Outside, since there are timing allowances between the first clock signal CK and the timing of second clock signal CB, so that the jump of Gout_N
The jump of Gout is lagged behind, this has also seriously affected the charging to driving transistor gate.
Fig. 4 is the schematic block diagram of shift register 400 according to an embodiment of the present invention.As shown in figure 4, shift register
Including input circuit 410, the first output circuit 420 and the second output circuit 430.
Input circuit 410 is configured as receiving input signal via input terminal GI and receives first via the first clock end CK
Clock signal.Input circuit 410 may be in response to the first clock signal CK and input signal GI be effectively supplied to first node N1.
First output circuit 420 is configured as receiving the first clock signal via the first clock end CK, via second clock
Hold CB receive second clock signal, and be connected to apply the first and second reference voltages the first and second reference voltage ends (VL,
) and first node N1 VH.First output circuit 420 may be in response to the first clock signal CK and effectively supply the first reference voltage
Should be to the first output end Gout, and be in significant level in response to first node and second clock signal CB is supplied to first
Output end Gout.First output circuit 420 is configured as output first gate driving signal.
Optionally, second clock signal CB can be at the first level and second electrical level, wherein the first level is operation level,
And second electrical level is inoperative level.When second clock signal CB be in the first level and it is effective when, first grid driving
Signal is effective.Here, the first clock signal and second clock signal can be the clock signal of reverse phase each other.Optionally, first
There are timing allowances between clock signal and second clock signal.
In some embodiments, the first output circuit 420 may include the first control sub-circuit 421 and the first output son electricity
Road 422.First control sub-circuit is configured as receiving the first clock signal via the first clock end CK, and is connected to application second
The second reference voltage end and node N1 of reference voltage.First control sub-circuit may be in response to the first clock signal CK effectively and
By the second reference voltage supplies to node N3.
First output sub-circuit is configured as receiving second clock signal via second clock end CB, and is connected to application the
The first reference voltage end and node N1 and node N3 of one reference voltage.First output sub-circuit may be in response to node N1 and be in
Significant level and second clock signal is supplied to the first output end Gout, and be in significant level in response to node N3 and incite somebody to action
First reference voltage supplies to the first output end Gout.First output sub-circuit is configured as output first gate driving signal.
Second output circuit 430 is configured as receiving second clock signal via second clock end CB, via the first output
It holds Gout to receive first gate driving signal, and is connected to the first and second reference voltages for applying the first and second reference voltages
It holds (VL, VH).Second output circuit 430 is configured as exporting second grid driving signal in second output terminal Gout_N.Second
Output circuit 430 includes the second control sub-circuit 431 and the second output sub-circuit 432.
Second output sub-circuit 432 is configured to respond to first gate driving signal and effectively supplies the first reference voltage
Second output terminal Gout_N should be arrived, and in response to node N2 is in significant level and the second reference voltage supplies are defeated to second
Outlet Gout_N.
Second control sub-circuit is configured as receiving second clock signal via second clock end CB, via the first output end
Gout receives first gate driving signal, and is connected to the first and second reference voltage ends for applying the first and second reference voltages
(VL, VH).Second control sub-circuit be used for based on the first clock signal and second grid driving signal come control node N2 whether
In significant level.Second control sub-circuit includes control transistor.Control transistor, which has, is connected to second clock signal end
The grid of CB, one be connected in the first and second reference voltage ends the first pole and be connected to the second pole of node N2.
Control transistor be configured to respond to second clock signal be in second electrical level (namely when invalid) and unlatching with by the first pole
Received reference voltage supplies are to second node N2, so that the second node N2 is in significant level.Control the class of transistor
Type is consistent with the type for the transistor that second grid driving signal to be driven.In other words, the grid for controlling transistor is effectively electric
Flat polarity is consistent with the polarity of the significant level of second grid driving signal.
For example, it is assumed that the second grid driving signal of second output terminal Gout_N output is N-type waveform, i.e. high level
Effectively, then controlling transistor can be N-type transistor.Since the significant level of N-type transistor is high level, low electricity is being transmitted
Threshold voltage loss effect is usually not present, it is possible to eliminate or alleviate the N-type waveform that second output terminal Gout_N is exported
Bootstrapping phenomenon so that the waveform finally exported can satisfy circuit (for example, low-temperature polysilicon oxide (Low Temperature
Polycrystalline Oxide；LTPO) circuit) demand.
Likewise, it is assumed that the second grid driving signal of second output terminal Gout_N output is p-type waveform, i.e. low level has
Effect, then controlling transistor can be P-type transistor.Since the significant level of P-type transistor is low level, in transmission high level
When threshold voltage loss effect is not present, it is possible to eliminate or alleviate the p-type waveform that is exported of second output terminal Gout_N
Bootstrapping phenomenon.
In some embodiments, control transistor can be IGZO(indium gallium zinc oxide, indium gallium zinc
Oxide) thin film transistor (TFT).Since the carrier mobility of amorphous oxides is 20 ~ 30 times of amorphous silicon, so using IGZO
Thin film transistor (TFT) can greatly improve TFT to the charge-discharge velocity of pixel electrode, improve the response speed of pixel, realize faster
Refresh rate.
Fig. 5 shows the exemplary circuit figure of the shift register 500 according to the embodiment of the present invention.Shift register 500 can
To include transistor T1 ', T2-T12 and capacitor C1-C3, input circuit 510,520 and of the first output circuit are separately constituted
And output circuit 530.
Input circuit 510 may include: the 5th transistor T5, have the grid for being connected to the first clock end CK, connection
To input terminal GI the first pole and be connected to the second pole of first node N1.
First output circuit 520 includes the first control sub-circuit 521 and the first output sub-circuit 522.First control son electricity
Road can include: the 6th transistor T6 has and is connected to the grid of first node N1, is connected to the first pole of the first clock end CK
And it is connected to the second pole of third node N3；7th transistor T7 has the grid for being connected to the first clock end CK, connection
To the first reference voltage end VH the first pole and be connected to the second pole of third node N3.First output sub-circuit may include the
Eight transistor T8 have grid, the first pole for being connected to the first reference voltage end VH and the company for being connected to third node N3
It is connected to the second pole of the first output end Gout；9th transistor T9 has the grid for being connected to fourth node N4, is connected to the
The first pole of two clock end CB and the second pole for being connected to the first output end Gout.
Optionally, the first control sub-circuit may also include that the tenth transistor T10, has and is connected to third node N3's
Grid, the first pole for being connected to the first reference voltage end VH and the second pole for being connected to the 5th node N5；11st transistor
T11 has the grid for being connected to second clock end CB, is connected to the first pole of first node N1 and is connected to the 5th node
The second pole of N5.Optionally, the first control sub-circuit may also include that the tenth two-transistor T12, has and is connected to the first reference
The grid of voltage end VH, the first pole for being connected to first node N1 and the second pole for being connected to fourth node N4.
Optionally, the first output sub-circuit, which may also include that, is connected between third node N3 and the first reference voltage end VH
First capacitor device C1 and the second capacitor C2 for being connected between fourth node N4 and the first output end Gout.
Second output circuit 530 includes the second control sub-circuit 531 and the second output sub-circuit 532.Second control son electricity
Road can include: second transistor T2 has the grid for being connected to the first output end Gout, is connected to the first reference voltage end VH
The first pole and be connected to the second pole of second node N2.The first transistor T1 ' has and is connected to second clock signal end
The grid of CB, the first pole for being connected to the second reference voltage end VL and the second pole for being connected to second node N2.Here, first
Transistor T1 ' is n-type transistor.Second output sub-circuit can include: the 4th transistor T4 has and is connected to second node N2
Grid, be connected to the first pole of the first reference voltage end VH and be connected to the second pole of second output terminal Gout_N；With
Three transistor T3, have be connected to the first output end Gout grid, be connected to the first pole of the first reference voltage end VH with
And it is connected to the second pole of second output terminal Gout_N.
Optionally, the second output sub-circuit further includes the be connected between third node N3 and second output terminal Gout_N
Three capacitor C3.
Fig. 6 shows the example timing diagram for shift register as shown in Figure 5, wherein assuming circuit shown in Fig. 5
In, transistor T1 ' is n-type transistor, and assumes that transistor T2-T12 is p-type transistor, and the first reference voltage end is applied
Increase level VH, and the second reference voltage end is applied low level VL.The input signal on input terminal GI that is provided in Fig. 6,
The timing and waveform of the second clock signal of the first clock signal and second clock end CB on one clock end CK and phase in Fig. 2
Together.For clear period, 5 different stage P1-P5 of corresponding each signal intensity hereinafter have been described in detail.
In the first stage in P1, input signal GI is low level, and the first clock signal CK is low level, second clock signal
CB is high level.
In input circuit, CK is that low level opens the 5th transistor T5, so that input signal GI is supplied to the
One node N1.Because in this stage, GI keeps low level, so first node N1 is also at low level.
In the first output circuit, CK is that low level opens the 7th transistor T7, thus will be from first with reference to electricity
The low level of pressure is supplied to third node N3.N3 is in low level and the 8th transistor T8 is opened, thus will be from the first ginseng
The high level for examining voltage is supplied to the first output end Gout.
In the second output circuit, the high level on the first output end Gout turns off the 4th transistor T4.CB is height
Level opens the first transistor T1 ', so that the low level from the second reference voltage end VL is supplied to second node N2.
N2 is in low level and third transistor T3 is opened, and the low level from the second reference voltage end VL is supplied to the second output
Hold Gout_N.
In second stage P2, the first clock signal CK, second clock signal CB are high level.
In input circuit, CK is that high level turns off the 5th transistor T5.Therefore, although GI in this stage in shape
State changes, i.e., becomes high level from low level, but first node N1 is maintained as the state in first stage T1, that is, locates
In low level.
In the first output circuit, CK is that high level turns off the 7th transistor T7.Meanwhile first node N1 is still kept
For the state in first stage T1, that is, it is in low level.On the one hand, the low level of first node N1 beats the 6th transistor T6
It opens, the high level of CK is supplied to third node N3, so that the 8th transistor T8 is turned off.On the other hand, the second reference voltage end
Low level VL the tenth two-transistor T12 is kept it turning on, so that the low level of first node N1 is supplied to fourth node
N4.N4 low level opens the 9th transistor T9, so that the high level from second clock signal end CB is supplied to first
Output end Gout.
In the second output circuit, the high level on the first output end Gout turns off the 4th transistor T4.Meanwhile CB
For high level the first transistor T1 ' is opened, the low level VL from the second reference voltage end is supplied to second node N2.
Second node N2 is in low level and third transistor T3 is opened, and the low level from the second reference voltage end VL is supplied to
Second output terminal Gout_N.
In phase III P3, input signal GI, the first clock signal CK are high level, and second clock signal CB is low electricity
It is flat.
In input circuit, since CK is high level, the 5th transistor T5 is still turned off, and first node N1 remains low electricity
It is flat.
In the first output circuit, on the one hand, the low level of first node N1 opens the 6th transistor T6, by CK's
High level is supplied to third node N3, so that the 8th transistor T8 is turned off.On the other hand since the first reference end is low level VL,
Tenth two-transistor T12 is kept it turning on, and first node N1, fourth node N4 remain low level.N4 is low so that the 9th transistor
T9 is kept it turning on, and the low level from second clock signal end CB is supplied to the first output end Gout.At this point, first grid drives
Dynamic signal is in low level.
In the second output circuit, the low level on the first output end Gout opens the 4th transistor T4, will come from
The high level VH of first reference voltage end is supplied to Gout_N.Meanwhile the first low level on output end Gout also makes second
Transistor T2 is opened, and the high level VH from the first reference voltage end is supplied to second node N2, so that third transistor T3
Shutdown.Since CB is low level, so the first transistor T1 ' is turned off at this time.
In fourth stage P4, input signal GI, the first clock signal CK, second clock signal CB are high level.
In input circuit, since CK is high level, the 5th transistor T5 is still turned off, and first node N1 remains low electricity
It is flat.
In the first output circuit, the state of each transistor is remained unchanged.Difference with phase III T3 is, due to
Two clock signals become high level, so the first gate driving signal on the first output end correspondingly becomes high electricity from low level
It is flat.
In the second output circuit, since CB is high level, the high level on the first output end Gout makes the 4th crystal
Pipe T4 shutdown.Meanwhile CB is that high level opens the first transistor T1 ', by the low level VL from the second reference voltage end
It is supplied to second node N2.Second node N2 is in low level and third transistor T3 is opened, and will come from the second reference voltage
The low level of end VL is supplied to second output terminal Gout_N.
In 5th stage P5, input signal GI is high level, and the first clock signal CK becomes low level, second clock signal
CB is high level.
In input circuit, CK is that low level opens the 5th transistor T5, so that input signal GI is supplied to the
One node N1.Because in this stage, GI keeps high level, so first node N1 is also at high level.
In the first output circuit, CK is that low level opens the 7th transistor T7, thus will be from first with reference to electricity
The low level of pressure is supplied to third node N3.N3 is in low level and the 8th transistor T8 is opened, thus will be from the first ginseng
The high level for examining voltage is supplied to the first output end Gout.On the other hand, N1 high level turns off the 9th transistor T9.
In the second output circuit, the high level on the first output end Gout turns off the 4th transistor T4.CB is height
Level opens the first transistor T1 ', so that the low level from the second reference voltage end VL is supplied to second node N2.
N2 is in low level and third transistor T3 is opened, and the low level from the second reference voltage end VL is supplied to the second output
Hold Gout_N.
Since in shift register shown in Fig. 5, the first transistor T1 ' (namely control transistor) is n-type transistor,
And its grid is connected to second clock signal end, and therefore, when the first transistor T1 ' is opened in P1, P2, P4, P5 stage,
Threshold voltage loss effect is not present when transmitting low level.The first transistor T1 ' unlatching can be by the electricity at second node N2
The flat low level for being pulled down to the second reference voltage end.This avoid the bootstrapping phenomenons occurred at second node N2, so that third
Transistor can be opened preferably, to mitigate or alleviate the bootstrapping phenomenon at second output terminal Gout_N.
Optionally, when in the second output circuit including third capacitor C3, the when second node N2 is in significant level
Three capacitor C3 can make the opening degree for further increasing third transistor T3, thus by the electricity of second output terminal Gout_N
Horizontal drawing is to lower level.The bootstrapping phenomenon at second output terminal Gout_N can be eliminated further as a result,.
In addition, the first transistor T1 ' and correspondingly third are brilliant when phase III P3 terminates, fourth stage P4 starts
Body pipe T3 can due to second clock signal CB jump and turned off in time, so that it is guaranteed that second grid driving signal and first
Gate drive signal can be realized synchronous jump.
Although being appreciated that the first output circuit 510 is shown as the shift LD of 8T2C form in the embodiment above
Device, but the invention is not restricted to this, but other conventional shift registers that can export gate drive signal can be used, all
Shift register such as in the form of 3T1C, 12T1C, 18T1C.
In the above embodiments, although transistor T2-12 is depicted and described as p-type transistor, n-type transistor
It is also possible.In the case where n-type transistor, gate turn-on voltage has low level, and gate off voltage has height
Level.
Fig. 7 shows another exemplary circuit figure of the second output circuit according to the embodiment of the present disclosure.In Fig. 7, except the
For one transistor T1 ' using outside n-type transistor, third transistor T3 ' also uses n-type transistor.Circuit structure and Fig. 5 shown in Fig. 7
In it is similar, difference be only that the first pole of second transistor T2 is connected to the second reference voltage end VL and the first transistor
The first pole of T1 ' is connected to the first reference voltage end VH.
In this embodiment, the level and second clock signal of the first gate driving signal of the first output end Gout output
Level basic synchronization change.When first gate driving signal and second clock signal are low level, first grid is driven
Dynamic signal is that low level opens the 4th transistor T4, so that the second reference voltage VH is supplied to second output terminal Gout_
N.Second grid driving signal is height at this time.Meanwhile first gate driving signal is that low level opens second transistor T2,
To which the first reference voltage VL is supplied to second node N2.N2 is low so that third transistor T3 ' (n-type transistor) is turned off.Separately
On the one hand, second clock signal is low level, but also the first transistor T1 ' is turned off.
When first gate driving signal and second clock signal are high level, first gate driving signal is high level
So that second transistor T2 and the 4th transistor T4 shutdown.On the other hand, second clock signal is high level, so that first crystal
Pipe T1 ' (N-shaped) is opened, so that the second reference voltage VH is supplied to second node N2.N2 high opens third transistor T3 '
It opens, so that the first reference voltage VL is supplied to second output terminal Gout_N.
In this embodiment, since the first transistor T1 ' in the exemplary circuit and third transistor T3 ' are all made of
N-type transistor is realized, is equally avoided the second grid caused by threshold voltage loss effect when transmitting low level and is driven
Bootstrapping phenomenon in signal.
In embodiments, each transistor can for example take the form of thin film transistor (TFT), be typically produced so that
Their the first, second electrode is interchangeably used.
In an alternative embodiment, shift register further includes the third reference electricity for being configured as being applied third reference voltage
Pressure side VLL(is not shown).In this embodiment, the first pole of the first transistor T1 ' be connected to third reference voltage end VLL rather than
Second reference voltage end VL.Reference voltage in third reference voltage end is lower than the first reference voltage, to facilitate first
Transistor T1 ' is pulled to lower by the level of second node N2 and correspondingly by the level Gout_N of second output terminal when opening
Level, further to eliminate the bootstrapping phenomenon in second grid driving signal.
Fig. 8 shows shift register shown in fig. 5 according to the resulting simulation waveform of sequential operation of Fig. 6.Such as Fig. 8 institute
Show, in the N-type waveform of shift register second output terminal, when changing to low level from high level, there is no lose because of threshold value
Desired low level situation cannot be reached caused by effect.Moreover, N-type waveform and the first output end of shift register
P-type waveform has substantially carried out synchronously level jump.
Embodiment according to the invention, by the crystal for suitably selecting suitable type according to desired output waveform
Pipe, and the design of control signal wire is correspondingly adjusted, the threshold value loss effect in avoiding GOA circuit because of transistor is caused
The problem of while so that its output waveform more meet demand.Moreover, embodiment according to the invention, does not need to introduce
Additional signal wire, and original control sequential can be continued to use, thus save in GOA circuit and design and manufacture cost.
Fig. 9 is the block diagram of the gate drivers 900 of embodiment according to the present invention.As shown in figure 9, gate drivers 900
Including M cascade shift register GOA(1), GOA(2) ..., GOA(M-1), GOA(M).Each shift register can be with
Take the form of the shift register as described in above in conjunction with Fig. 6-8.M is the integer more than or equal to 2.In gate drivers 900
In, other than first shift register, the input terminal of each shift register is connected to an adjacent upper shift register
The first output end.The input terminal of first shift register can connect to initial signal STV as input signal.
M shift register GOA(1 in gate drivers 900), GOA(2) ..., GOA(M-1), GOA(M) can be with
Be respectively connected to M the first grid line G [1], G [2] ..., G [M-1], G [M] and M the second grid line G_N [1], G_N
[2],……,G_N[M-1],G_N[M].Each shift register can be configured to be connected to the of the first reference voltage of transmission
One reference voltage line, the second reference voltage line for transmitting the second reference voltage, the first clock signal for transmitting the first clock signal
The line ck and second clock signal wire cb for transmitting second clock signal.First clock signal has opposite with second clock signal
Phase.First reference voltage has opposite polarity with the second reference voltage.
In an alternative embodiment, each shift register can be configured to the third for being connected to transmission third reference voltage
Reference voltage line.Third reference voltage and the second reference voltage polarity having the same, but there is bigger voltage amplitude.
Figure 10 is the block diagram of the display device of embodiment according to the present invention.With reference to Figure 10, display device 1000 includes aobvious
Show panel 1010, sequence controller 1020, gate drivers 1030, data driver 1040 and voltage generator 1050.Grid
Driver 1030 can take the form above for gate driving circuit 900 described in Fig. 9.In Figure 10, for the side of diagram
Just, the first clock line ck, second clock line cb, the first reference voltage line vh and the second reference voltage line vl being shown in FIG. 9
It is omitted.
Display panel 1010 is connected to the multiple gate lines G L extended in the first direction dl and hands over first direction D1
Pitch the multiple data line DL extended on the second direction D2 of (for example, substantially vertical).Display panel 1010 includes in the matrix form
Multiple pixel (not shown) of arrangement.Each of described pixel may be electrically connected to one grid line of the correspondence in gate lines G L
With the one data line of correspondence in data line DL.Display panel 1010 can be liquid crystal display panel, Organic Light Emitting Diode
(OLED) display panel or the display panel of any other suitable type.
It is raw that sequence controller 1020 controls the display panel 1010, gate drivers 1030, data driver 1040 and voltage
Grow up to be a useful person 1050 operation.Sequence controller 1020 receives input image data RGBD and input from external equipment (for example, host)
Control signal CONT.Input image data RGBD may include multiple input pixel datas for multiple pixels.Each input picture
Prime number evidence may include for correspondence one red gradation data R, the green gradation data G and blue grey in multiple pixels
According to B.Input control signal CONT may include master clock signal, data enable signal, vertical synchronizing signal, horizontal synchronizing signal
Deng.Sequence controller 1020 be based on input image data RGBD and input control signal CONT generate output image data RGBD ',
First control signal CONT1 and second control signal CONT2.Being achieved in that for sequence controller 1020 is known in the art.
Sequence controller 1020 (such as utilizing specialized hardware) can be realized in many ways to execute the various differences being discussed herein
Function." processor " is using an example of the sequence controller 1020 of one or more microprocessors, the micro process
Device can be used software (such as microcode) and be programmed to execute a variety of different functions being discussed herein.Sequence controller
1020 can realize in use or in the case where not using processor, and also can be implemented as executing the special of some functions
With the combination of hardware and the processor for executing other function.The example of sequence controller 1020 includes but is not limited to conventional micro- place
Manage device, specific integrated circuit (ASIC) and field programmable gate array (FPGA).
Gate drivers 1030 receive first control signal CONT1 from sequence controller 1020.First control signal CONT1
When may include via the first, second clock line ck and cb transmission being shown in FIG. 9 and first, second with opposite phase
Clock signal.Gate drivers 1030 generate multiple first grids for being output to gate lines G L based on first control signal CONT1
Pole driving signal and/or second grid driving signal.Gate drivers 1030 can be sequentially by multiple first gate driving signals
And/or second grid driving signal is applied to gate lines G L, to drive display panel to be shown.
Data driver 1040 receives second control signal CONT2 and output image data from sequence controller 1020
RGBD'.Data driver 1040 is based on second control signal CONT2 and output image data RGBD ' generates multiple data voltages.
Multiple data voltages of generation can be applied to data line DL by data driver 1040.
Voltage generator 1050 is to display panel 1010, sequence controller 1020, gate drivers 1030, data driver
1040 and potentially other component supply electric power.Specifically, voltage generator 1050 is configured in sequence controller
It is supplied under 1020 control respectively via the first reference voltage line vh being shown in FIG. 9 and the second reference voltage line vl transmission
First reference voltage and the second reference voltage.The configuration of voltage generator 1050 can be known in the art.It is realized at one
In mode, voltage generator 1050 may include the electric pressure converter and crossbar switch of such as DC/DC converter etc
(crossbar switch).The electric pressure converter generates multiple output voltages with different voltages level from input voltage.
Then, these output voltages can be selectively coupled to first under the control of sequence controller 1020 by the crossbar switch
Reference voltage line vh and the second reference voltage line vl, to supply the first, second required reference voltage.
In embodiments, gate drivers 1030 and/or data driver 1040 may be disposed at display panel 1010
On, or (Tape Carrier Package, TCP) can be encapsulated by such as tape carrier and be connected to display panel
1010.For example, gate drivers 1030, which can be incorporated in display panel 1010, drives (gate as array substrate row
Driver on array, GOA) circuit.
The example of display device 1000 include but is not limited to mobile phone, tablet computer, television set, display, laptop,
Digital Frame, navigator.
Above-described embodiment is shown for illustrative purpose, and is not necessarily to be construed as limiting the scope of the invention.
Under the premise of without departing from the spirit of the present invention, those of ordinary skill in the art can make several changes to described embodiment
Type and modification, these variants and modifications also should be regarded as covering within the scope of the present invention.
Claims (13)
1. a kind of shift register, comprising:
Input terminal is configured as receiving input signal；
First clock end is configured as receiving the first clock signal；
Second clock end is configured as receiving second clock signal；
First reference voltage end is configured as being applied the first reference voltage；
Second reference voltage end is configured as being applied the second reference voltage；
First output end is configured as output first gate driving signal；
Second output terminal is configured as output second grid driving signal；
Input circuit is configured to respond to the first clock signal and input signal is effectively supplied to first node；
First output circuit is configured as exporting first gate driving signal in the first output end, and is configured to respond to institute
The first clock signal is stated effectively to be in by the first reference voltage supplies to the first output end, and in response to the first node
Significant level and second clock signal is supplied to first output end, wherein when the second clock signal be in first electricity
Usually, the first gate driving signal is effective；With
Second output circuit is configured as exporting second grid driving signal, the second output circuit packet in second output terminal
It includes:
Sub-circuit is controlled, is configured as controlling the electricity of second node based on the first clock signal and second grid driving signal
It is flat, and
Sub-circuit is exported, is configured to respond to the first gate driving signal effectively and by the first reference voltage supplies to institute
State second output terminal, and in response to second node level effectively and by the second reference voltage supplies to second output terminal,
Wherein, the control sub-circuit includes the first transistor, and the first transistor is configured to respond to second clock letter
It number opens in second electrical level with by its first extremely received reference voltage supplies to second node, so that the second node
In significant level, and
Wherein, the type one of the type of the first transistor and the second grid driving signal transistor to be driven
It causes.
2. shift register as described in claim 1, wherein the first transistor includes being connected to second clock signal end
Grid, one be connected in the first and second reference voltage ends the first pole and be connected to the second pole of second node, with
And the control sub-circuit further include:
Second transistor comprising be connected to the grid of first output end, be connected to first and second reference voltage
Another the first pole in end and the second pole for being connected to the second node.
3. shift register as described in claim 1, wherein the output sub-circuit further include:
Third transistor comprising be connected to the grid of the second node, be connected to the first of second reference voltage end
Pole and the second pole for being connected to the second output terminal；With
4th transistor comprising be connected to the grid of first output end, be connected to the of first reference voltage end
One pole and the second pole for being connected to the second output terminal.
4. shift register as claimed in any one of claims 1-3, wherein the output sub-circuit further includes capacitor,
It includes the one end for connecting the second node and the other end for connecting the second output terminal.
5. shift register as claimed in any one of claims 1-3, wherein the first gate driving signal is configured to
P-type transistor is driven, the second grid driving signal is configured to drive N-type transistor, and the first transistor is N-type
Transistor.
6. shift register as claimed in any one of claims 1-3, wherein the first transistor includes the oxidation of indium gallium zinc
Object (IGZO) thin film transistor (TFT).
7. shift register as claimed any one in claims 1 to 3, wherein first output circuit includes:
Sub-circuit is controlled, is configured to respond to the first clock signal effectively and by the second reference voltage supplies to third node；
With
Sub-circuit is exported, is configured to respond to that first node is in significant level and that second clock signal is supplied to first is defeated
Outlet, and in response to third node be in significant level and by the first reference voltage supplies to the first output end.
8. shift register as claimed in any one of claims 1-3, wherein the input circuit includes:
5th transistor comprising be connected to the grid of first clock end, be connected to the input terminal the first pole and
It is connected to the second pole of first node.
9. shift register as claimed in claim 7, wherein the control sub-circuit of first output circuit includes:
6th transistor comprising be connected to the grid of the first node, be connected to the first pole of first clock end with
And it is connected to the second pole of third node；With
7th transistor comprising be connected to the grid of first clock end, be connected to the of second reference voltage end
One pole and the second pole for being connected to the third node.
10. shift register as claimed in claim 7, wherein the output sub-circuit of first output circuit includes:
8th transistor comprising be connected to the grid of the third node, be connected to the first of first reference voltage end
Pole and the second pole for being connected to first output end；With
9th transistor comprising be connected to the grid of fourth node, the first pole for being connected to the second clock end and company
It is connected to the second pole of first output end.
11. a kind of gate drivers, comprising:
The M cascade shift registers as described in any one of claims 1 to 10, M are the integer more than or equal to 2,
Wherein, the first output end of m-th of shift register in M shift register is connected in M shift register
The input terminal of the m+1 shift register, m are integer and 1≤m≤M-1.
12. a kind of display panel, comprising:
First reference voltage line is configured to transmit the first reference voltage；
Second reference voltage line is configured to transmit the second reference voltage；
First clock line is configured to transmit the first clock signal；
Second clock line, is configured to transmit second clock signal, and the first, second clock signal has opposite phase；And
Gate drivers as claimed in claim 11.
13. a kind of display device, comprising:
Display panel as claimed in claim 12；
Sequence controller is configured to control the operation of the display panel, wherein the sequence controller is configured to institute
It states the first clock line and the second clock line supplies first clock signal and the second clock signal respectively；And
Voltage generator is configured under the control of the sequence controller to the first scanning voltage line, described second
Scanning voltage line, first reference voltage line and second reference voltage line supply first scanning voltage, institute respectively
State the second scanning voltage, first reference voltage and second reference voltage.
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Also Published As
| Publication number | Publication date |
|---|---|
| CN113744693A (en) | 2021-12-03 |
| CN110148389B (en) | 2021-10-12 |
| CN113744693B (en) | 2024-02-13 |
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