CN110137173B - Memory and operation method thereof - Google Patents

Memory and operation method thereof Download PDF

Info

Publication number
CN110137173B
CN110137173B CN201910297081.9A CN201910297081A CN110137173B CN 110137173 B CN110137173 B CN 110137173B CN 201910297081 A CN201910297081 A CN 201910297081A CN 110137173 B CN110137173 B CN 110137173B
Authority
CN
China
Prior art keywords
bit
memory
line
positive voltage
drain region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201910297081.9A
Other languages
Chinese (zh)
Other versions
CN110137173A (en
Inventor
杨光军
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Huahong Grace Semiconductor Manufacturing Corp
Original Assignee
Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Huahong Grace Semiconductor Manufacturing Corp filed Critical Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority to CN201910297081.9A priority Critical patent/CN110137173B/en
Publication of CN110137173A publication Critical patent/CN110137173A/en
Application granted granted Critical
Publication of CN110137173B publication Critical patent/CN110137173B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

The invention discloses a memory, wherein the memory cell adopts a structure of three grid structures and two source-drain regions, the same row in the array structure comprises two control lines and a word line which are respectively connected with a control grid and a selection grid corresponding to the memory cell, the memory cells in the same column are connected in series, the memory cells in the same column are connected with two bit lines, the first source-drain regions of the memory cells in the odd-numbered rows and the second source-drain regions of the memory cells in the even-numbered rows are both connected with a first bit line, the second source-drain regions of the memory cells in the odd-numbered rows and the first source-drain regions of the memory cells in the even-numbered rows are both connected with a second bit line, the memory cell structure and the array structure of the memory can realize reasoning operation, and the input signal of the inference operation adopts the input current of the word line of each row and the output signal adopts the output voltage of the bit line corresponding to each column. The invention also discloses an operation method of the memory. The invention can realize the operation of calculation integration.

Description

Memory and operation method thereof
Technical Field
The present invention relates to the field of semiconductor integrated circuits, and more particularly, to a memory. The invention also relates to an operation method of the memory.
Background
As shown in fig. 1, it is a structural diagram of a memory Cell (Cell) of a conventional memory; each memory cell 1 includes: a first gate structure 104, a second gate structure 105, a third gate structure 106, a first source drain region 102 and a second source drain region 103.
The first Gate structure 104 is formed by stacking a first Gate dielectric layer 107, a Floating Gate (FG) 108, a second Gate dielectric layer 109 and a polysilicon control Gate 110, which are formed on the surface of the semiconductor substrate 101. The first source drain region 102 and the second source drain region 103 are typically N + doped, and the semiconductor substrate 101 is a P-type doped silicon substrate.
The second gate structure 105 is composed of a third gate dielectric layer 111 and a polysilicon gate 112 formed on the surface of the semiconductor substrate 101.
The third gate structure 106 is formed by overlapping a first gate dielectric layer 107, a floating gate 108, a second gate dielectric layer 109 and a polysilicon control gate 110 formed on the surface of the semiconductor substrate 101.
A channel region is formed by the semiconductor substrate 101 located between the first source drain region 102 and the second source drain region 103.
The first gate structure 104, the second gate structure 105, and the third gate structure 106 are arranged on the surface of the channel region between the first source-drain region 102 and the second source-drain region 103, and the formation of a channel on the surface of the channel region is controlled by the first gate structure 104, the second gate structure 105, and the third gate structure 106.
The polysilicon control gate 110 of the first gate structure 104 serves as a first control gate CCG0 of the memory cell 1; the polysilicon gate 112 of the second gate structure 105 is used as a select gate CWL of the memory cell 1; the polysilicon control gate 110 of the third gate structure 106 serves as the second control gate CCG1 of the memory cell 1.
The floating gate 108 of the first gate structure 104 is a first storage bit and the floating gate 108 of the third gate structure 106 is a second storage bit.
The first source drain region 102 is connected to the source S and the second source drain region 103 is connected to the drain D.
In prior art memories, programming of a memory bit typically employed source side hot electron injection (SSI) to program a second memory bit for illustration as follows:
the programmed voltages are:
select gate CWL is 1.4V, which results in the formation of a channel at the bottom of second gate structure 105;
the first control gate CCG0 is 5V, which results in the formation of a channel at the bottom of the first gate structure 104;
the source S provides a programming current with the magnitude of 2 muA;
the voltage of 5.5V is applied to the drain D, the voltage of 8V is applied to the third control gate CCG1, and the voltages of the drain D and the third control gate CCG1 cause the bottom of the third gate structure 106 to generate a larger depletion region, so that electrons flow into the depletion region at the bottom of the third gate structure 106 from the source S side through the channel and are then injected into the floating gate 108 of the third gate structure 106, thereby realizing programming. The existing memory can not realize single storage bit operation, thereby realizing the calculation integration.
Disclosure of Invention
The invention aims to provide a memory which can realize the operation of storage and calculation. Therefore, the invention also provides an operation method of the memory.
Therefore, the invention provides a memory which comprises a plurality of memory units, wherein each memory unit comprises three grid structures and two source-drain regions, the grid structures are respectively a first grid structure, a second grid structure and a third grid structure, and the source-drain regions are respectively a first source-drain region and a second source-drain region.
The first grid structure is formed by overlapping a first grid dielectric layer, a floating grid, a second grid dielectric layer and a polycrystalline silicon control grid which are formed on the surface of the semiconductor substrate.
The second grid structure consists of a third grid dielectric layer and a polysilicon grid which are formed on the surface of the semiconductor substrate.
The third grid structure is formed by overlapping a first grid dielectric layer, a floating grid, a second grid dielectric layer and a polycrystalline silicon control grid which are formed on the surface of the semiconductor substrate.
And forming a channel region by the semiconductor substrate between the first source drain region and the second source drain region.
The first gate structure, the second gate structure and the third gate structure are arranged on the surface of the channel region between the first source drain region and the second source drain region, and the first gate structure, the second gate structure and the third gate structure jointly control the formation of a channel on the surface of the channel region.
The polysilicon control gate of the first gate structure is used as a first control gate of the memory cell; the polysilicon gate of the second gate structure is used as a selection gate of the storage unit; the polysilicon control gate of the third gate structure serves as a second control gate of the memory cell.
The storage unit comprises two storage bits, the floating gate of the first grid structure is the first storage bit, and the floating gate of the third grid structure is the second storage bit.
Each memory cell is arranged in rows and columns to form an array structure, and the array structure is as follows:
the memory unit comprises two control lines and a word line, wherein the first control gate of each memory unit is connected to the corresponding first control line, the selection gates are connected to the corresponding word line, and the second control gates are connected to the corresponding second control line.
All the memory cells in the same column are connected in series, and the series structure is as follows: except for the first row and the last row with the maximum row numerical value, the first source drain region of each row of the storage units is connected with the second source drain region of the storage unit in the previous adjacent row, and the second source drain region of each row of the storage units is connected with the first source drain region of the storage unit in the next adjacent row.
The memory cells in the same column are connected with two bit lines, the first source drain regions of the memory cells in the odd-numbered rows and the second source drain regions of the memory cells in the even-numbered rows are connected to a first bit line, and the second source drain regions of the memory cells in the odd-numbered rows and the first source drain regions of the memory cells in the even-numbered rows are connected to a second bit line.
The operation of the memory includes an Inference (reference) operation, an input signal of the Inference operation uses an input current of the word line of each row, and an output signal of the Inference operation of the memory uses an output voltage of a bit line corresponding to each column.
In a further improvement, in the inference operation of the memory, the first working state of the same column is:
the storage bit corresponding to the source drain region connected with the first bit line is a selected storage bit, the storage bit corresponding to the source drain region connected with the second bit line is an unselected storage bit, the control line corresponding to each selected storage bit is connected with 0V voltage, the control line corresponding to each unselected storage bit is connected with a first positive voltage, the size of the first positive voltage meets the requirement that the surface of the channel region at the bottom of the unselected storage bit is inverted to form a channel, the first bit line is connected with 0V voltage, and each word line is connected with the input current to serve as the input signal, so that the output signal is formed by the second bit line.
In a further improvement, in the inference operation of the memory, the second working state of the same column is:
the storage bit corresponding to the source drain region connected with the second bit line is a selected storage bit, the storage bit corresponding to the source drain region connected with the first bit line is an unselected storage bit, the control line corresponding to each selected storage bit is connected with 0V voltage, the control line corresponding to each unselected storage bit is connected with a first positive voltage, the size of the first positive voltage meets the requirement that the surface of the channel region at the bottom of the unselected storage bit is inverted to form a channel, the second bit line is connected with 0V voltage, and each word line is connected with the input current to serve as the input signal, so that the output signal is formed by the first bit line.
In a further improvement, the operation of the memory further includes a Learning operation, the Learning operation includes a Weight increasing (Weight up) operation, and the operating status of the same column in the Weight increasing operation is:
each word line is connected to a second positive voltage.
Each control line is connected with a first negative voltage; the second positive voltage is greater than the first positive voltage, and the difference between the second positive voltage and the first negative voltage is of a magnitude sufficient to effect erasure of each of the storage bits.
Each of the bit lines is connected with a voltage of 0V.
In a further improvement, the learning operation includes a Weight-reducing (Weight down) operation, and in the Weight-reducing operation, the first operating state in the same column is:
the storage bit corresponding to the source-drain region connected with the first bit line is a selected storage bit, the storage bit corresponding to the source-drain region connected with the second bit line is an unselected storage bit, and the control line corresponding to each selected storage bit is connected with a third positive voltage.
The control line corresponding to each unselected storage bit is connected with a first positive voltage.
Each of the word lines is connected to a fourth positive voltage.
The first bit line is connected to a fifth positive voltage.
The second bit line is connected to a write current.
The fourth positive voltage enables the surface of the channel region at the bottom of the second grid structure to be inverted to form a channel, and the third positive voltage, the fifth positive voltage and the write current enable source-end hot electron injection programming of the selected storage bit.
In a further improvement, the learning operation includes a weight reduction operation, and in the weight reduction operation, the second operating state of the same column is:
the storage bit corresponding to the source-drain region connected with the second bit line is a selected storage bit, the storage bit corresponding to the source-drain region connected with the first bit line is an unselected storage bit, and the control line corresponding to each selected storage bit is connected with a third positive voltage.
The control line corresponding to each unselected storage bit is connected with a first positive voltage.
Each of the word lines is connected to a fourth positive voltage.
The first bit line is coupled to a write current.
The second bit line is connected with a fifth positive voltage.
In a further refinement, in a first operating state of the same column in the speculative operation of the memory, the output signal is determined by an output current from the second bit line, the output current of the second bit line being an accumulated value of the input current of each word line multiplied by a corresponding coefficient, the coefficient by which the input current of each word line is multiplied being determined by the programming depth of the corresponding memory bit.
In a further refinement, in a second operating state of the same column in the speculative operation of the memory, the output signal is determined from an output current from the first bit line, the output current of the first bit line being an accumulated value of the input current of each word line multiplied by a corresponding coefficient, the coefficient by which the input current of each word line is multiplied being determined by the programming depth of the corresponding memory bit.
In order to solve the technical problem, the memory in the operation method of the memory provided by the invention comprises a plurality of memory units, each memory unit comprises three gate structures and two source-drain regions, the gate structures are respectively a first gate structure, a second gate structure and a third gate structure, and the source-drain regions are respectively a first source-drain region and a second source-drain region.
The first grid structure is formed by overlapping a first grid dielectric layer, a floating grid, a second grid dielectric layer and a polycrystalline silicon control grid which are formed on the surface of the semiconductor substrate.
The second grid structure consists of a third grid dielectric layer and a polysilicon grid which are formed on the surface of the semiconductor substrate.
The third grid structure is formed by overlapping a first grid dielectric layer, a floating grid, a second grid dielectric layer and a polycrystalline silicon control grid which are formed on the surface of the semiconductor substrate.
And forming a channel region by the semiconductor substrate between the first source drain region and the second source drain region.
The first gate structure, the second gate structure and the third gate structure are arranged on the surface of the channel region between the first source drain region and the second source drain region, and the first gate structure, the second gate structure and the third gate structure jointly control the formation of a channel on the surface of the channel region.
The polysilicon control gate of the first gate structure is used as a first control gate of the memory cell; the polysilicon gate of the second gate structure is used as a selection gate of the storage unit; the polysilicon control gate of the third gate structure serves as a second control gate of the memory cell.
The storage unit comprises two storage bits, the floating gate of the first grid structure is the first storage bit, and the floating gate of the third grid structure is the second storage bit.
Each memory cell is arranged in rows and columns to form an array structure, and the array structure is as follows:
the memory unit comprises two control lines and a word line, wherein the first control gate of each memory unit is connected to the corresponding first control line, the selection gates are connected to the corresponding word line, and the second control gates are connected to the corresponding second control line.
All the memory cells in the same column are connected in series, and the series structure is as follows: except for the first row and the last row with the maximum row numerical value, the first source drain region of each row of the storage units is connected with the second source drain region of the storage unit in the previous adjacent row, and the second source drain region of each row of the storage units is connected with the first source drain region of the storage unit in the next adjacent row.
The memory cells in the same column are connected with two bit lines, the first source drain regions of the memory cells in the odd-numbered rows and the second source drain regions of the memory cells in the even-numbered rows are connected to a first bit line, and the second source drain regions of the memory cells in the odd-numbered rows and the first source drain regions of the memory cells in the even-numbered rows are connected to a second bit line.
The operation method of the memory comprises inference operation, wherein input signals of the inference operation adopt input currents of the word lines in each row, and output signals of the inference operation of the memory adopt output voltages of bit lines corresponding to each column.
In a further improvement, in the inference operation of the memory, the first working state of the same column is:
the storage bit corresponding to the source drain region connected with the first bit line is a selected storage bit, the storage bit corresponding to the source drain region connected with the second bit line is an unselected storage bit, the control line corresponding to each selected storage bit is connected with 0V voltage, the control line corresponding to each unselected storage bit is connected with a first positive voltage, the size of the first positive voltage meets the requirement that the surface of the channel region at the bottom of the unselected storage bit is inverted to form a channel, the first bit line is connected with 0V voltage, and each word line is connected with the input current to serve as the input signal, so that the output signal is formed by the second bit line.
In a further improvement, in the inference operation of the memory, the second working state of the same column is:
the storage bit corresponding to the source drain region connected with the second bit line is a selected storage bit, the storage bit corresponding to the source drain region connected with the first bit line is an unselected storage bit, the control line corresponding to each selected storage bit is connected with 0V voltage, the control line corresponding to each unselected storage bit is connected with a first positive voltage, the size of the first positive voltage meets the requirement that the surface of the channel region at the bottom of the unselected storage bit is inverted to form a channel, the second bit line is connected with 0V voltage, and each word line is connected with the input current to serve as the input signal, so that the output signal is formed by the first bit line.
In a further improvement, the operation method of the memory further includes a learning operation, where the learning operation includes a weight increasing operation, and in the weight increasing operation, the operating states of the same column are:
each word line is connected to a second positive voltage.
Each control line is connected with a first negative voltage; the second positive voltage is greater than the first positive voltage, and the difference between the second positive voltage and the first negative voltage is of a magnitude sufficient to effect erasure of each of the storage bits.
Each of the bit lines is connected with a voltage of 0V.
In a further improvement, the learning operation includes a weight reduction operation, and in the weight reduction operation, the first operating state of the same column is:
the storage bit corresponding to the source-drain region connected with the first bit line is a selected storage bit, the storage bit corresponding to the source-drain region connected with the second bit line is an unselected storage bit, and the control line corresponding to each selected storage bit is connected with a third positive voltage.
The control line corresponding to each unselected storage bit is connected with a first positive voltage.
Each of the word lines is connected to a fourth positive voltage.
The first bit line is connected to a fifth positive voltage.
The second bit line is connected to a write current.
The fourth positive voltage enables the surface of the channel region at the bottom of the second grid structure to be inverted to form a channel, and the third positive voltage, the fifth positive voltage and the write current enable source-end hot electron injection programming of the selected storage bit.
The learning operation comprises a weight reduction operation, and in the weight reduction operation, the second working state of the same column is as follows:
the storage bit corresponding to the source-drain region connected with the second bit line is a selected storage bit, the storage bit corresponding to the source-drain region connected with the first bit line is an unselected storage bit, and the control line corresponding to each selected storage bit is connected with a third positive voltage.
The control line corresponding to each unselected storage bit is connected with a first positive voltage.
Each of the word lines is connected to a fourth positive voltage.
The first bit line is coupled to a write current.
The second bit line is connected with a fifth positive voltage.
In a further refinement, in a first operating state of the same column in the speculative operation of the memory, the output signal is determined by an output current from the second bit line, the output current of the second bit line being an accumulated value of the input current of each word line multiplied by a corresponding coefficient, the coefficient by which the input current of each word line is multiplied being determined by the programming depth of the corresponding memory bit.
In a further refinement, in a second operating state of the same column in the speculative operation of the memory, the output signal is determined from an output current from the first bit line, the output current of the first bit line being an accumulated value of the input current of each word line multiplied by a corresponding coefficient, the coefficient by which the input current of each word line is multiplied being determined by the programming depth of the corresponding memory bit.
The memory cell of the memory adopts a structure of three grid structures and two source-drain regions, the same row in the array structure comprises two control lines and a word line which are respectively connected with the control grid and the selection grid corresponding to the memory cell, the memory cells in the same column are connected in series, the memory cells in the same column are connected with two bit lines, the first source-drain regions of the memory cells in the odd-numbered rows and the second source-drain regions of the memory cells in the even-numbered rows are both connected with the first bit line, the second source-drain regions of the memory cells in the odd-numbered rows and the first source-drain regions of the memory cells in the even-numbered rows are both connected with the second bit line, the memory cell structure and the array structure of the memory can realize inference operation, and the input signal of the inference operation adopts the input current of the word line of each row and the output signal adopts the output voltage of the bit line corresponding to each column, so the invention can realize the operation of arithmetic integration.
The invention can also realize corresponding learning operation in the calculation integration operation, including weight increasing operation and weight reducing operation.
Drawings
The invention is described in further detail below with reference to the following figures and detailed description:
FIG. 1 is a block diagram of a memory cell of a conventional memory;
FIG. 2 is a diagram of an array structure of a memory according to an embodiment of the invention.
Detailed Description
The memory of the embodiment of the invention comprises:
fig. 2 is an array structure diagram of a memory according to an embodiment of the present invention, where the memory according to an embodiment of the present invention includes a plurality of memory cells 1, each memory cell 1 includes three gate structures and two source/drain regions, the gate structures are a first gate structure 104, a second gate structure 105, and a third gate structure 106, and the source/drain regions are a first source/drain region 102 and a second source/drain region 103, respectively.
The first gate structure 104 is formed by overlapping a first gate dielectric layer 107, a floating gate 108, a second gate dielectric layer 109 and a polysilicon control gate 110 which are formed on the surface of the semiconductor substrate 101.
The second gate structure 105 is composed of a third gate dielectric layer 111 and a polysilicon gate 112 formed on the surface of the semiconductor substrate 101.
The third gate structure 106 is formed by overlapping a first gate dielectric layer 107, a floating gate 108, a second gate dielectric layer 109 and a polysilicon control gate 110 formed on the surface of the semiconductor substrate 101.
In the embodiment of the present invention, the semiconductor substrate 101 is a silicon substrate, and the first gate dielectric layer 107, the second gate dielectric layer 109, and the third gate dielectric layer 111 are all made of oxide layers.
A channel region is formed by the semiconductor substrate 101 located between the first source drain region 102 and the second source drain region 103.
The first gate structure 104, the second gate structure 105, and the third gate structure 106 are arranged on the surface of the channel region between the first source-drain region 102 and the second source-drain region 103, and the formation of a channel on the surface of the channel region is controlled by the first gate structure 104, the second gate structure 105, and the third gate structure 106.
The polysilicon control gate 110 of the first gate structure 104 serves as a first control gate CCG0 of the memory cell 1; the polysilicon gate 112 of the second gate structure 105 is used as a select gate CWL of the memory cell 1; the polysilicon control gate 110 of the third gate structure 106 serves as the second control gate CCG1 of the memory cell 1.
The memory cell 1 includes two memory bits, the floating gate 108 of the first gate structure 104 is a first memory bit, and the floating gate 108 of the third gate structure 106 is a second memory bit.
Each memory cell 1 is arranged in rows and columns to form an array structure, and the array structure is as follows:
two control lines and a word line are included in the same row, the first control gate CCG0 of each memory cell 1 is connected to the corresponding first control line, the select gates CWL are connected to the corresponding word line, and the second control gate CCG1 is connected to the corresponding second control line.
The memory cells 1 in the same column are connected in series and the series structure is: except for the first row and the last row with the maximum row value, the first source-drain regions 102 of the memory cells 1 in each row are connected with the second source-drain regions 103 of the memory cells 1 in the previous adjacent row, and the second source-drain regions 103 of the memory cells 1 in each row are connected with the first source-drain regions 102 of the memory cells 1 in the next adjacent row.
The memory cells 1 in the same column are connected to two bit lines, the first source-drain regions 102 of the memory cells 1 in the odd-numbered rows and the second source-drain regions 103 of the memory cells 1 in the even-numbered rows are both connected to a first bit line, and the second source-drain regions 103 of the memory cells 1 in the odd-numbered rows and the first source-drain regions 102 of the memory cells 1 in the even-numbered rows are both connected to a second bit line.
In fig. 2, the word lines in each row are denoted by WL plus row number, such as WL0, WL1, WL2, and the like.
The first control lines of each row are respectively represented by CG plus row number plus 0, such as CG00, CG10, CG20 and the like.
The second control lines of each row are respectively represented by CG plus a row number plus 1, such as CG01, CG11, CG21 and the like.
The first bit lines of each column are represented by BL plus column number plus 0, such as BL00, BL10, etc., respectively.
The second bit lines of each column are represented by BL plus column number plus 1, such as BL01, BL11, etc., respectively.
The operation of the memory includes an inferential operation whose input signal takes the input current of the word line for each row, generally denoted by X, where X and I areWL0、IWL1And IWL2And so on.
The output signal of the rational operation of the memory is represented by the output voltage of the corresponding bit line of each column, and generally, the output signal is represented by Y, where Y and VBL00、VBL10、VBL01And VBL11And so on.
In the inference operation of the memory, the first working state of the same column is:
and the storage bit corresponding to the source-drain region connected with the first bit line is a selected storage bit, the storage bit corresponding to the source-drain region connected with the second bit line is an unselected storage bit, and the first column, namely the column with the number of 0, is taken as an example: the selected memory bits are the memory bits corresponding to control lines CG00, CG11, CG20, respectively, and the unselected memory bits are the memory bits corresponding to control lines CG01, CG10, CG21, respectively.
The control line corresponding to each selected storage bit is connected with 0V voltage, the control line corresponding to each unselected storage bit is connected with a first positive voltage, the magnitude of the first positive voltage is enough to enable the surface of the channel region at the bottom of the unselected storage bit to be inverted to form a channel, the first bit line is connected with 0V voltage, each word line is connected with the input current as the input signal, and the output signal is formed from the second bit line.
In the embodiment of the present invention, in the first operation state of the same column in the speculative operation of the memory, the output signal is determined by an output current from the second bit line, the output current of the second bit line is an accumulated value obtained by adding the input current of each word line multiplied by a corresponding coefficient, and the coefficient multiplied by the input current of each word line is determined by the programming depth of the corresponding memory bit. Now, the following formula is described:
using I as input current corresponding to each word lineWLI for bit lines representing and forming said output signalBLExpressed, then there is a relationship between the input current and the current corresponding to the output signal that can be formulated as:
Figure GDA0002785977530000101
wherein y represents the current corresponding to the output signal, IiRepresenting the current I of the word line for a rowWLAnd beta denotes a coefficient determined by the programming depth of the memory bit corresponding to the memory cell, xiDenotes I after multiplication by a factor βi。
In the inference operation of the memory, the second working state of the same column is:
and the storage bit corresponding to the source drain region connected with the second bit line is a selected storage bit, and the storage bit corresponding to the source drain region connected with the first bit line is an unselected storage bit, taking the first column as an example: the selected memory bits are the memory bits corresponding to control lines CG01, CG10, CG21, respectively, and the unselected memory bits are the memory bits corresponding to control lines CG00, CG11, CG20, respectively.
The control line corresponding to each selected storage bit is connected with 0V voltage, the control line corresponding to each unselected storage bit is connected with a first positive voltage, the magnitude of the first positive voltage is enough to enable the surface of the channel region at the bottom of the unselected storage bit to be inverted to form a channel, the second bit line is connected with 0V voltage, each word line is connected with the input current as the input signal, and the output signal is formed from the first bit line.
In a second operating state of the same column in the speculative operation of the memory, the output signal is determined by an output current from the first bit line, the output current of the first bit line is an accumulated value of the input current of each word line multiplied by a corresponding coefficient, and the coefficient multiplied by the input current of each word line is determined by the programming depth of the corresponding memory bit.
The operation of the memory further comprises a learning operation, wherein the learning operation comprises a weight increasing operation, and in the weight increasing operation, the working state of the same column is as follows:
each word line is connected to a second positive voltage.
Each control line is connected with a first negative voltage; the second positive voltage is greater than the first positive voltage, and the difference between the second positive voltage and the first negative voltage is of a magnitude sufficient to effect erasure of each of the storage bits.
Each of the bit lines is connected with a voltage of 0V.
The learning operation comprises a Weight-losing (Weight down) operation, and in the Weight-losing operation, the first working state of the same column is as follows:
the storage bit corresponding to the source-drain region connected with the first bit line is a selected storage bit, the storage bit corresponding to the source-drain region connected with the second bit line is an unselected storage bit, and the control line corresponding to each selected storage bit is connected with a third positive voltage.
The control line corresponding to each unselected storage bit is connected with a first positive voltage.
Each of the word lines is connected to a fourth positive voltage.
The first bit line is connected to a fifth positive voltage.
The second bit line is connected to a write current.
The fourth positive voltage is sufficient to invert the surface of the channel region at the bottom of the second gate structure 105 to form a channel, and the third positive voltage, the fifth positive voltage and the write current are sufficient to implement source-side hot electron injection programming of the selected storage bit.
The learning operation comprises a weight reduction operation, and in the weight reduction operation, the second working state of the same column is as follows:
the storage bit corresponding to the source-drain region connected with the second bit line is a selected storage bit, the storage bit corresponding to the source-drain region connected with the first bit line is an unselected storage bit, and the control line corresponding to each selected storage bit is connected with a third positive voltage.
The control line corresponding to each unselected storage bit is connected with a first positive voltage.
Each of the word lines is connected to a fourth positive voltage.
The first bit line is coupled to a write current.
The second bit line is connected with a fifth positive voltage.
The following description of the various voltage levels used in the embodiments of the present invention is given with a specific parameter:
the first positive voltage is 5V, the second positive voltage is 6V, the third positive voltage is 7V, the fourth positive voltage is 1.4V, the fifth positive voltage is 4.5V, the first negative voltage is-6V, and the write current is generally denoted by Idp.
The memory unit 1 of the memory of the embodiment of the invention adopts a structure of three grid structures and two source-drain regions, the same row in the array structure comprises two control lines and a word line which are respectively connected with the control grid and the selection grid CWL corresponding to the memory unit 1, the memory units 1 in the same column are connected in series, the memory units 1 in the same column are connected with two bit lines, the first source-drain regions 102 of the memory units 1 in the odd-numbered rows and the second source-drain regions 103 of the memory units 1 in the even-numbered rows are both connected with a first bit line, the second source-drain regions 103 of the memory units 1 in the odd-numbered rows and the first source-drain regions 102 of the memory units 1 in the even-numbered rows are both connected with a second bit line, the memory unit 1 structure and the array structure of the memory of the invention can realize inference operation, and the input signal of the inference operation adopts the input current of the word line in each row and the output signal adopts the output, embodiments of the present invention enable a computationally efficient operation.
The embodiment of the invention can also realize corresponding learning operation in the storage and calculation integrated operation, including weight increasing operation and weight reducing operation.
The operation method of the memory of the embodiment of the invention comprises the following steps:
the memory in the operation method of the memory in the embodiment of the invention comprises a plurality of memory units 1, each memory unit 1 comprises three gate structures and two source-drain regions, the gate structures are respectively a first gate structure 104, a second gate structure 105 and a third gate structure 106, and the source-drain regions are respectively a first source-drain region 102 and a second source-drain region 103.
The first gate structure 104 is formed by overlapping a first gate dielectric layer 107, a floating gate 108, a second gate dielectric layer 109 and a polysilicon control gate 110 which are formed on the surface of the semiconductor substrate 101.
The second gate structure 105 is composed of a third gate dielectric layer 111 and a polysilicon gate 112 formed on the surface of the semiconductor substrate 101.
The third gate structure 106 is formed by overlapping a first gate dielectric layer 107, a floating gate 108, a second gate dielectric layer 109 and a polysilicon control gate 110 formed on the surface of the semiconductor substrate 101.
A channel region is formed by the semiconductor substrate 101 located between the first source drain region 102 and the second source drain region 103.
The first gate structure 104, the second gate structure 105, and the third gate structure 106 are arranged on the surface of the channel region between the first source-drain region 102 and the second source-drain region 103, and the formation of a channel on the surface of the channel region is controlled by the first gate structure 104, the second gate structure 105, and the third gate structure 106.
The polysilicon control gate 110 of the first gate structure 104 serves as a first control gate CCG0 of the memory cell 1; the polysilicon gate 112 of the second gate structure 105 is used as a select gate CWL of the memory cell 1; the polysilicon control gate 110 of the third gate structure 106 serves as the second control gate CCG1 of the memory cell 1.
The memory cell 1 includes two memory bits, the floating gate 108 of the first gate structure 104 is a first memory bit, and the floating gate 108 of the third gate structure 106 is a second memory bit.
Each memory cell 1 is arranged in rows and columns to form an array structure, and the array structure is as follows:
two control lines and a word line are included in the same row, the first control gate CCG0 of each memory cell 1 is connected to the corresponding first control line, the select gates CWL are connected to the corresponding word line, and the second control gate CCG1 is connected to the corresponding second control line.
The memory cells 1 in the same column are connected in series and the series structure is: except for the first row and the last row with the maximum row value, the first source-drain regions 102 of the memory cells 1 in each row are connected with the second source-drain regions 103 of the memory cells 1 in the previous adjacent row, and the second source-drain regions 103 of the memory cells 1 in each row are connected with the first source-drain regions 102 of the memory cells 1 in the next adjacent row.
The memory cells 1 in the same column are connected to two bit lines, the first source-drain regions 102 of the memory cells 1 in the odd-numbered rows and the second source-drain regions 103 of the memory cells 1 in the even-numbered rows are both connected to a first bit line, and the second source-drain regions 103 of the memory cells 1 in the odd-numbered rows and the first source-drain regions 102 of the memory cells 1 in the even-numbered rows are both connected to a second bit line.
The operation method of the memory comprises inference operation, wherein input signals of the inference operation adopt input currents of the word lines in each row, and output signals of the inference operation of the memory adopt output voltages of bit lines corresponding to each column.
In the inference operation of the memory, the first working state of the same column is:
the storage bit corresponding to the source drain region connected with the first bit line is a selected storage bit, the storage bit corresponding to the source drain region connected with the second bit line is an unselected storage bit, the control line corresponding to each selected storage bit is connected with 0V voltage, the control line corresponding to each unselected storage bit is connected with a first positive voltage, the size of the first positive voltage meets the requirement that the surface of the channel region at the bottom of the unselected storage bit is inverted to form a channel, the first bit line is connected with 0V voltage, and each word line is connected with the input current to serve as the input signal, so that the output signal is formed by the second bit line.
In a first operating state of the same column in the speculative operation of the memory, the output signal is determined by an output current from the second bit line, the output current of the second bit line is an accumulated value of the input current of each word line multiplied by a corresponding coefficient, and the coefficient multiplied by the input current of each word line is determined by the programming depth of the corresponding memory bit.
In the inference operation of the memory, the second working state of the same column is:
the storage bit corresponding to the source drain region connected with the second bit line is a selected storage bit, the storage bit corresponding to the source drain region connected with the first bit line is an unselected storage bit, the control line corresponding to each selected storage bit is connected with 0V voltage, the control line corresponding to each unselected storage bit is connected with a first positive voltage, the size of the first positive voltage meets the requirement that the surface of the channel region at the bottom of the unselected storage bit is inverted to form a channel, the second bit line is connected with 0V voltage, and each word line is connected with the input current to serve as the input signal, so that the output signal is formed by the first bit line.
In a second operating state of the same column in the speculative operation of the memory, the output signal is determined by an output current from the first bit line, the output current of the first bit line is an accumulated value of the input current of each word line multiplied by a corresponding coefficient, and the coefficient multiplied by the input current of each word line is determined by the programming depth of the corresponding memory bit.
The operation method of the memory further comprises a learning operation, wherein the learning operation comprises a weight increasing operation, and in the weight increasing operation, the working states of the same column are as follows:
each word line is connected to a second positive voltage.
Each control line is connected with a first negative voltage; the second positive voltage is greater than the first positive voltage, and the difference between the second positive voltage and the first negative voltage is of a magnitude sufficient to effect erasure of each of the storage bits.
Each of the bit lines is connected with a voltage of 0V.
The learning operation comprises a weight reduction operation, wherein in the weight reduction operation, the first working state of the same column is as follows:
the storage bit corresponding to the source-drain region connected with the first bit line is a selected storage bit, the storage bit corresponding to the source-drain region connected with the second bit line is an unselected storage bit, and the control line corresponding to each selected storage bit is connected with a third positive voltage.
The control line corresponding to each unselected storage bit is connected with a first positive voltage.
Each of the word lines is connected to a fourth positive voltage.
The first bit line is connected to a fifth positive voltage.
The second bit line is connected to a write current.
The fourth positive voltage is sufficient to invert the surface of the channel region at the bottom of the second gate structure 105 to form a channel, and the third positive voltage, the fifth positive voltage and the write current are sufficient to implement source-side hot electron injection programming of the selected storage bit.
The learning operation comprises a weight reduction operation, and in the weight reduction operation, the second working state of the same column is as follows:
the storage bit corresponding to the source-drain region connected with the second bit line is a selected storage bit, the storage bit corresponding to the source-drain region connected with the first bit line is an unselected storage bit, and the control line corresponding to each selected storage bit is connected with a third positive voltage.
The control line corresponding to each unselected storage bit is connected with a first positive voltage.
Each of the word lines is connected to a fourth positive voltage.
The first bit line is coupled to a write current.
The second bit line is connected with a fifth positive voltage.
The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.

Claims (15)

1. A memory, characterized by: the memory comprises a plurality of memory units, wherein each memory unit comprises three grid structures and two source drain regions, the grid structures are respectively a first grid structure, a second grid structure and a third grid structure, and the source drain regions are respectively a first source drain region and a second source drain region;
the first grid structure is formed by overlapping a first grid dielectric layer, a floating grid, a second grid dielectric layer and a polycrystalline silicon control grid which are formed on the surface of the semiconductor substrate;
the second grid structure consists of a third grid dielectric layer and a polysilicon grid which are formed on the surface of the semiconductor substrate;
the third grid structure is formed by overlapping a first grid dielectric layer, a floating grid, a second grid dielectric layer and a polycrystalline silicon control grid which are formed on the surface of the semiconductor substrate;
forming a channel region by the semiconductor substrate between the first source drain region and the second source drain region;
the first gate structure, the second gate structure and the third gate structure are arranged on the surface of the channel region between the first source drain region and the second source drain region, and the first gate structure, the second gate structure and the third gate structure jointly control the formation of a channel on the surface of the channel region;
the polysilicon control gate of the first gate structure is used as a first control gate of the memory cell; the polysilicon gate of the second gate structure is used as a selection gate of the storage unit; the polysilicon control gate of the third gate structure is used as a second control gate of the memory cell;
the storage unit comprises two storage bits, the floating gate of the first grid structure is a first storage bit, and the floating gate of the third grid structure is a second storage bit;
each memory cell is arranged in rows and columns to form an array structure, and the array structure is as follows:
the memory cell comprises two control lines and a word line in the same row, wherein the first control gate of each memory cell is connected to the corresponding first control line, the selection gates are connected to the corresponding word line, and the second control gates are connected to the corresponding second control lines;
all the memory cells in the same column are connected in series, and the series structure is as follows: except for the first row and the last row with the maximum row numerical value, the first source drain region of each row of the storage units is connected with the second source drain region of the storage unit in the previous adjacent row, and the second source drain region of each row of the storage units is connected with the first source drain region of the storage unit in the next adjacent row;
the memory cells in the same column are connected with two bit lines, the first source drain regions of the memory cells in the odd-numbered rows and the second source drain regions of the memory cells in the even-numbered rows are connected to a first bit line, and the second source drain regions of the memory cells in the odd-numbered rows and the first source drain regions of the memory cells in the even-numbered rows are connected to a second bit line;
the operation of the memory comprises inference operation, wherein input signals of the inference operation adopt input currents of the word lines in each row, and output signals of the inference operation of the memory adopt output voltages of bit lines corresponding to each column.
2. The memory of claim 1, wherein: in the inference operation of the memory, the first working state of the same column is:
the storage bit corresponding to the source drain region connected with the first bit line is a selected storage bit, the storage bit corresponding to the source drain region connected with the second bit line is an unselected storage bit, the control line corresponding to each selected storage bit is connected with 0V voltage, the control line corresponding to each unselected storage bit is connected with a first positive voltage, the size of the first positive voltage meets the requirement that the surface of the channel region at the bottom of the unselected storage bit is inverted to form a channel, the first bit line is connected with 0V voltage, and each word line is connected with the input current to serve as the input signal, so that the output signal is formed by the second bit line.
3. The memory of claim 2, wherein: in the inference operation of the memory, the second working state of the same column is:
the storage bit corresponding to the source drain region connected with the second bit line is a selected storage bit, the storage bit corresponding to the source drain region connected with the first bit line is an unselected storage bit, the control line corresponding to each selected storage bit is connected with 0V voltage, the control line corresponding to each unselected storage bit is connected with a first positive voltage, the size of the first positive voltage meets the requirement that the surface of the channel region at the bottom of the unselected storage bit is inverted to form a channel, the second bit line is connected with 0V voltage, and each word line is connected with the input current to serve as the input signal so as to form the output signal from the first bit line.
4. The memory of claim 3, wherein: the operation of the memory further comprises a learning operation, wherein the learning operation comprises a weight increasing operation, and in the weight increasing operation, the working state of the same column is as follows:
each word line is connected with a second positive voltage;
each control line is connected with a first negative voltage; the second positive voltage is greater than the first positive voltage, and the difference between the second positive voltage and the first negative voltage is of a magnitude sufficient to effect erasure of each of the storage bits;
each of the bit lines is connected with a voltage of 0V.
5. The memory of claim 4, wherein: the learning operation comprises a weight reduction operation, wherein in the weight reduction operation, the first working state of the same column is as follows:
the storage bit corresponding to the source drain region connected with the first bit line is a selected storage bit, the storage bit corresponding to the source drain region connected with the second bit line is an unselected storage bit, and the control line corresponding to each selected storage bit is connected with a third positive voltage;
the control line corresponding to each unselected storage bit is connected with a first positive voltage;
each word line is connected with a fourth positive voltage;
the first bit line is connected with a fifth positive voltage;
the second bit line is connected with a write current;
the fourth positive voltage enables the surface of the channel region at the bottom of the second grid structure to be inverted to form a channel, and the third positive voltage, the fifth positive voltage and the write current enable source-end hot electron injection programming of the selected storage bit.
6. The memory of claim 5, wherein: the learning operation comprises a weight reduction operation, and in the weight reduction operation, the second working state of the same column is as follows:
the storage bit corresponding to the source drain region connected with the second bit line is a selected storage bit, the storage bit corresponding to the source drain region connected with the first bit line is an unselected storage bit, and the control line corresponding to each selected storage bit is connected with a third positive voltage;
the control line corresponding to each unselected storage bit is connected with a first positive voltage;
each word line is connected with a fourth positive voltage;
the first bit line is connected with a write current;
the second bit line is connected with a fifth positive voltage.
7. The memory of claim 2, wherein: in a first operating state of the same column in the speculative operation of the memory, the output signal is determined by an output current from the second bit line, the output current of the second bit line is an accumulated value of the input current of each word line multiplied by a corresponding coefficient, and the coefficient multiplied by the input current of each word line is determined by the programming depth of the corresponding memory bit.
8. The memory of claim 3, wherein: in a second operating state of the same column in the speculative operation of the memory, the output signal is determined by an output current from the first bit line, the output current of the first bit line is an accumulated value of the input current of each word line multiplied by a corresponding coefficient, and the coefficient multiplied by the input current of each word line is determined by the programming depth of the corresponding memory bit.
9. A method of operating a memory, comprising: the memory comprises a plurality of memory units, each memory unit comprises three grid structures and two source-drain regions, the grid structures are respectively a first grid structure, a second grid structure and a third grid structure, and the source-drain regions are respectively a first source-drain region and a second source-drain region;
the first grid structure is formed by overlapping a first grid dielectric layer, a floating grid, a second grid dielectric layer and a polycrystalline silicon control grid which are formed on the surface of the semiconductor substrate;
the second grid structure consists of a third grid dielectric layer and a polysilicon grid which are formed on the surface of the semiconductor substrate;
the third grid structure is formed by overlapping a first grid dielectric layer, a floating grid, a second grid dielectric layer and a polycrystalline silicon control grid which are formed on the surface of the semiconductor substrate;
forming a channel region by the semiconductor substrate between the first source drain region and the second source drain region;
the first gate structure, the second gate structure and the third gate structure are arranged on the surface of the channel region between the first source drain region and the second source drain region, and the first gate structure, the second gate structure and the third gate structure jointly control the formation of a channel on the surface of the channel region;
the polysilicon control gate of the first gate structure is used as a first control gate of the memory cell; the polysilicon gate of the second gate structure is used as a selection gate of the storage unit; the polysilicon control gate of the third gate structure is used as a second control gate of the memory cell;
the storage unit comprises two storage bits, the floating gate of the first grid structure is a first storage bit, and the floating gate of the third grid structure is a second storage bit;
each memory cell is arranged in rows and columns to form an array structure, and the array structure is as follows:
the memory cell comprises two control lines and a word line in the same row, wherein the first control gate of each memory cell is connected to the corresponding first control line, the selection gates are connected to the corresponding word line, and the second control gates are connected to the corresponding second control lines;
all the memory cells in the same column are connected in series, and the series structure is as follows: except for the first row and the last row with the maximum row numerical value, the first source drain region of each row of the storage units is connected with the second source drain region of the storage unit in the previous adjacent row, and the second source drain region of each row of the storage units is connected with the first source drain region of the storage unit in the next adjacent row;
the memory cells in the same column are connected with two bit lines, the first source drain regions of the memory cells in the odd-numbered rows and the second source drain regions of the memory cells in the even-numbered rows are connected to a first bit line, and the second source drain regions of the memory cells in the odd-numbered rows and the first source drain regions of the memory cells in the even-numbered rows are connected to a second bit line;
the operation method of the memory comprises inference operation, wherein input signals of the inference operation adopt input currents of the word lines in each row, and output signals of the inference operation of the memory adopt output voltages of bit lines corresponding to each column.
10. The method of operating a memory of claim 9, wherein: in the inference operation of the memory, the first working state of the same column is:
the storage bit corresponding to the source drain region connected with the first bit line is a selected storage bit, the storage bit corresponding to the source drain region connected with the second bit line is an unselected storage bit, the control line corresponding to each selected storage bit is connected with 0V voltage, the control line corresponding to each unselected storage bit is connected with a first positive voltage, the size of the first positive voltage meets the requirement that the surface of the channel region at the bottom of the unselected storage bit is inverted to form a channel, the first bit line is connected with 0V voltage, and each word line is connected with the input current to serve as the input signal, so that the output signal is formed by the second bit line.
11. The method of operating a memory of claim 10, wherein: in the inference operation of the memory, the second working state of the same column is:
the storage bit corresponding to the source drain region connected with the second bit line is a selected storage bit, the storage bit corresponding to the source drain region connected with the first bit line is an unselected storage bit, the control line corresponding to each selected storage bit is connected with 0V voltage, the control line corresponding to each unselected storage bit is connected with a first positive voltage, the size of the first positive voltage meets the requirement that the surface of the channel region at the bottom of the unselected storage bit is inverted to form a channel, the second bit line is connected with 0V voltage, and each word line is connected with the input current to serve as the input signal so as to form the output signal from the first bit line.
12. The method of operating a memory of claim 11, wherein: the operation method of the memory further comprises a learning operation, wherein the learning operation comprises a weight increasing operation, and in the weight increasing operation, the working states of the same column are as follows:
each word line is connected with a second positive voltage;
each control line is connected with a first negative voltage; the second positive voltage is greater than the first positive voltage, and the difference between the second positive voltage and the first negative voltage is of a magnitude sufficient to effect erasure of each of the storage bits;
each of the bit lines is connected with a voltage of 0V.
13. The method of operating a memory of claim 12, wherein: the learning operation comprises a weight reduction operation, wherein in the weight reduction operation, the first working state of the same column is as follows:
the storage bit corresponding to the source drain region connected with the first bit line is a selected storage bit, the storage bit corresponding to the source drain region connected with the second bit line is an unselected storage bit, and the control line corresponding to each selected storage bit is connected with a third positive voltage;
the control line corresponding to each unselected storage bit is connected with a first positive voltage;
each word line is connected with a fourth positive voltage;
the first bit line is connected with a fifth positive voltage;
the second bit line is connected with a write current;
the fourth positive voltage enables the surface of the channel region at the bottom of the second grid structure to be inverted to form a channel, and the third positive voltage, the fifth positive voltage and the write current enable source-end hot electron injection programming of the selected storage bit;
the learning operation comprises a weight reduction operation, and in the weight reduction operation, the second working state of the same column is as follows:
the storage bit corresponding to the source drain region connected with the second bit line is a selected storage bit, the storage bit corresponding to the source drain region connected with the first bit line is an unselected storage bit, and the control line corresponding to each selected storage bit is connected with a third positive voltage;
the control line corresponding to each unselected storage bit is connected with a first positive voltage;
each word line is connected with a fourth positive voltage;
the first bit line is connected with a write current;
the second bit line is connected with a fifth positive voltage.
14. The method of operating a memory of claim 10, wherein: in a first operating state of the same column in the speculative operation of the memory, the output signal is determined by an output current from the second bit line, the output current of the second bit line is an accumulated value of the input current of each word line multiplied by a corresponding coefficient, and the coefficient multiplied by the input current of each word line is determined by the programming depth of the corresponding memory bit.
15. The method of operating a memory of claim 11, wherein: in a second operating state of the same column in the speculative operation of the memory, the output signal is determined by an output current from the first bit line, the output current of the first bit line is an accumulated value of the input current of each word line multiplied by a corresponding coefficient, and the coefficient multiplied by the input current of each word line is determined by the programming depth of the corresponding memory bit.
CN201910297081.9A 2019-04-15 2019-04-15 Memory and operation method thereof Active CN110137173B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201910297081.9A CN110137173B (en) 2019-04-15 2019-04-15 Memory and operation method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201910297081.9A CN110137173B (en) 2019-04-15 2019-04-15 Memory and operation method thereof

Publications (2)

Publication Number Publication Date
CN110137173A CN110137173A (en) 2019-08-16
CN110137173B true CN110137173B (en) 2021-01-22

Family

ID=67569890

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201910297081.9A Active CN110137173B (en) 2019-04-15 2019-04-15 Memory and operation method thereof

Country Status (1)

Country Link
CN (1) CN110137173B (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112558917B (en) * 2019-09-10 2021-07-27 珠海博雅科技有限公司 Integrated storage and calculation circuit and data calculation method based on integrated storage and calculation circuit
CN113129940A (en) * 2019-12-30 2021-07-16 北京兆易创新科技股份有限公司 Flash memory and manufacturing method thereof
CN111640461B (en) * 2020-05-22 2021-12-03 福建省晋华集成电路有限公司 Operation method of DRAM
CN112017701B (en) * 2020-08-26 2023-02-17 珠海博雅科技股份有限公司 Threshold voltage adjusting device and threshold voltage adjusting method
CN113689893A (en) * 2021-08-26 2021-11-23 北京磐芯微电子科技有限公司 Flash memory array

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6093600A (en) * 1999-10-29 2000-07-25 United Silicon, Inc. Method of fabricating a dynamic random-access memory device
US8873302B2 (en) * 2011-10-28 2014-10-28 Invensas Corporation Common doped region with separate gate control for a logic compatible non-volatile memory cell
CN103000218A (en) * 2012-11-20 2013-03-27 上海宏力半导体制造有限公司 Memory circuit
CN106057239B (en) * 2016-05-27 2019-11-22 上海华虹宏力半导体制造有限公司 The operation scheme for programming of flash array
CN106846239B (en) * 2017-01-12 2019-10-22 北京大学 Realize the code-shaped flash memory system and working method of image convolution
CN108346448B (en) * 2018-03-14 2020-12-04 上海华虹宏力半导体制造有限公司 Flash memory and control method thereof
CN108777155B (en) * 2018-08-02 2024-07-05 杭州知存算力科技有限公司 Flash memory chip

Also Published As

Publication number Publication date
CN110137173A (en) 2019-08-16

Similar Documents

Publication Publication Date Title
CN110137173B (en) Memory and operation method thereof
US7133316B2 (en) Program/erase method for P-channel charge trapping memory device
KR100391404B1 (en) Semiconductor memory
EP0725403B1 (en) Improved reading non-volatile semiconductor memory device
JP5595901B2 (en) Nonvolatile semiconductor memory device
CN109817624B (en) Memory and operation method thereof
CN104246894B (en) The method for reducing the programming interference in Nonvolatile memery unit
US11017851B1 (en) Silicon-oxide-nitride-oxide-silicon based multi level non-volatile memory device and methods of operation thereof
US20150043279A1 (en) Semiconductor memory device
US10424384B2 (en) Semiconductor memory device and control method of semiconductor memory device
TW201503258A (en) Structure and method for manufacture of memory device with thin silicon body
JP2009271966A (en) Nonvolatile semiconductor memory
US20050030793A1 (en) Method for operating a nor-array memory module composed of p-type memory cells
JPH113595A (en) Non-volatile semiconductor memory
CN115249502A (en) NOR flash memory array and data writing method, reading method and erasing method thereof
US5467307A (en) Memory array utilizing low voltage Fowler-Nordheim Flash EEPROM cell
CN102067235A (en) NADN based NMOS NOR flash memory cell, a NADN based NMOS NOR flash memory array, and a method of forming a nand based nmos nor flash memory array
JP5166095B2 (en) Nonvolatile semiconductor memory device driving method and nonvolatile semiconductor memory device
CN108492844B (en) Double-split gate flash memory array and programming method thereof
US20060138528A1 (en) Charge trap insulator memory device
US20120014183A1 (en) 3 transistor (n/p/n) non-volatile memory cell without program disturb
JPH09139483A (en) Non-volatile semiconductor storage device
TWI839588B (en) Silicon-oxide-nitride-oxide-silicon based multi-level non-volatile memory device and methods of operation thereof
WO2024134770A1 (en) Memory device using semiconductor element
JP2827607B2 (en) Semiconductor storage device

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant