CN106057239B - The operation scheme for programming of flash array - Google Patents
The operation scheme for programming of flash array Download PDFInfo
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- CN106057239B CN106057239B CN201610364752.5A CN201610364752A CN106057239B CN 106057239 B CN106057239 B CN 106057239B CN 201610364752 A CN201610364752 A CN 201610364752A CN 106057239 B CN106057239 B CN 106057239B
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- grid
- flash memory
- memory unit
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- sharing flash
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
- G11C16/3427—Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
Abstract
A kind of operation scheme for programming of flash array, flash array include at least the first and second grid-sharing flash memory units, and the first and second grid-sharing flash memory units are respectively provided with source electrode, drain electrode, the first control gate, wordline grid and the second control gate；The source electrode of first grid-sharing flash memory unit connects the first bit line, drain electrode the second bit line of connection；The source electrode of second grid-sharing flash memory unit connects the second bit line, drain electrode the first bit line of connection, alternatively, the source electrode of the second grid-sharing flash memory unit connects the first bit line, drain electrode the second bit line of connection；Operation scheme for programming includes: to apply the first control grid line that the first negative electricity is depressed into the second grid-sharing flash memory unit when being programmed operation to the first grid-sharing flash memory unit, and apply the second control grid line that the second negative electricity is depressed into the second grid-sharing flash memory unit；The programming for being configured to the second grid-sharing flash memory unit of limitation of first negative voltage and the second negative voltage.The present invention program can reduce programming interference of the flash array in programming operation, and be easier to implement.
Description
Technical field
The present invention relates to memory technology field, in particular to a kind of operation scheme for programming of flash array.
Background technique
Flash memory (Flash) is used as a kind of nonvolatile memory, it has also become the mainstream of non-volatile semiconductor storage technology.
In various Flash devices, it is divided into two types substantially: stacked gate structure and grid dividing structure, wherein stacked gate structure exists
Erasing problem is crossed, so that its complex circuit designs；In contrast, grid dividing structure effectively prevented erasure effect, so that circuit
It designs relatively easy.In addition, comparing stacked gate structure, grid dividing structure is programmed using the injection of source thermoelectron, is had higher
Programming efficiency, so that split-gate type flash memory is widely used in the production of the electronics such as all kinds of smart cards, SIM card, microcontroller, mobile phone
In product.
In the prior art, in order to save the area of flash array, multiple flash cells are generally set in flash array
Share bit lines, for example, flash array includes multiple grid-sharing flash memory units, the multiple grid-sharing flash memory unit share bit lines.When it
In grid-sharing flash memory unit when being programmed, two bit lines of connection will be applied certain program voltage, and shared
The grid-sharing flash memory unit of bit line also may be at programmed state simultaneously；If the grid-sharing flash memory unit of shared bit line at this time
Channel in add up have the electronics of enough flowings, and it is described on the direction that it controls grid line to there is certain voltage to make
The electronics of flowing can be pulled to floating gate, then, unnecessary programing effect will be caused at this time, cause programming interference.
It therefore, in the prior art include that the flash array of grid-sharing flash memory unit has the problem of programming interference.
Summary of the invention
Present invention solves the technical problem that the problem of being how to prevent the programming interference in flash array.
In order to solve the above technical problems, the embodiment of the present invention provides a kind of operation scheme for programming of flash array, the sudden strain of a muscle
Array is deposited including at least the first grid-sharing flash memory unit and the second grid-sharing flash memory unit, first grid-sharing flash memory unit and second point
Flash memory in grating unit is respectively provided with source electrode, drain electrode, the first control gate, wordline grid and the second control gate；The first grid flash memory list
The source electrode of member connects the first bit line, and the drain electrode of first grid-sharing flash memory unit connects the second bit line；Second grid flash memory
The source electrode of unit connects second bit line, and the drain electrode of second grid-sharing flash memory unit connects first bit line, alternatively, institute
The source electrode for stating the second grid-sharing flash memory unit connects first bit line, the drain electrode connection of second grid-sharing flash memory unit described the
Two bit lines；First control gate of first grid-sharing flash memory unit and the second grid-sharing flash memory unit is separately connected respective first control
Second control gate of grid line processed, first grid-sharing flash memory unit and the second grid-sharing flash memory unit is separately connected respective second control
The wordline grid of grid line processed, first grid-sharing flash memory unit and the second grid-sharing flash memory unit are separately connected respective wordline.
The operation scheme for programming of the flash array includes: to be programmed operation to first grid-sharing flash memory unit
When, apply the first control grid line that the first negative electricity is depressed into second grid-sharing flash memory unit, and apply the second negative electricity be depressed into it is described
Second control grid line of the second grid-sharing flash memory unit；First negative voltage and second negative voltage are configured to limitation institute
State the programming of the second grid-sharing flash memory unit.
Optionally, the operation scheme for programming of the flash array further include: apply tertiary voltage to second point of grid and dodge
The wordline of memory cell, first negative voltage are lower than the tertiary voltage, and second negative voltage is lower than the tertiary voltage.
Optionally, the voltage range of first negative voltage is -0.1V to -3V.
Optionally, the voltage range of second negative voltage is -0.1V to -3V.
Optionally, the voltage range of the tertiary voltage is 0~1V.
Optionally, being programmed operation to first grid-sharing flash memory unit includes: to apply the voltage that range is 3V~6V
To first bit line；Apply program current that range is 1 μ of μ A~4 A to second bit line；Applying range is 6V~10V's
Voltage to first grid-sharing flash memory unit first control grid line；Apply voltage that range is 3V~6V to first point of grid
Second control grid line of flash cell；Apply range be 1V~2V voltage to first grid-sharing flash memory unit wordline.
Optionally, first grid-sharing flash memory unit and the second grid-sharing flash memory unit respectively include being made of N+ doped region
Source region and drain region, wherein the source region connects the source electrode, and the drain region connects the drain electrode；Institute
It states for the channel region of p-type doping between source region and the drain region, the surface of the channel region is used to form connection institute
State the channel of source region and the drain region；First control gate, institute are formed in the surface of the channel region
State wordline grid and second control gate；First control gate, the wordline grid and second control gate are successively arranged side by side
It is listed between the source region and the drain region, has been respectively included in first control gate and second control gate
For storing the floating gate of charge；First control gate and second control gate are in symmetrical structure in wordline grid two sides,
The source region and the drain region are in symmetrical structure.
Compared with prior art, the technical solution of the embodiment of the present invention has the advantages that
The operation scheme for programming of the flash array includes: to be programmed operation to first grid-sharing flash memory unit
When, apply the first control grid line that the first negative electricity is depressed into second grid-sharing flash memory unit, and apply the second negative electricity be depressed into it is described
Second control grid line of the second grid-sharing flash memory unit；First negative voltage and second negative voltage are configured to limitation institute
State the programming of the second grid-sharing flash memory unit.The embodiment of the present invention to first grid-sharing flash memory unit program when, by with
First control grid line of the second grid-sharing flash memory unit of its share bit lines and the second control grid line apply negative voltage, to reduce second
Longitudinal direction (that is, from direction of control gate, floating gate to channel) electric field in grid-sharing flash memory unit, to reduce programming interference.
Furthermore, the embodiment of the present invention controls grid line and the second control to the first of second grid-sharing flash memory unit
Grid line applies the problem of negative voltage can prevent programming interference, and compared with prior art, the voltage that wordline applies can be just
Voltage, such as range are the voltage of 0~1V, to reduce the difficulty of circuit realization.
Detailed description of the invention
Fig. 1 is a kind of circuit diagram of the partial structurtes of existing flash array.
Fig. 2 is a kind of circuit diagram of the partial structurtes of flash array of the embodiment of the present invention.
Fig. 3 is a kind of the schematic diagram of the section structure of grid-sharing flash memory unit of the embodiment of the present invention.
Specific embodiment
It as described in the background section, in the prior art, include the flash array of grid-sharing flash memory unit with programming string
The problem of disturbing.
Present inventor analyzes the prior art.Referring to Fig. 1, Fig. 1 is a kind of existing flash array
The circuit diagram of partial structurtes.
Flash array 200 in the prior art can include at least the first grid-sharing flash memory unit 201 and the second grid flash memory
Unit 202, first grid-sharing flash memory unit 201 and the second grid-sharing flash memory unit 202 can be respectively provided with source electrode (not shown),
Drain (not shown), the first control gate (not shown), wordline grid (not shown) and the second control gate (not shown).
The source electrode of first grid-sharing flash memory unit 201 connects the first bit line BL1, first grid-sharing flash memory unit 201
Drain electrode connect the second bit line BL2.The source electrode of second grid-sharing flash memory unit 202 connects the second bit line BL2, and described the
The drain electrode of two grid-sharing flash memory units 202 connects the first bit line BL1.
First control gate of first grid-sharing flash memory unit 201 and the second grid-sharing flash memory unit 202 is separately connected respectively
The first control grid line CG01 and CG02, the second control of first grid-sharing flash memory unit 201 and the second grid-sharing flash memory unit 202
Grid processed are separately connected respective second control grid line CG11 and CG12, and first grid-sharing flash memory unit 201 and second point of grid dodge
The wordline grid of memory cell 202 are separately connected respective wordline WL1 and WL2.
In the flash array, due to first grid-sharing flash memory unit 201 and second grid-sharing flash memory unit 202
Share bit lines, then, when being programmed operation to first grid-sharing flash memory unit 201, second grid-sharing flash memory unit
The voltage applied on 202 bit line may make the second grid-sharing flash memory unit 202 accidentally be programmed, now it is necessary to described second
The control of control grid line CG02 and/or second of the wordline WL2 of grid-sharing flash memory unit 202 and/or first grid line CG12 applies appropriate
Voltage is accidentally programmed to avoid second grid-sharing flash memory unit 202, otherwise will cause the programming string of the flash array 200
Disturb problem.
In order to enable with the grid-sharing flash memory units of programmed grid-sharing flash memory unit share bit lines not by programming interference, it is existing
Have in technology that there are a kind of operation scheme for programming for the above flash cell, when in first grid-sharing flash memory unit 201
When one of two storage positions (such as A) is programmed operation, applies the voltage of 5.5V to the first bit line BL1, apply 0.1V
Second bit line BL2 described in voltage value to 0.5V, meanwhile, grid line is controlled to the first of second grid-sharing flash memory unit 202
The control of CG02 and second grid line CG12 applies the voltage of 0V simultaneously, and to the wordline WL2 of second grid-sharing flash memory unit 202
The voltage of application -1V, the operation scheme for programming can be by applying negative voltage on wordline WL2 to inhibit the second grid flash memory
The sub-threshold current leakage of unit 202 inhibits the channel current in the channel of the second grid-sharing flash memory unit 202, so that its channel
The inside thermoelectron of not enough flowings, to inhibit the programming of the second grid-sharing flash memory unit 202.However, in flash array
In 200, negative voltage more difficult implementation in circuit realization is applied to the wordline WL2 of second grid-sharing flash memory unit 202, this will be
The circuit design of flash array 200 is made troubles.
According to the above analysis it is found that the operation scheme for programming of the prior art is in the programming interference for overcoming flash array
The circuit design of flash array is made troubles.
In order to solve the problems, such as that techniques discussed above, the embodiment of the present invention provide a kind of programming operation side of flash array
Method passes through first of the second grid-sharing flash memory unit to shared bit line when programming to first grid-sharing flash memory unit
It controls grid line and the second control grid line applies negative voltage, to reduce the longitudinal direction in the second grid-sharing flash memory unit (that is, from control
The direction of grid, floating gate to channel) electric field, to reduce programming interference.
It is understandable to enable above-mentioned purpose of the invention, feature and beneficial effect to become apparent, with reference to the accompanying drawing to this
The specific embodiment of invention is described in detail.
With continued reference to Fig. 1, the flash array of the embodiment of the present invention can also include at least 201 He of the first grid-sharing flash memory unit
Second grid-sharing flash memory unit 202, first grid-sharing flash memory unit 201 and the second grid-sharing flash memory unit 202 be respectively provided with source electrode,
Drain electrode, the first control gate, wordline grid and the second control gate.
The source electrode of first grid-sharing flash memory unit 201 connects the first bit line BL1, first grid-sharing flash memory unit 201
Drain electrode connect the second bit line BL2.The source electrode of second grid-sharing flash memory unit 202 connects the second bit line BL2, and described the
The drain electrode of two grid-sharing flash memory units 202 connects the first bit line BL1.
First control gate of first grid-sharing flash memory unit 201 and the second grid-sharing flash memory unit 202 is separately connected respectively
The first control grid line CG01 and CG02, the second control of first grid-sharing flash memory unit 201 and the second grid-sharing flash memory unit 202
Grid processed are separately connected respective second control grid line CG11 and CG12, and first grid-sharing flash memory unit 201 and second point of grid dodge
The wordline grid of memory cell 202 are separately connected respective wordline WL1 and WL2.
The embodiment of the present invention provides a kind of operation scheme for programming of flash array, the programming operation of the flash array 200
Method may include:
When being programmed operation to first grid-sharing flash memory unit 201, applies the first negative electricity and be depressed into described second point
First control grid line CG02 of flash memory in grating unit 202, and apply the second negative electricity is depressed into second grid-sharing flash memory unit 202 the
Two control grid line CG12；Wherein, first negative voltage and second negative voltage are configured to limit second point of grid
The programming of flash cell 202.
It should be pointed out that above-described first negative voltage and the second negative voltage are relative to the flash array 200
Ground signalling for.
Furthermore, the flash array 200 of the embodiment of the present invention is programmed first grid-sharing flash memory unit 201
When operation, in the channel memory cell of permission second grid-sharing flash memory unit 202 in the case where sub-threshold current leakage, pass through setting
Negative electricity is depressed into the first control grid line CG02 and the second control grid line CG12 of second grid-sharing flash memory unit 202, to weaken the
Longitudinal direction (that is, from direction of control gate, floating gate to channel) electric field in two grid-sharing flash memory units 202, keeps its unprogrammed, suppression
The programming interference of the flash array 200 is made.
Fig. 2 is a kind of circuit diagram of the partial structurtes of flash array of the embodiment of the present invention.
It should be noted that as shown in Fig. 2, in the flash array 200,201 He of the first grid-sharing flash memory unit
The connection structure of second grid-sharing flash memory unit 202 can be with are as follows: the source electrode of first grid-sharing flash memory unit 201 connects first
The drain electrode of line BL1, first grid-sharing flash memory unit 201 connect the second bit line BL2；Second grid-sharing flash memory unit 202
Source electrode connects the first bit line BL1, and the drain electrode of second grid-sharing flash memory unit 202 connects the second bit line BL2.
In the embodiment shown in Figure 2, in the flash array 200, although 201 He of the first grid-sharing flash memory unit
Second grid-sharing flash memory unit 202 be it is adjacent, but it is not limited to this, the first grid-sharing flash memory unit 201 and the second grid flash memory list
Member 202 can also be non-conterminous two grid-sharing flash memory units in flash array 200, as long as sharing two bit lines.
Referring to figs. 1 and 2, in the flash array 200 of the embodiment of the present invention, first grid-sharing flash memory unit 201
The first bit line BL1 and the second bit line BL2 is shared with the second grid-sharing flash memory unit 202, the embodiment of the present invention is not to the specific of the two
Position in flash array 200 of circuit connecting mode and the two be defined.
Referring to Fig. 3, Fig. 3 is a kind of the schematic diagram of the section structure of grid-sharing flash memory unit of the embodiment of the present invention.
In conjunction with Fig. 2 and Fig. 3, Fig. 3 is by taking the first grid-sharing flash memory unit 201 as an example, and in specific implementation, first point of grid dodge
Memory cell 201 and the second grid-sharing flash memory unit 202 may include the source region 101 and drain region being made of N+ doped region respectively
Domain 102, wherein the source region 101 connects the source electrode (not shown), and the drain region 102 connects the drain electrode (figure
Do not show)；It is the channel region 10 of p-type doping between the source region 101 and the drain region 102, the channel region 10
Surface is used to form the channel for connecting the source region 101 and the drain region 102.
The first control gate CG0, wordline grid WL and the second control gate are formed in the surface of the channel region 10
CG1；The first control gate CG0, the wordline grid WL and the second control gate CG1 are successively arranged side by side at the source area
Between domain 101 and the drain region 102, respectively included in the first control gate CG0 and the second control gate CG1 useful
In the floating gate FG0 and FG1 of storage charge.
The first control gate CG0 and the second control gate CG1 is in symmetrical structure in the two sides wordline grid WL, described
Source region 101 and the drain region 102 are in symmetrical structure.
The source region 101 can connect the first bit line BL1, and the drain region 102 can connect the second bit line
BL2。
With continued reference to Fig. 2 and Fig. 3, in specific implementation, the voltage range of first negative voltage can for -0.1V to -
3V。
Preferably, first negative voltage can be -1V.
In specific implementation, the voltage range of second negative voltage can be -0.1V to -3V.
Preferably, second negative voltage can be -1V.
In embodiments of the present invention, the wordline of tertiary voltage to second grid-sharing flash memory unit 202 can also be applied
WL2, first negative voltage are lower than the tertiary voltage, and second negative voltage is lower than the tertiary voltage.
In specific implementation, the voltage range of the tertiary voltage can be 0~1V.
Preferably, the tertiary voltage can be 0V.
Furthermore, the voltage that range is 0~1V is applied to its wordline WL2, in the programming string for reducing flash array 200
While disturbing, it is easier to implement.
It should be pointed out that due to by limiting the longitudinal direction in second grid-sharing flash memory unit 202 (that is, from control
The direction of grid, floating gate to channel) electric field, so that second grid-sharing flash memory unit 202 can not be programmed, and therefore, the present invention
Embodiment does not limit the voltage applied on the wordline WL2 of second grid-sharing flash memory unit 202.
In embodiments of the present invention, being programmed operation to first grid-sharing flash memory unit 201 may include following step
It is rapid:
Apply voltage that range is 3V~6V to the first bit line BL1, it is preferable that the voltage of 5.5V can be applied to institute
State the first bit line BL1；
Apply program current that range is 1 μ of μ A~4 A to the second bit line BL2, it is preferable that the volume of 2 μ A can be applied
Journey electric current is to the second bit line BL2；
Apply range be 6V~10V voltage to first grid-sharing flash memory unit 201 first control grid line CG01, it is excellent
Selection of land can apply the voltage of 8V to the first control grid line CG01 of first grid-sharing flash memory unit 201；
Apply range be 3V~6V voltage to first grid-sharing flash memory unit 201 second control grid line CG11, it is excellent
Selection of land can apply the voltage of 5V to the second control grid line CG11 of first grid-sharing flash memory unit 201；
Applying range is the voltage of 1V~2V to the wordline WL1 of first grid-sharing flash memory unit 201, can preferably be applied
Add the voltage of 1.5V to the wordline WL of first grid-sharing flash memory unit 201.
It should be noted that the execution sequence of each step is not limited to said sequence in the embodiment of the present invention.
It should be pointed out that applying range is the program current of 1 μ of μ A~4 A to the second bit line BL2, institute can be made
It states and is formed with the about voltage of 0.1V~0.5V on the second bit line BL2；And program current is applied to the second bit line BL2, it can
So that stream has enough electronics in the channel of first grid-sharing flash memory unit 201, in favor of first grid flash memory
The programming of unit 201.In specific implementation, the electricity of about 0.1V~0.5V can also directly be applied to the second bit line BL2
Pressure, the present embodiment is without specifically limited.
When being programmed operation to first grid-sharing flash memory unit 201, applying 1.5V voltage to its wordline WL1 can be with
Choose first grid-sharing flash memory unit 201.The voltage difference formed on the first bit line BL1 and the second bit line BL2 can
So that stream has sufficiently large channel current in first grid-sharing flash memory unit 201, in favor of the electronics flowing in channel.It applies
Add the voltage of 8V to control grid line CG01 to the first of first grid-sharing flash memory unit 201, applies the voltage of 5V to described first
Second control grid line CG11 of grid-sharing flash memory unit 201, can make in first grid-sharing flash memory unit 201, described first
The floating gate FG0 of control gate line traffic control is programmed, and the floating gate of the second control grid line FG1 control is unprogrammed.
It should be noted that the embodiment of the present invention is when being programmed first grid-sharing flash memory unit 201, to it
For the corresponding floating gate FG0 of first control grid line CG01 is programmed, the embodiment of the present invention can also dodge first point of grid
The corresponding floating gate FG1 of the second control grid line CG11 of memory cell 201 is programmed, can be to first grid-sharing flash memory unit
The voltage applied on 201 the first control grid line CG01 and its second control grid line CG11 is exchanged.
It in specific implementation, can also be to its wordline WL1, when being programmed to first grid-sharing flash memory unit 201
One control grid line CG01, the second control grid line CG11 and the first bit line BL1 and the second bit line BL2 apply different electricity
Pressure, as long as can achieve the programing effect to first grid-sharing flash memory unit 201, the embodiment of the present invention is without special
Limitation.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (6)
1. a kind of operation scheme for programming of flash array, the flash array includes at least the first grid-sharing flash memory unit and second point
Flash memory in grating unit, first grid-sharing flash memory unit and the second grid-sharing flash memory unit are respectively provided with source electrode, drain electrode, the first control
Grid, wordline grid and the second control gate；
The source electrode of first grid-sharing flash memory unit connects the first bit line, the drain electrode connection second of first grid-sharing flash memory unit
Bit line；
The source electrode of second grid-sharing flash memory unit connects second bit line, the drain electrode connection of second grid-sharing flash memory unit
First bit line, alternatively, the source electrode of second grid-sharing flash memory unit connects first bit line, second grid flash memory
The drain electrode of unit connects second bit line；
First control gate of first grid-sharing flash memory unit and the second grid-sharing flash memory unit is separately connected respective first control
Second control gate of grid line, first grid-sharing flash memory unit and the second grid-sharing flash memory unit is separately connected respective second control
The wordline grid of grid line, first grid-sharing flash memory unit and the second grid-sharing flash memory unit are separately connected respective wordline；
It is characterized in that, the operation scheme for programming of the flash array includes:
When being programmed operation to first grid-sharing flash memory unit, applies the first negative electricity and be depressed into the second grid flash memory list
First control grid line of member, and apply the second control grid line that the second negative electricity is depressed into second grid-sharing flash memory unit；
The programming for being configured to limit second grid-sharing flash memory unit of first negative voltage and second negative voltage；
Applying the wordline of tertiary voltage to second grid-sharing flash memory unit, first negative voltage is lower than the tertiary voltage,
Second negative voltage is lower than the tertiary voltage, and the voltage of the tertiary voltage is positive voltage.
2. the operation scheme for programming of flash array according to claim 1, which is characterized in that the electricity of first negative voltage
Pressing range is -0.1V to -3V.
3. the operation scheme for programming of flash array according to claim 2, which is characterized in that the electricity of second negative voltage
Pressing range is -0.1V to -3V.
4. the operation scheme for programming of flash array according to claim 1 or 3, which is characterized in that the tertiary voltage
Voltage range is the positive voltage less than 1V.
5. the operation scheme for programming of flash array according to claim 1, which is characterized in that first grid flash memory
Unit is programmed operation
Apply voltage that range is 3V~6V to first bit line；
Apply program current that range is 1 μ of μ A~4 A to second bit line；
Apply range be 6V~10V voltage to first grid-sharing flash memory unit first control grid line；
Apply range be 3V~6V voltage to first grid-sharing flash memory unit second control grid line；
Apply range be 1V~2V voltage to first grid-sharing flash memory unit wordline.
6. the operation scheme for programming of flash array according to any one of claims 1 to 5, which is characterized in that described first
Grid-sharing flash memory unit and the second grid-sharing flash memory unit respectively include the source region and drain region being made of N+ doped region,
In, the source region connects the source electrode, and the drain region connects the drain electrode；The source region and the drain region
It is the channel region of p-type doping between domain, the surface of the channel region, which is used to form, connects the source region and the drain region
The channel in domain；
First control gate, the wordline grid and second control gate are formed in the surface of the channel region；Institute
It states the first control gate, the wordline grid and second control gate and is successively arranged side by side at the source region and the drain region
Between domain, the floating gate for storing charge is respectively included in first control gate and second control gate；
First control gate and second control gate are in symmetrical structure, the source region and institute in wordline grid two sides
Drain region is stated in symmetrical structure.
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| CN106971372B (en) * | 2017-02-24 | 2020-01-03 | 北京大学 | Coding type flash memory system and method for realizing image convolution |
| CN108257638B (en) * | 2018-01-18 | 2021-01-29 | 上海华虹宏力半导体制造有限公司 | Programming method suitable for split gate flash memory |
| CN108648777B (en) * | 2018-05-10 | 2020-08-11 | 上海华虹宏力半导体制造有限公司 | Programming sequential circuit and method of double-separation gate flash memory |
| CN110137173B (en) * | 2019-04-15 | 2021-01-22 | 上海华虹宏力半导体制造有限公司 | Memory and operation method thereof |
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