CN108492844B

CN108492844B - Double-split gate flash memory array and programming method thereof

Info

Publication number: CN108492844B
Application number: CN201810254478.5A
Authority: CN
Inventors: 杨光军; 高超
Original assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2018-03-26
Filing date: 2018-03-26
Publication date: 2020-10-16
Anticipated expiration: 2038-03-26
Also published as: CN108492844A

Abstract

The invention discloses a double-split-gate flash memory array and a programming method thereof, wherein the double-split-gate flash memory array comprises M × N memory cells, and a control grid line CG0/CG1 of each memory cell is parallel to a bit line BL0/BL1 and is vertical to a word line WL.

Description

Double-split gate flash memory array and programming method thereof

Technical Field

The present invention relates to flash memory and a programming method thereof, and more particularly, to a dual split gate flash memory array and a programming method thereof.

Background

Fig. 1 is a schematic diagram of a cell structure of a dual split gate flash memory. As shown in fig. 1, a dual split gate flash memory cell includes: a semiconductor P-type substrate (P _ sub)10 on which an N-Well (N-Well)11 is disposed, the N-Well 11 having spaced apart source (S) and drain (D)

regions

110 and 120 and a channel region 130; a channel region 130 between the source region (S)110 and the drain region (D) 120; a first bit line BL0 and a second bit line BL1 connected to the source region 110 and the drain region 120, respectively; a first floating gate 210 disposed over the channel region 130 above and to the right of the source region 110; a second floating gate 220 disposed above the channel region 130 above and to the left of the drain region 120, the first floating gate 210 and the second floating gate 220 constituting a first memory bit cell and a second memory bit cell, respectively; a first control gate 310 and a second control gate 320, which are respectively disposed above the first floating gate 210 and the second floating gate 220, and the first and second control gate lines are respectively connected to the first control gate 310 and the second control gate 320; a word line region 40 is located over the channel region 130 between the first floating gate 210 and the second floating gate 220, and a word line WL is connected to the word line region 40.

In the prior art, a Source injection method (Source injection) is generally adopted when programming the dual split gate flash memory shown in fig. 1, assuming that a right storage bit a (storage bit at an oval circle) is selected, a word line voltage WL is set to be 1.4V, a second bit line voltage BL1 is set to be 5V, a second control gate line voltage CG1 is set to be 8V, a first control gate line voltage CG0 is set to be 5V, and a first bit line BL0 is a bias voltage Vdp.

Disclosure of Invention

To overcome the above-mentioned deficiencies of the prior art, an object of the present invention is to provide a dual split gate flash memory array and a programming method thereof, which are suitable for low power consumption situations.

To achieve the above and other objects, the present invention provides a dual split gate flash memory array, which includes M × N memory cells, wherein the control gate line CG0/CG1 of each memory cell is parallel to the bit line BL0/BL1 and perpendicular to the word line WL.

Further, in the column direction, the first and second control gate lines CG0j and CG1j are respectively connected to the first and second control gate regions of the memory cells of each column, j is 0, 1, 2, 3, … …, N-1, the bit line BL0 is connected to the source terminal of the memory cell of the first column, the bit line BLj is connected to the drain terminal of the memory cell of the j column and the source terminal of the memory cell of the j +1 column, j is 1, 2, 3, … …, N-1, and the bit line BLN is connected to the drain terminal of the memory cell of the N column.

Furthermore, during programming, the bit line current of the selected memory cell is set to 0, which is suitable for low power consumption.

Further, during programming, the word line voltage WL of the selected memory cell is set to-5V to-10V, the first bit line BL0 and the second bit line voltage BL1 are set to BL 0V, the first control gate line voltage CG0 is set to 0V to-8V, and the second control gate line voltage CG1 is set to 5V to-10V.

Further, for other unselected memory cells in the row of the selected memory cell, the word line voltage WL of the memory cell is-5V to-10V, and the control gate line voltage CG0/1 in the column direction is 0, so that no tunneling effect and no programming action occur on the memory cell.

Further, for other unselected memory cells or storage bits of the column where the selected memory cell is located, the second control gate line voltage CG1 of the memory cell is 5V to 10V, the first control gate line voltage CG0 is 0V to-8V, if the memory cells are not in the same column, the word line voltage WL is 0V, no tunneling effect occurs on the memory cell, and thus no programming operation occurs, and if the memory cells are not in the same column, that is, another storage bit of the selected memory cell, although the word line voltage WL is-5V to-10V, the corresponding first control gate line voltage CG0 is 0V to-8V, and thus no tunneling effect occurs on the storage bit.

Further, for the row and column of the unselected memory cell, the word line voltage WL is 0V in the row direction, and the first and second control gate line voltages CG0/1 are 0V in the column direction, no tunneling effect and thus no programming action occurs on such memory cell.

Furthermore, a tunneling effect of polysilicon inversion is adopted during programming.

Compared with the prior art, the dual-split gate flash memory array and the programming method thereof can be suitable for low-power-consumption occasions.

Drawings

FIG. 1 is a schematic diagram of a cell structure of a dual split gate flash memory;

FIG. 2 is a schematic diagram of an array architecture of a dual split gate flash memory array according to the present invention.

Detailed Description

Other advantages and capabilities of the present invention will be readily apparent to those skilled in the art from the present disclosure by describing the embodiments of the present invention with specific embodiments thereof in conjunction with the accompanying drawings. The invention is capable of other and different embodiments and its several details are capable of modification in various other respects, all without departing from the spirit and scope of the present invention.

In the method for programming a dual split gate flash memory array of the present invention, a polysilicon inversion (Reverse poly to poly) tunneling (Fowler-Nordheim tunneling) method is used to program the dual split gate flash memory array shown in fig. 1, assuming that a right storage bit a (storage bit at an oval circle) is selected, a word line voltage WL is set to-5V to-10V (preferably, WL to-8V), a first bit line voltage BL0 and a second bit line voltage BL0 are set to BL1 to 0V, a first control gate line voltage CG0 is set to 0V to-8V (preferably, CG0 is set to-4V), and a second control gate line voltage CG1 is set to 5V to 10V (preferably, CG1 is set to 8V).

The bit line current is 0 when programming in this way, which is suitable for low power consumption.

FIG. 2 is a schematic diagram of an array architecture of a dual split gate flash memory array according to the present invention. As shown in fig. 2, the dual split gate flash memory array of the present invention includes M × N memory arrays, in a row direction, a word line WLi is connected to a word line region (i ═ 0, 1, 2, … …, M-1) of the memory cells in each row, in a column direction, a first control gate line CG0j and a second control gate line CG1j are respectively connected to a first control gate region and a second control gate region (j ═ 0, 1, 2, 3, … …, N-1) of the memory cells in each column, a bit line BL0 is connected to a source terminal of the memory cells in the first column, a bit line BLj is connected to a drain terminal of the memory cells in the j th column and a source terminal of the memory cells in the j +1 column (j ═ 1, 2, 3, … …, N-1), a bit line BLN is connected to a drain terminal of the memory cells in the N column, that is, that the control gate line CG0/1 of the present invention is parallel to the bit line BL0/1 and perpendicular to the word line WL, to enable a programming operation on a single bit.

For other unselected memory cells or storage bits (bit), assuming that the storage bit a is selected, the method is divided into three categories:

in the first type, the word line voltage WL of the unselected memory cell in the row of the selected memory cell is-8V, but the control gate line voltage CG0/1 is 0 in the column direction, and no tunneling effect and thus no programming action occurs in the unselected memory cell;

in the second type, other unselected memory cells or memory bits in the column where the memory cell is located are selected, the second control gate line voltage of the memory cell is CG1 ═ 8V, the first control gate line voltage is CG0 ═ 4V, if the memory cell is not in the same column, the word line voltage WL ═ 0V, no tunneling effect occurs on the memory cell, and thus no programming action occurs, if the memory cell is not in the same column, that is, another memory bit of the selected memory cell, although the word line voltage WL ═ 8V, but the corresponding first control gate line voltage CG0 ═ 4V, no tunneling effect occurs on the memory bit, and thus no programming action occurs;

in the third category, the unselected memory cell is in the row and column, the word line voltage WL is 0V in the row direction, and the first and second control gate line voltages CG0/1 are 0V in the column direction, and no tunneling effect and thus no programming action occurs in such memory cells.

The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Modifications and variations can be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the present invention. Therefore, the scope of the invention should be determined from the following claims.

Claims

1. A dual split gate flash memory array comprising M x N memory cells, comprising: the control grid line CG0/CG1 of each memory cell is parallel to a bit line BL0/BL1 and is vertical to a word line WL, each memory cell comprises two storage bits, the two storage bits of the same memory cell respectively correspond to a control grid, and each control grid is respectively connected with different control grid lines.

2. The dual split gate flash memory array of claim 1, wherein: in the column direction, a first control gate line CG0j and a second control gate line CG1j are respectively connected to the first control gate region and the second control gate region of the memory cell of each column, j is 0, 1, 2, 3, … …, N-1, a bit line BL0 is connected to the source terminal of the memory cell of the first column, a bit line BLj is connected to the drain terminal of the memory cell of the j-th column and the source terminal of the memory cell of the j + 1-th column, j is 1, 2, 3, … …, N-1, and a bit line BLN is connected to the drain terminal of the memory cell of the N-th column.

3. The dual split gate flash memory array of claim 2, wherein: during programming, the bit line current of the selected memory cell is set to 0, which is suitable for low power consumption.

4. The dual split gate flash memory array of claim 3, wherein: in programming, the word line voltage WL of the selected memory cell is set to-5V to-10V, the first bit line BL0 and the second bit line voltage BL1 are set to BL0 are set to 0V, the first control gate line voltage CG0 is set to 0V to-8V, and the second control gate line voltage CG1 is set to 5V to 10V.

5. The dual split gate flash memory array of claim 4, wherein: for other unselected memory cells in the row of the selected memory cell, the word line voltage of the unselected memory cells is WL-5V-10V, and the control gate line voltages CG0 and CG1 in the column direction of the unselected memory cells are 0V, so that no tunneling effect and no programming action occur on the unselected memory cells.

6. The dual split gate flash memory array of claim 4, wherein: for other unselected memory cells in the column of the selected memory cell, the second control gate line voltage of the unselected memory cell is CG 1-5V-10V, the first control gate line voltage is CG 0-0-8V, if the unselected memory cells are not in the same row, the word line voltage WL-0V does not generate tunneling effect on the unselected memory cell, so that no programming action occurs, and for the unselected storage bit of the selected memory cell, although the word line voltage WL-5V-10V, the first control gate line voltage CG0 corresponding to the unselected storage bit is 0-8V, so that no tunneling effect occurs on the unselected storage bit, so that no programming action occurs.

7. The dual split gate flash memory array of claim 4, wherein: for the row and the column of the unselected memory cell, the word line voltage WL is 0V in the row direction, and the first and second control gate line voltages CG0, CG1 are both 0V in the column direction, and no tunneling effect and thus no programming action occurs on the unselected memory cell.

8. A programming method of a dual split gate flash memory array is characterized in that: the programming method is used for programming the dual split gate flash memory array as claimed in any one of claims 1 to 7, and adopts a tunneling effect of polysilicon inversion during programming.

9. The method of claim 8, wherein the method further comprises: during programming, the bit line current of the selected memory cell is set to 0, which is suitable for low power consumption.

10. The method of claim 9, wherein the method further comprises: in programming, the word line voltage WL of the selected memory cell is set to-5V to-10V, the first bit line BL0 and the second bit line voltage BL1 are set to BL0 are set to 0V, the first control gate line voltage CG0 is set to 0V to-8V, and the second control gate line voltage CG1 is set to 5V to 10V.