CN102385920A - Memory array and programming method - Google Patents
Memory array and programming method Download PDFInfo
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- CN102385920A CN102385920A CN2010102711885A CN201010271188A CN102385920A CN 102385920 A CN102385920 A CN 102385920A CN 2010102711885 A CN2010102711885 A CN 2010102711885A CN 201010271188 A CN201010271188 A CN 201010271188A CN 102385920 A CN102385920 A CN 102385920A
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Abstract
Provided is a memory array and programming method. Drain voltage of a first memory unit for conducting programming and a second memory unit located on the same line and also adjacent to the first memory unit is clamped on the same electric potential, two adjacent bit lines coupled with a second memory unit source/ drain terminal are led to have the same voltage, and voltage drops do not exist. No current flows by on the memory unit so that leakage current is avoided. The memory array and programming method further decomposes larger voltage difference which possibly exists between adjacent bit lines into a plurality of voltage drops smaller than a memory unit threshold value, and further ensures that other memory units are all in a cut-off state except the first memory unit for conduct programming and no current flows by, thereby effectively preventing the memory units not related to programming from being interfered during a programming process, and further improving accuracy of programming.
Description
Technical field
The present invention relates to memory array, be specifically related to a kind of programmed method of memory array, belong to technical field of semiconductors.
Background technology
Non-volatility semiconductor devices such as flash memory are with the reference cell current that is set to certain predetermined threshold value electric current as a reference; The electric current and the reference current of memory cell of in reading process, will flowing through compares; Whether big according to the memory cell current that is read than reference current, and carry out the judgement of data " 1 " or " 0 ".
Highgrade integration along with storage arrangement; The space of memory cell constantly is reduced; Model (pattern) size also reduces thereupon; Floating gate memory cell (Floating gate memory cell) can be stored two separate bit data, and it has improved the integrated level of storage array greatly.In the storage array that adopts floating gate memory cell to form, adopt the framework of virtual ground usually, above the array bit line, be formed on gate stack structure vertical with it on the surface level.
Flash storage device adopts the steady current programmed method more; Yet; In the virtual ground array structure; Area of isolation is not to be formed between the bit line, and along with dwindle (scaleddown) of virtual ground memory array size, the leakage between bit line (bit-line to bit-line leakage) increases; And bit line contact deviation (bit-line contact misalignment) also can cause producing leakage current between this bit line side, the unadulterated silicide regions at this bit line and adjacent being arranged at, thereby reduces the effect of this bit line contact.
The appearance of leakage current has had a strong impact on the accuracy of program current.In the prior art; Usually be employed in the bit line top and form corresponding bit line contact, can use additional doping implantation to increase the size in this bit line diffusion zone in this contact through after the etching in case the stop bit line contacts deviation; Yet; This method will be dwindled the distance between bit line, also can increase the leakage current between bit line, thereby make the programming to memory array produce error.
Summary of the invention
The technical matters that the present invention will solve is; A kind of memory array and programmed method are provided, effectively reduce leakage current, reduce in the programming process because the programming error that leakage current produces; Improve the accuracy of program current, to improve the accuracy of memory array programming.
For solving the problems of the technologies described above, memory array provided by the invention comprises:
Multirow and multiple row memory cell;
A plurality of word lines, it is coupled to the multirow memory cell, is connected with the grid of each memory cell, through the strobe case of each row of memory cells of control word line Control of Voltage;
A plurality of bit lines, it is coupled to the multiple row memory cell, is connected the programming and the read-write motion of each the row memory cell of Control of Voltage through controlling adjacent two bit lines with the active electrode (S/D) of each memory cell;
A plurality of pre-charge circuits are for above-mentioned word line and bit line provide required WV or working current;
And clamping circuit; In the memory array programming process; To clamp down on identical and stable drain voltage with first bit line of the first memory unit drain terminal coupling of the action of programming and with second bit-line voltage of second memory unit drain terminal coupling; Wherein second memory unit and first memory unit are positioned at same delegation, and the two is adjacent.
Further, clamping circuit comprises current feedback circuit and impact damper, and current feedback circuit provides stable, an accurate program current, and this electric current is identical with the first memory cell current selected, the action of programming of flowing through; The output of this current feedback circuit is connected to drain terminal and the positive or the negative-phase input of impact damper with the first memory unit of the action of programming simultaneously; The output terminal of impact damper connects a pre-charge circuit, this pre-charge circuit provide one with the identical pressure drop of first memory unit drain terminal voltage of the action of programming, and with the negative or the normal phase input end of this Voltage Feedback to impact damper.
Further; In this memory array programming process; The bit line that is coupled with source, the first memory unit end of the action of programming provides a high level by the pre-charge circuit that it was connected, and by pre-charge circuit or the clamping circuit that it was connected one steady current is provided with the bit line of this first memory unit drain terminal coupling.
Further, in this memory array, related memory cell is two floating booms, two control gate structure, and has the selection grid that are connected with word line, and in this structure, each memory cell can be stored two separate bytes.
The present invention also provides a kind of memory array programmed method; Each related memory cell is two floating booms, two control gate structure in this memory array; In the programming process; To the action of programming of first memory unit, with the word line of first memory cell gate coupling on apply a word line voltage V
W, this word line voltage V
WScope is 0.8V～1.6V.
Further, this word line voltage V
WBe 1.6V.
Further, apply identical drain voltage V being positioned on second bit line of same delegation and adjacent second storage unit drain terminal coupling with first bit line of first memory unit drain terminal coupling and with the first memory unit
D, this voltage range is 0.1V～0.6V.
Further, this drain voltage V
DBe 0.3V.
Further, apply N voltage V being positioned on the N bit line of same delegation and the at interval N memory cell drain terminal coupling of (N-2) individual memory cell with the second memory unit
N, its scope is 1V～5V, wherein, N is integer and N>=3.
Further, preliminary filling N voltage V at first on being positioned at (N+1) bit line of (N+1) memory cell drain terminal of delegation coupling with the second memory unit
N, unsettled then.
Further, apply i voltage V being positioned on the i bit line with the coupling of the i memory cell drain terminal of delegation with the second memory unit
i, its scope is 1V～3V, wherein, i is integer and 2≤i＜N.
Further, the voltage V that applies at i bit line with the coupling of i memory cell drain terminal
iSatisfy condition: 0≤V
i-V
I-1The threshold voltage V of＜the i memory cell
Thi
Further, other bit lines are unsettled in the memory array.
Memory array provided by the invention and programmed method; First memory unit through the action of will programming and be positioned at same delegation with it and the drain terminal voltage clamp of adjacent second memory unit on a same potential; Make with adjacent two bit lines of not source, gated memory unit/drain terminal coupling and have identical voltage; Do not have pressure drop therebetween, no current does not flow through on the gated memory unit, effectively reduces the leakage current of memory array in the programming process.
It is some pressure drops less than memory cell threshold voltage that a kind of memory array programmed method provided by the invention also further decomposes the big voltage difference that possibly exist between adjacent bit lines; Further guarantee except that the first memory unit of the action of programming; Other memory cells all are in cut-off state; No current is flowed through, thereby effectively prevents in the programming process memory cell that does not relate to the programming action to be produced interference, further improves its programming accuracy of action.
Description of drawings
Fig. 1 is memory array organization figure provided by the invention;
Fig. 2 a is a memory cell transistor structural drawing related in memory array provided by the invention and the programmed method;
Fig. 2 b is memory cell equivalent structure figure related in memory array provided by the invention and the programmed method;
Fig. 3 is a memory array programmed method synoptic diagram provided by the invention;
Fig. 4 is a memory array programmed method most preferred embodiment synoptic diagram provided by the invention.
Embodiment
For making the object of the invention, technical scheme and advantage clearer, the present invention is made further detailed description below in conjunction with accompanying drawing.
Fig. 1 is memory array organization figure provided by the invention.
As shown in Figure 1, the memory array that this embodiment provides comprises:
Multirow and multiple row memory cell;
A plurality of word lines (WL < 0 >～WL < n >), it is coupled to the multirow memory cell, is connected with the grid of each memory cell, the strobe case of each row of memory cells of word line voltage control that provides through pre-charge circuit;
A plurality of bit lines (BL < 0 >～BL < k >), it is coupled to the multiple row memory cell, is connected the programming and the read-write motion of each the row memory cell of Control of Voltage through controlling adjacent two bit lines with the active electrode (S/D) of each memory cell;
(P1～P3) is for above-mentioned word line and bit line provide required WV or working current to a plurality of pre-charge circuits;
Clamping circuit, in the memory array programming process, will with the first bit line BL of first memory unit M1 drain coupled of the action of programming<1>, and with the second bit line BL of second memory unit M2 drain terminal coupling<2>Voltage clamp is at identical and stable drain voltage V
DOn, wherein, the second memory unit M2 and the first storage unit M1 are positioned at same delegation, and the two is adjacent.
In this embodiment, clamping circuit comprises current feedback circuit A1 and impact damper A2, and current feedback circuit A1 provides stable, an accurate program current, and this electric current is identical with the electric current of the first memory unit M1 that flows through; The output of this current feedback circuit A1 is connected to the drain terminal of first memory unit M1 and the input end of impact damper A2 simultaneously; The output terminal of impact damper A2 connects pre-charge circuit P3, this pre-charge circuit P3 provide one with the identical pressure drop V of first memory unit M1 drain terminal voltage
D, and with this voltage V
DFeed back to another input end of impact damper A2.
As preferred embodiment, the output terminal of current feedback circuit A1 connects the in-phase input end of impact damper A2, and the inverting input of impact damper A2 is connected with its output terminal.
As another embodiment, the output terminal of current feedback circuit A2 connects the inverting input of impact damper A2, and the in-phase input end of impact damper A2 is connected with its output terminal.
In this embodiment; M1 programmes to the first memory unit; By the pre-charge circuit P1 that it was connected one high level is provided with the bit line BL < 0>of its source end S coupling, by the pre-charge circuit P2 that it was connected one steady current is provided with the first bit line BL < 1>of its drain terminal D coupling.
As most preferred embodiment, related memory cell is two floating booms, two control gate structure in this memory array, and its transistor junction composition and memory cell equivalent structure figure are respectively shown in Fig. 2 a and Fig. 2 b.
Shown in Fig. 2 a and Fig. 2 b; Be positioned at the memory cell that semiconductor sinks to the bottom on 100 and have two position storage unit 500,600; Have the selection grid 400 that link together with word line WL therebetween; Select grid 400 and 500/600 of the storage unit in position insulation oxide 700 to be arranged at interval, each storage unit 500/600 includes one and is used to store the floating boom 520/620 and control gate 510/520 of data, and this memory cell 300 is connected with bit line with draining through source electrode 200.This memory cell can be stored two separate bytes.
The memory array that this embodiment provides; Through introduce clamping circuit will programme the first memory unit of action and be positioned at same delegation with it and the drain terminal voltage clamp of adjacent second memory unit on a same potential; Make with adjacent two bit lines of not source, gated memory unit/drain terminal coupling and have identical voltage; Do not have pressure drop therebetween, no current does not flow through on the gated memory unit, effectively reduces the leakage current of memory array in the programming process.
The present invention also provides a kind of memory array programmed method.
Fig. 3 is a memory array programmed method synoptic diagram provided by the invention.
As shown in Figure 3, each related memory cell is the two floating booms described in Fig. 2 a/ Fig. 2 b, two control gate structure in this memory array.
In this embodiment, to the first memory unit M1 action of programming, with the word line WL of first memory unit M1 gate coupled<0>On apply a word line voltage V
W, this word line voltage V
WScope is 0.8V～1.6V; Second memory unit M2 and first memory unit M1 are positioned at same delegation and the two is adjacent, with the first bit line BL of first memory unit M1 drain terminal coupling<1>Reach the second bit line BL with the coupling of second memory unit M2 drain terminal<2>On apply the first identical drain voltage V
D, this voltage range is 0.1V～0.6V.
Further, apply N voltage V being positioned on the N bit line of same delegation and the at interval N memory cell MN drain terminal coupling of (N-2) individual memory cell with second memory unit M2
N, its scope is 1V～5V, wherein, N is integer and N>=3.At this moment, pre-charge pressure V at first on being positioned at (N+1) bit line of (N+1) memory cell M (N+1) drain terminal of delegation coupling with second memory unit M2
N, unsettled then.
Further, apply i voltage Vi being positioned on the i bit line with the coupling of the i memory cell Mi drain terminal of delegation with second memory unit M2, its scope is 1V～3V, and wherein, i is that integer and 2≤i are less than N.In addition, the voltage Vi that applies at the i bit line 0≤V that satisfies condition with i memory cell Mi drain terminal coupling
i-V
I-1The threshold voltage V of＜the i memory cell
Thi.
In this embodiment, other bit lines of memory array are unsettled.
Fig. 4 is a memory array programmed method most preferred embodiment synoptic diagram provided by the invention.
As shown in Figure 4; As most preferred embodiment; Each related memory cell is the two floating booms shown in Fig. 2 a/ Fig. 2 b, two control gate structure in the memory array programmed method that present embodiment provides; In the programming process, the first memory unit M1 action of programming, with the word line WL of first memory unit M1 gate coupled<0>On apply a word line voltage V
W, its scope is 0.8V～1.6V, in the present embodiment, and word line WL<0>On the voltage that applies be 1.6V.
In the present embodiment, with the bit line BL of M1 source, the first memory unit end coupling of the action of programming<0>Apply a high level V
S, this voltage V
SScope is 2.5V～5.5V, with the first bit line BL of first memory unit M1 drain terminal coupling<1>And be positioned at the second bit line BL of same delegation and the M2 drain terminal coupling of adjacent second memory unit with first memory unit M1<2>On apply identical drain voltage V
D, this voltage range is 0.1V～0.6V.In the present embodiment, bit line BL<0>On the voltage V that applies
SBe 5V, the first bit line BL<1>With the second bit line BL<2>On the drain voltage V that applies
DBe 0.3V.
At this moment; The voltage that applies on the bit line BL < 1>of the M2 source, second memory unit adjacent with first memory unit M1/drain terminal coupling, the BL < 2>equates; Second memory unit M2 goes up no current and flows through; With the first memory unit M1 of action of programming that all flows through of the electric current on the first bit line BL < 1>of first memory unit M1 drain terminal coupling, no leakage current generation.
In the present embodiment; Be positioned on the 3rd word line BL < 3>of same delegation and the coupling of adjacent the 3rd memory cell M3 drain terminal with second memory unit M2 and apply tertiary voltage V3; Its scope is 1V～2V, and in the present embodiment, the voltage that applies on the 3rd word line BL < 3>is 1V.
At this moment; The three memory cell M3 grid voltage adjacent with second memory unit M2 (being the voltage that applies on the word line WL < 0 >) is 1.6V; With apply voltage 0.3V, 1V respectively on the second bit line BL < 2>of its source/drain terminal coupling and the 3rd bit line BL < 3 >; Because drain terminal voltage is very low,, be not subject to the programming action and disturb.
In the present embodiment; Be positioned on the 4th bit line BL < 4>of same delegation and the coupling of adjacent the 4th memory cell M4 drain terminal with the 3rd memory cell M3 and apply the 4th voltage V4; Its scope is 1V～5V, and in the present embodiment, the voltage that applies on the 4th word line BL < 4>is 3V.
At this moment, the 4th adjacent with the 3rd memory cell M3 memory cell M4 grid voltage (is word line WL<0>On the voltage that applies) be 1.6V, with the 3rd bit line BL of its source/drain terminal coupling<3>And the 4th bit line BL<4>On apply voltage 1V, 3V respectively, pressure drop V is leaked in its source
GS4=1.6V-1V=0.6V, much smaller than the threshold voltage of this memory cell M4 conducting, the 4th memory cell M4 is in cut-off state, and no current flows through, and not disturbed by the programming action.
In the present embodiment, the five bit line BL < 5>adjacent with the 4th bit line BL < 4>be preliminary filling the 4th voltage V4=3V at first, and unsettled subsequently, other bit lines are all unsettled in the memory array.
At this moment; In the present embodiment only to the first memory unit M1 action of programming; The source-drain voltage of the second memory unit M2 that is adjacent is clamped on the same potential, and no leakage current produces, simultaneously; It is some pressure drops less than memory cell threshold voltage that the memory array programmed method that present embodiment provides also further decomposes the big voltage difference that possibly exist between adjacent bit lines; Guarantee that further other memory cells all are in cut-off state except that the first memory unit of the action of programming, no current is flowed through; Thereby effectively prevent in the programming process memory cell that does not relate to the programming action to be produced interference, further improve its programming accuracy of action.
Under situation without departing from the spirit and scope of the present invention, can also constitute many very embodiment of big difference that have.Should be appreciated that except like enclosed claim limited, the invention is not restricted at the specific embodiment described in the instructions.
Claims (18)
1. memory array comprises:
Multirow and multiple row memory cell;
A plurality of word lines, it is coupled to said multirow memory cell;
A plurality of bit lines, it is coupled to said multiple row memory cell;
A plurality of pre-charge circuits are for said a plurality of word lines and a plurality of bit line provide WV or working current;
It is characterized in that this memory array also comprises:
Clamping circuit; In said memory array programming process; To clamp down on identical and stable drain voltage with first bit line of the first memory unit drain terminal coupling of the action of programming and with second bit-line voltage of second memory unit drain terminal coupling; Wherein, said second memory unit and said first memory unit are positioned at same delegation, and the two is adjacent.
2. memory array according to claim 1; It is characterized in that; Said clamping circuit comprises: current feedback circuit and impact damper, and said current feedback circuit output one stable, precise current, this current value is identical with the current value of the first memory unit stream warp of the action of programming.
3. memory array according to claim 1 and 2; It is characterized in that; In said memory array programming process; By said pre-charge circuit one high level is provided with the bit line of source, the first memory unit end coupling of the action of programming, by said pre-charge circuit one steady current is provided with the bit line of said first memory unit drain terminal coupling.
4. memory array according to claim 1 is characterized in that, said memory cell is two floating booms, two control gate structure, can store two separate bytes.
5. memory array programmed method; Each memory cell is two floating booms, two control gate structure in the said memory array; In the programming process; To the action of programming of first memory unit, apply the first identical drain voltage V being positioned at the bit line of said first memory unit drain terminal coupling and with it on second bit line that same delegation and adjacent second memory unit drain terminal be coupled
D
6. memory array programmed method according to claim 5 is characterized in that, with the word line of said first memory cell gate coupling on apply a word line voltage V
W, said word line voltage V
WScope is 0.8V～1.6V.
7. memory array programmed method according to claim 6 is characterized in that, said word line voltage V
WBe 1.6V.
8. memory array programmed method according to claim 6 is characterized in that, the said first identical drain voltage V
DScope is 0.1V～0.6V.
9. memory array programmed method according to claim 6 is characterized in that, the said first identical drain voltage V
DBe 0.3V.
10. memory array programmed method according to claim 8 is characterized in that, the N bit line that is positioned at same delegation and the N memory cell drain terminal coupling of (N-2) individual memory cell at interval with said second memory unit applies N voltage V
N, its scope is 1V～5V, wherein, N is integer and N>=3.
11. memory array programmed method according to claim 10 is characterized in that, is positioned at (N+1) bit line of (N+1) memory cell drain terminal of delegation coupling preliminary filling N voltage V at first with said second memory unit
N, unsettled then.
12. memory array programmed method according to claim 10 is characterized in that, is positioned on the i bit line with the coupling of the i memory cell drain terminal of delegation with said second memory unit to apply i voltage V
i, its scope is 1V～3V, wherein, i is integer and 2≤i＜N.
13. memory array programmed method according to claim 12 is characterized in that 0≤V
i-V
I-1The threshold voltage V of＜the i memory cell
Thi
14., it is characterized in that other bit lines are unsettled in this memory array according to claim 10 or 11 or 13 described memory array programmed methods.
15. memory array programmed method according to claim 13 is characterized in that, said N=3 applies tertiary voltage V being positioned on the 3rd bit line of same delegation and the coupling of adjacent the 3rd memory cell drain terminal with said second memory unit
3, and this tertiary voltage V
3Scope is 1V～2V.
16. memory array programmed method according to claim 15 is characterized in that, said tertiary voltage V
3Be 1V.
17. according to claim 15 or 16 described memory array programmed methods, it is characterized in that, apply the 4th voltage V being positioned on the 4th bit line of same delegation and the coupling of adjacent the 4th memory cell drain terminal with said the 3rd memory cell
4, and the 4th voltage V
4Scope is 1V～5V.
18. memory array programmed method according to claim 17 is characterized in that, said the 4th voltage V
4Be 3V.
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| CN105280224A (en) * | 2014-07-08 | 2016-01-27 | 旺宏电子股份有限公司 | Memory device for reducing Program Disturb and programming method thereof |
| CN108492844A (en) * | 2018-03-26 | 2018-09-04 | 上海华虹宏力半导体制造有限公司 | A kind of double separate gate flash memory arrays and its programmed method |
| CN110459257A (en) * | 2019-08-19 | 2019-11-15 | 珠海创飞芯科技有限公司 | OTP in-line memory and its programmed method, read method |
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