CN110137173A - Memory and its operating method - Google Patents
Memory and its operating method Download PDFInfo
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- CN110137173A CN110137173A CN201910297081.9A CN201910297081A CN110137173A CN 110137173 A CN110137173 A CN 110137173A CN 201910297081 A CN201910297081 A CN 201910297081A CN 110137173 A CN110137173 A CN 110137173A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
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Abstract
The invention discloses a kind of memories, storage unit uses the structure of three gate structures and two source-drain areas, in array structure in a line include two control lines and a wordline, it is separately connected the corresponding control gate of storage unit and selection grid, storage unit is cascaded in same row, the storage unit of same row is connected with two bit lines, second source-drain area of each storage unit of the first source-drain area and even number line of each storage unit of odd-numbered line is all connected to the first bit line, first source-drain area of each storage unit of the second source-drain area and even number line of each storage unit of odd-numbered line is all connected to the second bit line, the memory cell structure and array structure of memory of the invention are able to achieve reasoning operation, and the input signal of reasoning operation uses the output voltage of the corresponding bit line of each column using the input current and output signal of the wordline of each row.The invention also discloses the operating methods of memory.The present invention, which is able to achieve, deposits calculation one operation.
Description
Technical field
The present invention relates to semiconductor integrated circuit fields, more particularly to a kind of memory.The invention further relates to one kind to deposit
The operating method of reservoir.
Background technique
As shown in Figure 1, being the structure chart of the storage unit (Cell) of existing memory；Each storage unit 1 includes: the first grid
Pole structure 104, second grid structure 105, third gate structure 106, the first source-drain area 102 and the second source-drain area 103.
The first grid structure 104 is by being formed in the first gate dielectric layer 107, the floating gate on 101 surface of semiconductor substrate
(Floating Gate, FG) the 108, second gate dielectric layer 109 and polysilicon control grid 110 are formed by stacking.First source-drain area 102
It is usually N+ doping with the second source-drain area 103, semiconductor substrate 101 is the silicon substrate of p-type doping.
The second grid structure 105 is by being formed in the third gate dielectric layer 111 and polysilicon on 101 surface of semiconductor substrate
Grid 112 form.
The third gate structure 106 is by being formed in the first gate dielectric layer 107, the floating gate on 101 surface of semiconductor substrate
108, the second gate dielectric layer 109 and polysilicon control grid 110 are formed by stacking.
It is made of the semiconductor substrate 101 between first source-drain area 102 and second source-drain area 103
Channel region.
The first grid structure 104, the second grid structure 105 and the third gate structure 106 are arranged in institute
It states on the channel region surface between the first source-drain area 102 and second source-drain area 103, by the first grid structure
104, the shape of the channel on channel region surface described in the second grid structure 105 and 106 co- controlling of third gate structure
At.
First control gate of the polysilicon control grid 110 of the first grid structure 104 as the storage unit 1
CCG0；Selection grid ((select gate)) of the polysilicon gate 112 of the second grid structure 105 as the storage unit 1
CWL；Second control gate CCG1 of the polysilicon control grid 110 of the third gate structure 106 as the storage unit 1.
The floating gate 108 of the first grid structure 104 is the first storage position, the floating gate 108 of the third gate structure 106
For the second storage position.
First source-drain area 102 is connected to source S, and the second source-drain area 103 is connected to drain D.
In existing memory, the programming to storage position is usually all using source thermoelectron injection (SSI), to deposit to second
Storage space is programmed in order to illustrate as follows:
The voltage of programming are as follows:
Selection grid CWL is 1.4V, this can be such that the channel of 105 bottom of second grid structure is formed；
First control gate CCG0 is 5V, this can be such that the channel of 104 bottom of first grid structure is formed；
Source S provides a program current, size such as 2 μ A；
Drain D adds 5.5V voltage, and third control gate CCG1 adds 8V voltage, the voltage meeting of drain D and third control gate CCG1
106 bottom of third gate structure is set to generate larger depletion region, electronics is flowed into the third from source S side by channel
It can be injected into after the depletion region of 106 bottom of gate structure in the floating gate 108 of the third gate structure 106, realize programming, it is this
The electron injection mode of programming is source thermoelectron injection (SSI), be can be realized using lesser program current.Existing storage
Device cannot achieve single storage bit manipulation, deposit calculation integration to cannot achieve.
Summary of the invention
Technical problem to be solved by the invention is to provide a kind of memory, it is able to achieve and deposits calculation one operation.For this purpose, this hair
It is bright that a kind of operating method of memory is also provided.
For this purpose, it includes multiple storage units that the present invention, which provides a kind of memory, each storage unit includes three grids
Structure and two source-drain areas, the gate structure are respectively first grid structure, second grid structure, third gate structure, institute
Stating source-drain area is respectively the first source-drain area and the second source-drain area.
The first grid structure is by being formed in the first gate dielectric layer, floating gate, the second gate medium of semiconductor substrate surface
Layer and polysilicon control grid are formed by stacking.
The second grid structure is made of the third gate dielectric layer and polysilicon gate for being formed in semiconductor substrate surface.
The third gate structure is by being formed in the first gate dielectric layer, floating gate, the second gate medium of semiconductor substrate surface
Layer and polysilicon control grid are formed by stacking.
Channel region is formed by the semiconductor substrate between first source-drain area and second source-drain area.
The first grid structure, the second grid structure and the third gate structure are arranged in first source and drain
On the channel region surface between area and second source-drain area, by the first grid structure, the second grid structure
With the formation of the channel on channel region surface described in the third gate structure co- controlling.
First control gate of the polysilicon control grid of the first grid structure as the storage unit；The second gate
Selection grid of the polysilicon gate of pole structure as the storage unit；The polysilicon control grid of the third gate structure is as institute
State the second control gate of storage unit.
The storage unit includes two storage positions, and the floating gate of the first grid structure is first to store position, and described the
The floating gate of three gate structures is the second storage position.
Each storage unit procession rearranges array structure, the array structure are as follows:
With including two control lines and a wordline in a line, the first control gate of each storage unit is all connected to pair
The first control line answered, selection grid are all connected to the corresponding wordline, and the second control gate is all connected to corresponding second control
Line.
Each storage unit in same row is cascaded and cascaded structure are as follows: except the first row and line number value are maximum
Outside last line, the first source-drain area of storage unit described in each row connects the second of the storage unit of previous adjacent row
Source-drain area, the second source-drain area of storage unit described in each row connect the first source and drain of the storage unit of the adjacent row of the latter
Area.
The storage unit of same row is connected with two bit lines, the first source-drain area of each storage unit of odd-numbered line
It is all connected to the first bit line with the second source-drain area of each storage unit of even number line, each storage unit of odd-numbered line
First source-drain area of each storage unit of the second source-drain area and even number line is all connected to the second bit line.
The operation of the memory includes reasoning (Inference) operation, and the input signal of the reasoning operation is using each
The input current of the capable wordline, the output signal of the reasoning operation of the memory is using each output for arranging corresponding bit line
Voltage.
A further improvement is that in the reasoning operation of the memory, the first working condition of same row are as follows:
The corresponding storage position of the source-drain area being connected with first bit line is by selection storage position and the second bit line phase
The corresponding storage position of source-drain area even is non-selected storage position, and each described by the corresponding control line in selection storage position to meet 0V electric
Pressure, the corresponding control line in each unselected storage position, which connects, makes the first positive voltage, the big Grain Full of first positive voltage
Foot makes the channel region surface transoid of the unselected storage position bottom form channel, and first bit line connects 0V voltage,
Each wordline all connects the input current as the input signal, forms the output signal from the second line.
A further improvement is that in the reasoning operation of the memory, second of working condition of same row are as follows:
The corresponding storage position of the source-drain area being connected with second bit line is by selection storage position and the first bit line phase
The corresponding storage position of source-drain area even is non-selected storage position, and each described by the corresponding control line in selection storage position to meet 0V electric
Pressure, the corresponding control line in each unselected storage position, which connects, makes the first positive voltage, the big Grain Full of first positive voltage
Foot makes the channel region surface transoid of the unselected storage position bottom form channel, and second bit line connects 0V voltage,
Each wordline all connects the input current as the input signal, forms the output signal from first bit line.
A further improvement is that the operation of the memory further includes study (Learning) operation, the learning manipulation
It is operated including weight gain (Weight up), in the weight gain operation, the working condition of same row are as follows:
Each wordline all connects the second positive voltage.
Each control line all connects the first negative voltage；Second positive voltage be greater than first positive voltage, described second
The size of the difference of positive voltage and first negative voltage meets the erasing realized to each storage position.
Each bit line all connects 0V voltage.
A further improvement is that the learning manipulation includes loss of weight (Weight down) operation, in the loss of weight operation,
The first working condition of same row are as follows:
The corresponding storage position of the source-drain area being connected with first bit line is by selection storage position and the second bit line phase
The corresponding storage position of source-drain area even is non-selected storage position, each described to store the corresponding control line in position by selection and connect third
Positive voltage.
The corresponding control line in each unselected storage position, which connects, makes the first positive voltage.
Each wordline all connects the 4th positive voltage.
First bit line connects the 5th positive voltage.
Second bit line connects write current.
4th positive voltage, which meets, makes the channel region surface transoid of the second grid structural base form channel,
The third positive voltage, the 5th positive voltage and said write electric current, which meet, to be realized to described by selection storage position progress source
Thermoelectron injection programming.
A further improvement is that the learning manipulation includes loss of weight operation, and in the loss of weight operation, second of same row
Working condition are as follows:
The corresponding storage position of the source-drain area being connected with second bit line is by selection storage position and the first bit line phase
The corresponding storage position of source-drain area even is non-selected storage position, each described to store the corresponding control line in position by selection and connect third
Positive voltage.
The corresponding control line in each unselected storage position, which connects, makes the first positive voltage.
Each wordline all connects the 4th positive voltage.
First bit line connects write current.
Second bit line connects the 5th positive voltage.
A further improvement is that in the first working condition of the same row in the reasoning operation of the memory, institute
Output signal is stated by determining from the output electric current of second bit line, the output electric current of second bit line is each wordline
The accumulated value that the input current is added multiplied by corresponding coefficient, the input current of each wordline multiplied by coefficient
It is determined by the programming depth of the corresponding storage position.
A further improvement is that in second of working condition of the same row in the reasoning operation of the memory, institute
Output signal is stated by determining from the output electric current of first bit line, the output electric current of first bit line is each wordline
The accumulated value that the input current is added multiplied by corresponding coefficient, the input current of each wordline multiplied by coefficient
It is determined by the programming depth of the corresponding storage position.
In order to solve the above technical problems, memory includes that multiple storages are single in the operating method of memory provided by the invention
Member, each storage unit include three gate structures and two source-drain areas, the gate structure be respectively first grid structure,
Second grid structure, third gate structure, the source-drain area are respectively the first source-drain area and the second source-drain area.
The first grid structure is by being formed in the first gate dielectric layer, floating gate, the second gate medium of semiconductor substrate surface
Layer and polysilicon control grid are formed by stacking.
The second grid structure is made of the third gate dielectric layer and polysilicon gate for being formed in semiconductor substrate surface.
The third gate structure is by being formed in the first gate dielectric layer, floating gate, the second gate medium of semiconductor substrate surface
Layer and polysilicon control grid are formed by stacking.
Channel region is formed by the semiconductor substrate between first source-drain area and second source-drain area.
The first grid structure, the second grid structure and the third gate structure are arranged in first source and drain
On the channel region surface between area and second source-drain area, by the first grid structure, the second grid structure
With the formation of the channel on channel region surface described in the third gate structure co- controlling.
First control gate of the polysilicon control grid of the first grid structure as the storage unit；The second gate
Selection grid of the polysilicon gate of pole structure as the storage unit；The polysilicon control grid of the third gate structure is as institute
State the second control gate of storage unit.
The storage unit includes two storage positions, and the floating gate of the first grid structure is first to store position, and described the
The floating gate of three gate structures is the second storage position.
Each storage unit procession rearranges array structure, the array structure are as follows:
With including two control lines and a wordline in a line, the first control gate of each storage unit is all connected to pair
The first control line answered, selection grid are all connected to the corresponding wordline, and the second control gate is all connected to corresponding second control
Line.
Each storage unit in same row is cascaded and cascaded structure are as follows: except the first row and line number value are maximum
Outside last line, the first source-drain area of storage unit described in each row connects the second of the storage unit of previous adjacent row
Source-drain area, the second source-drain area of storage unit described in each row connect the first source and drain of the storage unit of the adjacent row of the latter
Area.
The storage unit of same row is connected with two bit lines, the first source-drain area of each storage unit of odd-numbered line
It is all connected to the first bit line with the second source-drain area of each storage unit of even number line, each storage unit of odd-numbered line
First source-drain area of each storage unit of the second source-drain area and even number line is all connected to the second bit line.
The operating method of the memory includes reasoning operation, and the input signal of the reasoning operation is using the described of each row
The input current of wordline, the output signal of the reasoning operation of the memory is using each output voltage for arranging corresponding bit line.
A further improvement is that in the reasoning operation of the memory, the first working condition of same row are as follows:
The corresponding storage position of the source-drain area being connected with first bit line is by selection storage position and the second bit line phase
The corresponding storage position of source-drain area even is non-selected storage position, and each described by the corresponding control line in selection storage position to meet 0V electric
Pressure, the corresponding control line in each unselected storage position, which connects, makes the first positive voltage, the big Grain Full of first positive voltage
Foot makes the channel region surface transoid of the unselected storage position bottom form channel, and first bit line connects 0V voltage,
Each wordline all connects the input current as the input signal, forms the output signal from the second line.
A further improvement is that in the reasoning operation of the memory, second of working condition of same row are as follows:
The corresponding storage position of the source-drain area being connected with second bit line is by selection storage position and the first bit line phase
The corresponding storage position of source-drain area even is non-selected storage position, and each described by the corresponding control line in selection storage position to meet 0V electric
Pressure, the corresponding control line in each unselected storage position, which connects, makes the first positive voltage, the big Grain Full of first positive voltage
Foot makes the channel region surface transoid of the unselected storage position bottom form channel, and second bit line connects 0V voltage,
Each wordline all connects the input current as the input signal, forms the output signal from first bit line.
A further improvement is that the operating method of the memory further includes learning manipulation, the learning manipulation includes increasing
It operates again, in the weight gain operation, the working condition of same row are as follows:
Each wordline all connects the second positive voltage.
Each control line all connects the first negative voltage；Second positive voltage be greater than first positive voltage, described second
The size of the difference of positive voltage and first negative voltage meets the erasing realized to each storage position.
Each bit line all connects 0V voltage.
A further improvement is that the learning manipulation includes loss of weight operation, in loss of weight operation, same row the first
Working condition are as follows:
The corresponding storage position of the source-drain area being connected with first bit line is by selection storage position and the second bit line phase
The corresponding storage position of source-drain area even is non-selected storage position, each described to store the corresponding control line in position by selection and connect third
Positive voltage.
The corresponding control line in each unselected storage position, which connects, makes the first positive voltage.
Each wordline all connects the 4th positive voltage.
First bit line connects the 5th positive voltage.
Second bit line connects write current.
4th positive voltage, which meets, makes the channel region surface transoid of the second grid structural base form channel,
The third positive voltage, the 5th positive voltage and said write electric current, which meet, to be realized to described by selection storage position progress source
Thermoelectron injection programming.
The learning manipulation includes loss of weight operation, in the loss of weight operation, second of working condition of same row are as follows:
The corresponding storage position of the source-drain area being connected with second bit line is by selection storage position and the first bit line phase
The corresponding storage position of source-drain area even is non-selected storage position, each described to store the corresponding control line in position by selection and connect third
Positive voltage.
The corresponding control line in each unselected storage position, which connects, makes the first positive voltage.
Each wordline all connects the 4th positive voltage.
First bit line connects write current.
Second bit line connects the 5th positive voltage.
A further improvement is that in the first working condition of the same row in the reasoning operation of the memory, institute
Output signal is stated by determining from the output electric current of second bit line, the output electric current of second bit line is each wordline
The accumulated value that the input current is added multiplied by corresponding coefficient, the input current of each wordline multiplied by coefficient
It is determined by the programming depth of the corresponding storage position.
A further improvement is that in second of working condition of the same row in the reasoning operation of the memory, institute
Output signal is stated by determining from the output electric current of first bit line, the output electric current of first bit line is each wordline
The accumulated value that the input current is added multiplied by corresponding coefficient, the input current of each wordline multiplied by coefficient
It is determined by the programming depth of the corresponding storage position.
The storage unit of memory of the present invention uses the structure of three gate structures and two source-drain areas, same in array structure
Include two control lines and a wordline in a line, be separately connected the corresponding control gate of storage unit and selection grid, in same row
Storage unit is cascaded, and the storage unit of same row is connected with two bit lines, the first source of each storage unit of odd-numbered line
Second source-drain area of each storage unit of drain region and even number line is all connected to the first bit line, and the second of each storage unit of odd-numbered line
First source-drain area of each storage unit of source-drain area and even number line is all connected to the second bit line, the storage list of memory of the invention
Meta structure and array structure are able to achieve reasoning operation, and the input signal of reasoning operation is using the input electricity of the wordline of each row
Stream and output signal are using each output voltage for arranging corresponding bit line, so the present invention, which is able to achieve, deposits calculation one operation.
The present invention, which is also able to achieve, deposits corresponding learning manipulation in calculation one operation, including weight gain operation and loss of weight operation.
Detailed description of the invention
The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:
Fig. 1 is the structure chart of the storage unit of existing memory；
Fig. 2 is the array junctions composition of memory of the embodiment of the present invention.
Specific embodiment
Memory of the embodiment of the present invention:
The structure chart of the storage unit 1 of memory of the embodiment of the present invention also please refers to described in Fig. 1, and Fig. 2 is implementation of the present invention
The array junctions composition of example memory, memory of the embodiment of the present invention includes multiple storage units 1, and each storage unit 1 includes
Three gate structures and two source-drain areas, the gate structure are respectively first grid structure 104, second grid structure 105,
Three gate structures 106, the source-drain area are respectively the first source-drain area 102 and the second source-drain area 103.
The first grid structure 104 is by being formed in the first gate dielectric layer 107, the floating gate on 101 surface of semiconductor substrate
108, the second gate dielectric layer 109 and polysilicon control grid 110 are formed by stacking.
The second grid structure 105 is by being formed in the third gate dielectric layer 111 and polysilicon on 101 surface of semiconductor substrate
Grid 112 form.
The third gate structure 106 is by being formed in the first gate dielectric layer 107, the floating gate on 101 surface of semiconductor substrate
108, the second gate dielectric layer 109 and polysilicon control grid 110 are formed by stacking.
In the embodiment of the present invention, the semiconductor substrate 101 is silicon substrate, first gate dielectric layer 107, described second
The material of gate dielectric layer 109 and the third gate dielectric layer 111 is all oxide layer.
It is made of the semiconductor substrate 101 between first source-drain area 102 and second source-drain area 103
Channel region.
The first grid structure 104, the second grid structure 105 and the third gate structure 106 are arranged in institute
It states on the channel region surface between the first source-drain area 102 and second source-drain area 103, by the first grid structure
104, the shape of the channel on channel region surface described in the second grid structure 105 and 106 co- controlling of third gate structure
At.
First control gate of the polysilicon control grid 110 of the first grid structure 104 as the storage unit 1
CCG0；Selection grid CWL of the polysilicon gate 112 of the second grid structure 105 as the storage unit 1；The third grid
Second control gate CCG1 of the polysilicon control grid 110 of pole structure 106 as the storage unit 1.
The storage unit 1 includes two storage positions, and the floating gate 108 of the first grid structure 104 is the first storage position,
The floating gate 108 of the third gate structure 106 is the second storage position.
Each 1 procession of the storage unit rearranges array structure, the array structure are as follows:
With, including two control lines and a wordline, the first control gate CCG0 of each storage unit 1 connects in a line
It is connected to corresponding first control line, selection grid CWL is all connected to the corresponding wordline, and the second control gate CCG1 is all connected to pair
The second control line answered.
Each storage unit 1 in same row is cascaded and cascaded structure are as follows: except the first row and line number value are maximum
Last line outside, the first source-drain area 102 of storage unit 1 described in each row connects the storage unit of previous adjacent row
1 the second source-drain area 103, the storage of the adjacent row of the second source-drain area 103 connection the latter of storage unit 1 described in each row
First source-drain area 102 of unit 1.
The storage unit 1 of same row is connected with two bit lines, the first source and drain of each storage unit 1 of odd-numbered line
Second source-drain area 103 of each storage unit 1 of area 102 and even number line is all connected to the first bit line, odd-numbered line it is each described
First source-drain area 102 of each storage unit 1 of the second source-drain area 103 and even number line of storage unit 1 is all connected to second
Bit line.
In Fig. 2, the wordline of each row adds row number to indicate with WL respectively, such as WL0, WL1, WL2.
First control line of each row adds row number to add 0 to indicate with CG respectively, such as CG00, CG10, CG20.
Second control line of each row adds row number to add 1 to indicate with CG respectively, such as CG01, CG11, CG21.
First bit line respectively arranged adds column number to add 0 to indicate with BL respectively, such as BL00, BL10.
Second bit line respectively arranged adds column number to add 1 to indicate with BL respectively, such as BL01, BL11.
The operation of the memory includes reasoning operation, and the input signal of the reasoning operation uses the wordline of each row
Input current, commonly enter signal is indicated with X, herein X and IWL0、IWL1And IWL2Etc. correlations.
The output signal of the reasoning operation of the memory is using each output voltage for arranging corresponding bit line, in general, output
Signal indicated using Y, Y and V hereinBL00、VBL10、VBL01And VBL11Etc. correlations.
In the reasoning operation of the memory, the first working condition of same row are as follows:
The corresponding storage position of the source-drain area being connected with first bit line is by selection storage position and the second bit line phase
The corresponding storage position of source-drain area even is non-selected storage position, is to number the column for being 0 in the case of first row: by selection storage position point
Not Wei storage corresponding with control line CG00, CG11, CG20 position, non-selected storage position be respectively and control line CG01, CG10,
The corresponding storage position CG21.
It is each it is described 0V voltage is connect by the corresponding control line in selection storage position, each unselected storage position is corresponding
The control line, which connects, makes the first positive voltage, and the size of first positive voltage meets the institute for making the unselected storage position bottom
It states channel region surface transoid and forms channel, first bit line connects 0V voltage, and each wordline all connects the input current conduct
The input signal forms the output signal from the second line.
In the embodiment of the present invention, in the first working condition of the same row in the reasoning operation of the memory, institute
Output signal is stated by determining from the output electric current of second bit line, the output electric current of second bit line is each wordline
The accumulated value that the input current is added multiplied by corresponding coefficient, the input current of each wordline multiplied by coefficient
It is determined by the programming depth of the corresponding storage position.It is described as follows now in conjunction with formula:
By the corresponding input current I of each wordlineWLIndicate and formed the bit line I of the output signalBLTable
Show then have input current and the relationship of the corresponding electric current of output signal that can be formulated are as follows:
Wherein, y indicates the corresponding electric current of output signal, IiIndicate the electric current I for the capable wordlineWL, β expression is by depositing
The coefficient that the programming depth of the corresponding storage position of storage unit determines, xiIt indicates multiplied by the I after factor betai。
In the reasoning operation of the memory, second of working condition of same row are as follows:
The corresponding storage position of the source-drain area being connected with second bit line is by selection storage position and the first bit line phase
The corresponding storage position of source-drain area even is non-selected storage position, by taking first row as an example: being selected storage position respectively and control line
The corresponding storage position CG01, CG10, CG21, non-selected storage position is respectively and control line CG00, CG11, CG20 are corresponding
Store position.
It is each it is described 0V voltage is connect by the corresponding control line in selection storage position, each unselected storage position is corresponding
The control line, which connects, makes the first positive voltage, and the size of first positive voltage meets the institute for making the unselected storage position bottom
It states channel region surface transoid and forms channel, second bit line connects 0V voltage, and each wordline all connects the input current conduct
The input signal forms the output signal from first bit line.
In second of working condition of the same row in the reasoning operation of the memory, the output signal is by from institute
State the first bit line output electric current determine, first bit line output electric current be each wordline the input current multiplied by
The accumulated value that corresponding coefficient is added, the input current of each wordline multiplied by coefficient by the corresponding storage
The programming depth of position determines.
The operation of the memory further includes learning manipulation, and the learning manipulation includes weight gain operation, the weight gain operation
In, the working condition of same row are as follows:
Each wordline all connects the second positive voltage.
Each control line all connects the first negative voltage；Second positive voltage be greater than first positive voltage, described second
The size of the difference of positive voltage and first negative voltage meets the erasing realized to each storage position.
Each bit line all connects 0V voltage.
The learning manipulation includes loss of weight (Weight down) operation, in the loss of weight operation, the first work of same row
Make state are as follows:
The corresponding storage position of the source-drain area being connected with first bit line is by selection storage position and the second bit line phase
The corresponding storage position of source-drain area even is non-selected storage position, each described to store the corresponding control line in position by selection and connect third
Positive voltage.
The corresponding control line in each unselected storage position, which connects, makes the first positive voltage.
Each wordline all connects the 4th positive voltage.
First bit line connects the 5th positive voltage.
Second bit line connects write current.
4th positive voltage, which meets, makes the channel region surface transoid of 105 bottom of second grid structure form ditch
Road, the third positive voltage, the 5th positive voltage and said write electric current, which meet, to be realized to described by selection storage position progress
Source thermoelectron injection programming.
The learning manipulation includes loss of weight operation, in the loss of weight operation, second of working condition of same row are as follows:
The corresponding storage position of the source-drain area being connected with second bit line is by selection storage position and the first bit line phase
The corresponding storage position of source-drain area even is non-selected storage position, each described to store the corresponding control line in position by selection and connect third
Positive voltage.
The corresponding control line in each unselected storage position, which connects, makes the first positive voltage.
Each wordline all connects the 4th positive voltage.
First bit line connects write current.
Second bit line connects the 5th positive voltage.
Now with a specific parameter declaration once various voltage swings used by the embodiment of the present invention:
First positive voltage is 5V, and second positive voltage is 6V, and the third positive voltage is 7V, the 4th positive electricity
Pressure is 1.4V, and the 5th positive voltage is 4.5V, and first negative voltage is -6V, and write current generallys use Idp expression.
Structure of the storage unit 1 of memory of the embodiment of the present invention using three gate structures and two source-drain areas, array
With including two control lines and a wordline in a line in structure, it is separately connected the corresponding control gate of storage unit 1 and selection grid
CWL, storage unit 1 is cascaded in same row, and the storage unit 1 of same row is connected with two bit lines, and odd-numbered line is respectively deposited
Second source-drain area 103 of each storage unit 1 of the first source-drain area 102 and even number line of storage unit 1 is all connected to the first bit line, odd
First source-drain area 102 of each storage unit 1 of the second source-drain area 103 and even number line of several rows of each storage unit 1 is all connected to
Second bit line, 1 structure of storage unit and array structure of memory of the invention are able to achieve reasoning operation, and reasoning operation is defeated
Enter output voltage of the signal using the input current and output signal of the wordline of each row using the corresponding bit line of each column, institute
It is able to achieve with the embodiment of the present invention and deposits calculation one operation.
The embodiment of the present invention, which is also able to achieve, deposits corresponding learning manipulation in calculation one operation, including weight gain operation and loss of weight behaviour
Make.
The operating method of memory of the embodiment of the present invention:
Memory includes multiple storage units 1 in the operating method of memory of the embodiment of the present invention, each storage unit 1
Including three gate structures and two source-drain areas, the gate structure is respectively first grid structure 104, second grid structure
105, third gate structure 106, the source-drain area are respectively the first source-drain area 102 and the second source-drain area 103.
The first grid structure 104 is by being formed in the first gate dielectric layer 107, the floating gate on 101 surface of semiconductor substrate
108, the second gate dielectric layer 109 and polysilicon control grid 110 are formed by stacking.
The second grid structure 105 is by being formed in the third gate dielectric layer 111 and polysilicon on 101 surface of semiconductor substrate
Grid 112 form.
The third gate structure 106 is by being formed in the first gate dielectric layer 107, the floating gate on 101 surface of semiconductor substrate
108, the second gate dielectric layer 109 and polysilicon control grid 110 are formed by stacking.
It is made of the semiconductor substrate 101 between first source-drain area 102 and second source-drain area 103
Channel region.
The first grid structure 104, the second grid structure 105 and the third gate structure 106 are arranged in institute
It states on the channel region surface between the first source-drain area 102 and second source-drain area 103, by the first grid structure
104, the shape of the channel on channel region surface described in the second grid structure 105 and 106 co- controlling of third gate structure
At.
First control gate of the polysilicon control grid 110 of the first grid structure 104 as the storage unit 1
CCG0；Selection grid CWL of the polysilicon gate 112 of the second grid structure 105 as the storage unit 1；The third grid
Second control gate CCG1 of the polysilicon control grid 110 of pole structure 106 as the storage unit 1.
The storage unit 1 includes two storage positions, and the floating gate 108 of the first grid structure 104 is the first storage position,
The floating gate 108 of the third gate structure 106 is the second storage position.
Each 1 procession of the storage unit rearranges array structure, the array structure are as follows:
With, including two control lines and a wordline, the first control gate CCG0 of each storage unit 1 connects in a line
It is connected to corresponding first control line, selection grid CWL is all connected to the corresponding wordline, and the second control gate CCG1 is all connected to pair
The second control line answered.
Each storage unit 1 in same row is cascaded and cascaded structure are as follows: except the first row and line number value are maximum
Last line outside, the first source-drain area 102 of storage unit 1 described in each row connects the storage unit of previous adjacent row
1 the second source-drain area 103, the storage of the adjacent row of the second source-drain area 103 connection the latter of storage unit 1 described in each row
First source-drain area 102 of unit 1.
The storage unit 1 of same row is connected with two bit lines, the first source and drain of each storage unit 1 of odd-numbered line
Second source-drain area 103 of each storage unit 1 of area 102 and even number line is all connected to the first bit line, odd-numbered line it is each described
First source-drain area 102 of each storage unit 1 of the second source-drain area 103 and even number line of storage unit 1 is all connected to second
Bit line.
The operating method of the memory includes reasoning operation, and the input signal of the reasoning operation is using the described of each row
The input current of wordline, the output signal of the reasoning operation of the memory is using each output voltage for arranging corresponding bit line.
In the reasoning operation of the memory, the first working condition of same row are as follows:
The corresponding storage position of the source-drain area being connected with first bit line is by selection storage position and the second bit line phase
The corresponding storage position of source-drain area even is non-selected storage position, and each described by the corresponding control line in selection storage position to meet 0V electric
Pressure, the corresponding control line in each unselected storage position, which connects, makes the first positive voltage, the big Grain Full of first positive voltage
Foot makes the channel region surface transoid of the unselected storage position bottom form channel, and first bit line connects 0V voltage,
Each wordline all connects the input current as the input signal, forms the output signal from the second line.
In the first working condition of the same row in the reasoning operation of the memory, the output signal is by from institute
State the second bit line output electric current determine, second bit line output electric current be each wordline the input current multiplied by
The accumulated value that corresponding coefficient is added, the input current of each wordline multiplied by coefficient by the corresponding storage
The programming depth of position determines.
In the reasoning operation of the memory, second of working condition of same row are as follows:
The corresponding storage position of the source-drain area being connected with second bit line is by selection storage position and the first bit line phase
The corresponding storage position of source-drain area even is non-selected storage position, and each described by the corresponding control line in selection storage position to meet 0V electric
Pressure, the corresponding control line in each unselected storage position, which connects, makes the first positive voltage, the big Grain Full of first positive voltage
Foot makes the channel region surface transoid of the unselected storage position bottom form channel, and second bit line connects 0V voltage,
Each wordline all connects the input current as the input signal, forms the output signal from first bit line.
In second of working condition of the same row in the reasoning operation of the memory, the output signal is by from institute
State the first bit line output electric current determine, first bit line output electric current be each wordline the input current multiplied by
The accumulated value that corresponding coefficient is added, the input current of each wordline multiplied by coefficient by the corresponding storage
The programming depth of position determines.
The operating method of the memory further includes learning manipulation, and the learning manipulation includes weight gain operation, the weight gain
In operation, the working condition of same row are as follows:
Each wordline all connects the second positive voltage.
Each control line all connects the first negative voltage；Second positive voltage be greater than first positive voltage, described second
The size of the difference of positive voltage and first negative voltage meets the erasing realized to each storage position.
Each bit line all connects 0V voltage.
The learning manipulation includes loss of weight operation, in the loss of weight operation, the first working condition of same row are as follows:
The corresponding storage position of the source-drain area being connected with first bit line is by selection storage position and the second bit line phase
The corresponding storage position of source-drain area even is non-selected storage position, each described to store the corresponding control line in position by selection and connect third
Positive voltage.
The corresponding control line in each unselected storage position, which connects, makes the first positive voltage.
Each wordline all connects the 4th positive voltage.
First bit line connects the 5th positive voltage.
Second bit line connects write current.
4th positive voltage, which meets, makes the channel region surface transoid of 105 bottom of second grid structure form ditch
Road, the third positive voltage, the 5th positive voltage and said write electric current, which meet, to be realized to described by selection storage position progress
Source thermoelectron injection programming.
The learning manipulation includes loss of weight operation, in the loss of weight operation, second of working condition of same row are as follows:
The corresponding storage position of the source-drain area being connected with second bit line is by selection storage position and the first bit line phase
The corresponding storage position of source-drain area even is non-selected storage position, each described to store the corresponding control line in position by selection and connect third
Positive voltage.
The corresponding control line in each unselected storage position, which connects, makes the first positive voltage.
Each wordline all connects the 4th positive voltage.
First bit line connects write current.
Second bit line connects the 5th positive voltage.
The present invention has been described in detail through specific embodiments, but these are not constituted to limit of the invention
System.Without departing from the principles of the present invention, those skilled in the art can also make many modification and improvement, these are also answered
It is considered as protection scope of the present invention.
Claims (15)
1. a kind of memory, it is characterised in that: including multiple storage units, each storage unit include three gate structures and
Two source-drain areas, the gate structure are respectively first grid structure, second grid structure, third gate structure, the source and drain
Area is respectively the first source-drain area and the second source-drain area；
The first grid structure by be formed in the first gate dielectric layer of semiconductor substrate surface, floating gate, the second gate dielectric layer and
Polysilicon control grid is formed by stacking；
The second grid structure is made of the third gate dielectric layer and polysilicon gate for being formed in semiconductor substrate surface；
The third gate structure by be formed in the first gate dielectric layer of semiconductor substrate surface, floating gate, the second gate dielectric layer and
Polysilicon control grid is formed by stacking；
Channel region is formed by the semiconductor substrate between first source-drain area and second source-drain area；
The first grid structure, the second grid structure and the third gate structure be arranged in first source-drain area and
On the channel region surface between second source-drain area, by the first grid structure, the second grid structure and institute
State the formation of the channel on channel region surface described in third gate structure co- controlling；
First control gate of the polysilicon control grid of the first grid structure as the storage unit；The second grid knot
Selection grid of the polysilicon gate of structure as the storage unit；The polysilicon control grid of the third gate structure is deposited described in being used as
Second control gate of storage unit；
The storage unit includes two storage positions, and the floating gate of the first grid structure is the first storage position, the third grid
The floating gate of pole structure is the second storage position；
Each storage unit procession rearranges array structure, the array structure are as follows:
With including two control lines and a wordline in a line, the first control gate of each storage unit is all connected to corresponding
First control line, selection grid are all connected to the corresponding wordline, and the second control gate is all connected to corresponding second control line；
Each storage unit in same row is cascaded and cascaded structure are as follows: except the first row and line number value are maximum last
Outside a line, the first source-drain area of storage unit described in each row connects the second source and drain of the storage unit of previous adjacent row
Area, the second source-drain area of storage unit described in each row connect the first source-drain area of the storage unit of the adjacent row of the latter；
The storage unit of same row is connected with two bit lines, the first source-drain area and idol of each storage unit of odd-numbered line
Second source-drain area of several rows of each storage unit is all connected to the first bit line, and the second of each storage unit of odd-numbered line
First source-drain area of each storage unit of source-drain area and even number line is all connected to the second bit line；
The operation of the memory includes reasoning operation, and the input signal of the reasoning operation uses the defeated of the wordline of each row
Enter electric current, the output signal of the reasoning operation of the memory is using each output voltage for arranging corresponding bit line.
2. memory as described in claim 1, it is characterised in that: in the reasoning operation of the memory, the of same row
A kind of working condition are as follows:
The corresponding storage position of the source-drain area being connected with first bit line is to be connected by selection storage position with second bit line
The corresponding storage position of source-drain area is non-selected storage position, it is each it is described 0V voltage is connect by the corresponding control line in selection storage position,
The corresponding control line in each unselected storage position, which connects, makes the first positive voltage, and the size satisfaction of first positive voltage makes
The channel region surface transoid of the unselected storage position bottom forms channel, and first bit line meets 0V voltage, each institute
It states wordline and all connects the input current as the input signal, form the output signal from the second line.
3. memory as claimed in claim 2, it is characterised in that: in the reasoning operation of the memory, the of same row
Two kinds of working conditions are as follows:
The corresponding storage position of the source-drain area being connected with second bit line is to be connected by selection storage position with first bit line
The corresponding storage position of source-drain area is non-selected storage position, it is each it is described 0V voltage is connect by the corresponding control line in selection storage position,
The corresponding control line in each unselected storage position, which connects, makes the first positive voltage, and the size satisfaction of first positive voltage makes
The channel region surface transoid of the unselected storage position bottom forms channel, and second bit line meets 0V voltage, each institute
It states wordline and all connects the input current as the input signal, form the output signal from first bit line.
4. memory as claimed in claim 3, it is characterised in that: the operation of the memory further includes learning manipulation, described
Learning manipulation includes weight gain operation, in the weight gain operation, the working condition of same row are as follows:
Each wordline all connects the second positive voltage；
Each control line all connects the first negative voltage；Second positive voltage is greater than first positive voltage, second positive electricity
The size of pressure and the difference of first negative voltage meets the erasing realized to each storage position；
Each bit line all connects 0V voltage.
5. memory as claimed in claim 4, it is characterised in that: the learning manipulation includes loss of weight operation, the loss of weight behaviour
In work, the first working condition of same row are as follows:
The corresponding storage position of the source-drain area being connected with first bit line is to be connected by selection storage position with second bit line
The corresponding storage position of source-drain area is non-selected storage position, each described to connect third positive electricity by the corresponding control line in selection storage position
Pressure；
The corresponding control line in each unselected storage position, which connects, makes the first positive voltage；
Each wordline all connects the 4th positive voltage；
First bit line connects the 5th positive voltage；
Second bit line connects write current；
4th positive voltage, which meets, makes the channel region surface transoid of the second grid structural base form channel, described
Third positive voltage, the 5th positive voltage and said write electric current, which meet, to be realized to described by selection storage position progress source thermoelectricity
Sub- injection programming.
6. memory as claimed in claim 5, it is characterised in that: the learning manipulation includes loss of weight operation, the loss of weight behaviour
In work, second of working condition of same row are as follows:
The corresponding storage position of the source-drain area being connected with second bit line is to be connected by selection storage position with first bit line
The corresponding storage position of source-drain area is non-selected storage position, each described to connect third positive electricity by the corresponding control line in selection storage position
Pressure；
The corresponding control line in each unselected storage position, which connects, makes the first positive voltage；
Each wordline all connects the 4th positive voltage；
First bit line connects write current；
Second bit line connects the 5th positive voltage.
7. memory as claimed in claim 2, it is characterised in that: the of the same row in the reasoning operation of the memory
In a kind of working condition, the output signal from the output electric current of second bit line by determining, the output of second bit line
Electric current is the accumulated value that is added multiplied by corresponding coefficient of the input current of each wordline, each wordline it is described
Input current multiplied by coefficient by it is corresponding it is described storage position programming depth determine.
8. memory as claimed in claim 3, it is characterised in that: the of the same row in the reasoning operation of the memory
In two kinds of working conditions, the output signal from the output electric current of first bit line by determining, the output of first bit line
Electric current is the accumulated value that is added multiplied by corresponding coefficient of the input current of each wordline, each wordline it is described
Input current multiplied by coefficient by it is corresponding it is described storage position programming depth determine.
9. a kind of operating method of memory, it is characterised in that: memory includes multiple storage units, each storage unit packet
Three gate structures and two source-drain areas are included, the gate structure is respectively first grid structure, second grid structure, third grid
Pole structure, the source-drain area are respectively the first source-drain area and the second source-drain area；
The first grid structure by be formed in the first gate dielectric layer of semiconductor substrate surface, floating gate, the second gate dielectric layer and
Polysilicon control grid is formed by stacking；
The second grid structure is made of the third gate dielectric layer and polysilicon gate for being formed in semiconductor substrate surface；
The third gate structure by be formed in the first gate dielectric layer of semiconductor substrate surface, floating gate, the second gate dielectric layer and
Polysilicon control grid is formed by stacking；
Channel region is formed by the semiconductor substrate between first source-drain area and second source-drain area；
The first grid structure, the second grid structure and the third gate structure be arranged in first source-drain area and
On the channel region surface between second source-drain area, by the first grid structure, the second grid structure and institute
State the formation of the channel on channel region surface described in third gate structure co- controlling；
First control gate of the polysilicon control grid of the first grid structure as the storage unit；The second grid knot
Selection grid of the polysilicon gate of structure as the storage unit；The polysilicon control grid of the third gate structure is deposited described in being used as
Second control gate of storage unit；
The storage unit includes two storage positions, and the floating gate of the first grid structure is the first storage position, the third grid
The floating gate of pole structure is the second storage position；
Each storage unit procession rearranges array structure, the array structure are as follows:
With including two control lines and a wordline in a line, the first control gate of each storage unit is all connected to corresponding
First control line, selection grid are all connected to the corresponding wordline, and the second control gate is all connected to corresponding second control line；
Each storage unit in same row is cascaded and cascaded structure are as follows: except the first row and line number value are maximum last
Outside a line, the first source-drain area of storage unit described in each row connects the second source and drain of the storage unit of previous adjacent row
Area, the second source-drain area of storage unit described in each row connect the first source-drain area of the storage unit of the adjacent row of the latter；
The storage unit of same row is connected with two bit lines, the first source-drain area and idol of each storage unit of odd-numbered line
Second source-drain area of several rows of each storage unit is all connected to the first bit line, and the second of each storage unit of odd-numbered line
First source-drain area of each storage unit of source-drain area and even number line is all connected to the second bit line；
The operating method of the memory includes reasoning operation, and the input signal of the reasoning operation uses the wordline of each row
Input current, the output signal of the reasoning operation of the memory using the corresponding bit line of each column output voltage.
10. the operating method of memory as claimed in claim 9, it is characterised in that: in the reasoning operation of the memory,
The first working condition of same row are as follows:
The corresponding storage position of the source-drain area being connected with first bit line is to be connected by selection storage position with second bit line
The corresponding storage position of source-drain area is non-selected storage position, it is each it is described 0V voltage is connect by the corresponding control line in selection storage position,
The corresponding control line in each unselected storage position, which connects, makes the first positive voltage, and the size satisfaction of first positive voltage makes
The channel region surface transoid of the unselected storage position bottom forms channel, and first bit line meets 0V voltage, each institute
It states wordline and all connects the input current as the input signal, form the output signal from the second line.
11. the operating method of memory as claimed in claim 10, it is characterised in that: operated in the reasoning of the memory
In, second of working condition of same row are as follows:
The corresponding storage position of the source-drain area being connected with second bit line is to be connected by selection storage position with first bit line
The corresponding storage position of source-drain area is non-selected storage position, it is each it is described 0V voltage is connect by the corresponding control line in selection storage position,
The corresponding control line in each unselected storage position, which connects, makes the first positive voltage, and the size satisfaction of first positive voltage makes
The channel region surface transoid of the unselected storage position bottom forms channel, and second bit line meets 0V voltage, each institute
It states wordline and all connects the input current as the input signal, form the output signal from first bit line.
12. the operating method of memory as claimed in claim 11, it is characterised in that: the operating method of the memory is also wrapped
Learning manipulation is included, the learning manipulation includes weight gain operation, in the weight gain operation, the working condition of same row are as follows:
Each wordline all connects the second positive voltage；
Each control line all connects the first negative voltage；Second positive voltage is greater than first positive voltage, second positive electricity
The size of pressure and the difference of first negative voltage meets the erasing realized to each storage position；
Each bit line all connects 0V voltage.
13. the operating method of memory as claimed in claim 12, it is characterised in that: the learning manipulation includes loss of weight behaviour
Make, in the loss of weight operation, the first working condition of same row are as follows:
The corresponding storage position of the source-drain area being connected with first bit line is to be connected by selection storage position with second bit line
The corresponding storage position of source-drain area is non-selected storage position, each described to connect third positive electricity by the corresponding control line in selection storage position
Pressure；
The corresponding control line in each unselected storage position, which connects, makes the first positive voltage；
Each wordline all connects the 4th positive voltage；
First bit line connects the 5th positive voltage；
Second bit line connects write current；
4th positive voltage, which meets, makes the channel region surface transoid of the second grid structural base form channel, described
Third positive voltage, the 5th positive voltage and said write electric current, which meet, to be realized to described by selection storage position progress source thermoelectricity
Sub- injection programming；
The learning manipulation includes loss of weight operation, in the loss of weight operation, second of working condition of same row are as follows:
The corresponding storage position of the source-drain area being connected with second bit line is to be connected by selection storage position with first bit line
The corresponding storage position of source-drain area is non-selected storage position, each described to connect third positive electricity by the corresponding control line in selection storage position
Pressure；
The corresponding control line in each unselected storage position, which connects, makes the first positive voltage；
Each wordline all connects the 4th positive voltage；
First bit line connects write current；
Second bit line connects the 5th positive voltage.
14. the operating method of memory as claimed in claim 10, it is characterised in that: in the reasoning operation of the memory
Same row the first working condition in, the output signal from the output electric current of second bit line by determining, described
The output electric current of two bit lines is the accumulated value that the input current of each wordline is added multiplied by corresponding coefficient, each institute
State the input current of wordline multiplied by coefficient determined by the programming depth of the corresponding storage position.
15. the operating method of memory as claimed in claim 11, it is characterised in that: in the reasoning operation of the memory
Same row second of working condition in, the output signal from the output electric current of first bit line by determining, described
The output electric current of one bit line is the accumulated value that the input current of each wordline is added multiplied by corresponding coefficient, each institute
State the input current of wordline multiplied by coefficient determined by the programming depth of the corresponding storage position.
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| CN113689893A (en) * | 2021-08-26 | 2021-11-23 | 北京磐芯微电子科技有限公司 | Flash memory array |
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