CN113689893A

CN113689893A - Flash memory array

Info

Publication number: CN113689893A
Application number: CN202110989487.0A
Authority: CN
Inventors: 蒋家勇; 石振东
Original assignee: Beijing Pansin Microelectronics Technology Co ltd
Current assignee: Beijing Pansin Microelectronics Technology Co ltd
Priority date: 2021-08-26
Filing date: 2021-08-26
Publication date: 2021-11-23

Abstract

The present disclosure provides a flash memory array. A flash memory array according to the present disclosure includes: a plurality of flash memory cells arranged in a row direction and a column direction perpendicular to the row direction; a plurality of word line groups extending in a row direction; and a plurality of bit line groups extending in the column direction, wherein a flash memory cell pair is provided at an intersection of the word line group and the bit line group, the flash memory cell pair including a first flash memory cell and a second flash memory cell adjacent in the row direction sharing the same bit line group. The flash memory array according to the present disclosure can improve the arrangement density of bit lines and can reduce bit line parasitic resistance without increasing the array size. Furthermore, the flash memory array according to the present disclosure also has better process compatibility and scaling characteristics than the prior art flash memory array.

Description

Flash memory array

Technical Field

The present disclosure relates to the field of semiconductor technology, and in particular, to a flash memory array.

Background

Flash memory, flash memory for short, is a non-volatile memory, i.e. the stored data will not be lost even if the power is off, especially suitable for the fields of mobile communication and computer memory parts. In addition, some flash memories also have high-density storage capability, and are suitable for applications in large-capacity mobile storage media and the like.

Conventional flash memories employ a floating gate type cell structure. The floating gate type nonvolatile memory originates from a MIMIS (Metal-Insulator-Semiconductor) structure proposed by d.kahng and s.sze in 1967. The structure is additionally provided with a Metal floating gate and an ultrathin tunneling Oxide layer on the basis of a traditional Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET), so that charges are stored by utilizing the Metal floating gate. Based on this, Masuoka et al first proposed the concept of Flash Memory in 1984, namely, to implement high speed erase capability by erasing bit-by-bit in block (sector) and to eliminate the necessary select pipes in EEPROM (Erasable Programmable Read-only Memory), thereby having a smaller Memory cell size. With the advent of flash memory, flash memory has rapidly been developed with its high writing speed, high integration, and superior performance. An ETOX flash memory cell (Electron Tunneling Oxide device) is proposed by Intel corporation in 1988, and becomes the basis of most floating gate type flash memory cell structures so far.

However, the floating gate type flash memory has the following disadvantages: the process is relatively complex; the existence of the floating gate structure in the flash memory unit increases the longitudinal height of the gate structure, which is not beneficial to reducing the process size and the unit area in proportion; meanwhile, because of the conductivity of the floating gate, the stored charges can move freely in the floating gate, which is not favorable for improving the reliability of the memory. In order to solve the problems of complex process, poor reliability and the like of the floating gate type flash Memory, researchers propose a Charge-Trapping-Memory (CTM) which stores charges by using a Silicon Nitride medium and is also called a SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) type flash Memory. Based on this, b.eitan et al proposed a two-bit Memory cell structure NROM (Nitride-Read-Only-Memory) in 2000, which utilizes the non-conductive property of the insulating silicon Nitride storage medium to implement two storage bits at the source terminal and the drain terminal of a storage transistor, but the cell structure has the disadvantages that the two storage bits interfere with each other, the device size cannot be reduced, and the like.

However, both the conventional floating gate ETOX flash memory and SONOS NROM flash memory have the problems that the process size cannot be reduced, the cell area is large, the write power consumption is large, and the array area overhead is large, and high-density integration above gigabit (Gb) capacity cannot be realized.

In addition, existing flash memory arrays require bit lines, word lines, and source lines to be provided to enable selection and operation of the flash memory cells. However, the source lines of the conventional flash memory array are formed in the active region, and the sheet resistance of the active region is much higher than that of metal. Therefore, to reduce the series resistance of the source lines, active area source lines need to be shorted together by a common source line of metal every several rows or columns in the row direction or the column direction, resulting in an increase in area overhead of the flash memory array.

With the rapid development of applications such as mobile intelligent terminals, wearable devices, and intelligent sensor networks, higher requirements are put forward on power consumption, storage capacity, and cost of flash memories, and therefore a flash memory technology with the advantages of low power consumption, small unit area, small process size, high array integration density, large capacity, and the like is required.

Disclosure of Invention

The above information disclosed in this background section is only for background understanding of the inventive concept and therefore it may contain information that does not constitute prior art.

In order to solve the above problems in the prior art, the present disclosure proposes a flash memory array.

According to an aspect of the present disclosure, there is provided a flash memory array, including: a plurality of flash memory cells arranged in a row direction and a column direction perpendicular to the row direction; a plurality of word line groups extending in a row direction; and a plurality of bit line groups extending in the column direction, wherein a flash memory cell pair is provided at an intersection of the word line group and the bit line group, the flash memory cell pair including a first flash memory cell and a second flash memory cell adjacent in the row direction sharing the same bit line group.

The flash memory array according to the present disclosure can improve the arrangement density of bit lines and can reduce bit line parasitic resistance without increasing the array size. Furthermore, the flash memory array according to the present disclosure also has better process compatibility and scaling characteristics than the prior art flash memory array.

However, the effects of the present disclosure are not limited to the above effects, and it is to be understood that various extensions may be made without departing from the spirit and scope of the present disclosure that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.

Drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the invention and together with the description serve to explain the principles of the invention.

Fig. 1 is a cross-sectional view illustrating a flash memory cell according to an embodiment of the present disclosure.

Fig. 2 shows an equivalent circuit diagram of a flash memory cell according to an embodiment of the present disclosure.

Fig. 3 shows a circuit schematic of a flash cell pair according to a first embodiment of the present disclosure.

Fig. 4 shows a circuit schematic of a flash memory array according to a first embodiment of the present disclosure.

Fig. 5 shows a schematic diagram of one layout example of a bit line group according to the first embodiment of the present disclosure.

Fig. 6 shows a schematic diagram of another layout example of a bit line group according to the first embodiment of the present disclosure.

Fig. 7 shows a circuit schematic of a flash cell pair according to a second embodiment of the present disclosure.

Fig. 8 shows a circuit schematic of a flash memory array according to a second embodiment of the present disclosure.

Fig. 9 shows a schematic diagram of one layout example of a bit line group according to a second embodiment of the present disclosure.

FIG. 10 shows a schematic diagram of a layout of control lines of a flash array according to an embodiment of the present disclosure.

Detailed Description

In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of various exemplary embodiments or implementations of the present invention. As used herein, "embodiments" and "implementations" are interchangeable words, and are non-limiting examples of apparatuses or methods that employ one or more of the inventive concepts disclosed herein. It may be evident, however, that the various exemplary embodiments may be practiced without these specific details or with one or more equivalent arrangements. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring the exemplary embodiments. Moreover, the exemplary embodiments may be different, but not necessarily exclusive. For example, the particular shapes, configurations and characteristics of the exemplary embodiments may be used or implemented in other exemplary embodiments without departing from the inventive concept.

Unless otherwise indicated, the illustrated exemplary embodiments should be understood as providing exemplary features of varying detail of some ways in which the inventive concepts may be practiced. Thus, unless otherwise specified, features, components, modules, layers, films, panels, regions, and/or aspects and the like (hereinafter referred to individually or collectively as "elements") of the various embodiments may be otherwise combined, separated, interchanged, and/or rearranged without departing from the spirit of the invention.

The use of cross-hatching and/or shading in the figures is typically provided for clarifying the boundaries between adjacent elements. As such, the presence or absence of cross-hatching or shading is not intended to convey or indicate any preference or requirement for particular materials, material properties, dimensions, proportions, commonality between the illustrated elements, and/or any other characteristic, attribute, shape, etc., of an element, unless otherwise specified. Further, in the drawings, the size and relative sizes of elements may be exaggerated for clarity and/or descriptive purposes. When the exemplary embodiments may be implemented differently, a specific order of processing may be performed differently from that described. For example, two processes described in succession may be executed substantially concurrently or in reverse order to that described. Also, like reference numerals refer to like elements.

When an element such as a layer is referred to as being "on," "connected to" or "coupled to" another element or layer, it can be directly on, connected or coupled to the other element or layer or intervening elements or layers may be present. However, when an element or layer is referred to as being "directly on," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. For purposes of this specification, the term "connected" may refer to physical, electrical, and/or fluid connections, with or without intervening elements. Further, the D1, D2, and D3 axes are not limited to three axes of a rectangular coordinate system, such as the x, y, and z axes, and may be interpreted in a broader sense. For example, the D1 axis, the D2 axis, and the D3 axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For purposes of this disclosure, "at least one of X, Y and Z" and "at least one selected from the group consisting of X, Y, and Z" may be construed as X only, Y only, Z only, or any combination of two or more of X, Y and Z, such as, for example, XYZ, XYY, YZ, and ZZ. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

Although the terms first, second, etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, a first element discussed below could be termed a second element without departing from the teachings of the present disclosure.

Spatial relational terms, such as "under," "below," "under," "lower," "over," "upper," "higher," and "side" (e.g., as in a "sidewall") and the like may be used herein for descriptive purposes to describe the relationship of one element to another element as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use, operation, and/or manufacture in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. Furthermore, the apparatus may be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, components, and/or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. It should also be noted that, as used herein, the terms "substantially," "about," and other similar terms are used as approximate terms rather than degree terms, and thus are utilized to account for inherent deviations in the measured, calculated, and/or provided values as recognized by those of ordinary skill in the art.

Some example embodiments are described and illustrated in the accompanying drawings in terms of functional blocks, units and/or modules, as is conventional in the art. Those skilled in the art will appreciate that the blocks, units and/or modules are physically implemented by electronic (or optical) circuitry, such as logic circuitry, discrete components, microprocessors, hardwired circuitry, memory elements, wired connections, and so forth, which may be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. Where the blocks, units, and/or modules are implemented by a microprocessor or other similar hardware, they may be written and controlled using software (e.g., microcode) to perform the various functions discussed herein, and may optionally be driven by firmware and/or software. It is also contemplated that each block, unit, and/or module may be implemented by dedicated hardware, or as a combination of dedicated hardware for performing some functions and a processor (e.g., one or more programmed microprocessors and associated circuitry) for performing other operations. Furthermore, each block, unit and/or module of some example embodiments may be physically separated into two or more interactive and discrete blocks, units and/or modules without departing from the scope of the present inventive concept. Furthermore, the blocks, units and/or modules of some example embodiments may be physically combined into more complex blocks, units and/or modules without departing from the scope of the inventive concept.

Embodiments are described herein with reference to cross-sectional and/or exploded views, which are schematic illustrations of idealized embodiments and/or intermediate structures. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments disclosed herein are not necessarily to be construed as limited to the particular illustrated shapes of regions but are to include deviations in shapes that result, for example, from manufacturing. In this manner, the regions illustrated in the figures may be schematic in nature and the shapes of these regions may not reflect the actual shape of a region of a device, and thus this is not necessarily intended to be limiting.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. Terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Fig. 1 illustrates a cross-sectional view of a flash memory cell MC100 according to an embodiment of the present disclosure.

As shown in fig. 1, a flash memory cell MC100 according to an embodiment of the present disclosure may include a substrate 101 including a deep well region DNW103 of a second doping type and a well region PW 102 of a first doping type disposed on the deep well region DNW 103.

Although the first doping type is defined as P-type and the second doping type is defined as N-type in fig. 1 as an example, one skilled in the art will recognize that the present disclosure is not limited thereto and the first doping type may also be N-type, in which case the second doping type may be P-type.

According to an embodiment of the present disclosure, the substrate 101 may be, for example, a silicon (Si) substrate.

Further, the flash memory cell MC100 includes a first memory transistor MS110, a gate transistor MG120, and a second memory transistor MD 130 connected in series in this order. The first memory transistor MS110 may be disposed on the well region PW 102 and stores the first DATA 1. The second memory transistor MD 130 may be disposed on the well region PW 102 and stores second DATA 2. The gate transistor MG120 is disposed between the first and second memory transistors MS110 and MD 130 in the horizontal direction DR1 on the well region PW 102, for isolating the first and second memory transistors MS110 and MD 130 and performing a gate operation on the first and second memory transistors MS110 and MD 130.

According to an embodiment of the present disclosure, the flash memory cell MC100 includes two memory transistors MS110 and MD 130, and thus the flash memory cell MC100 can implement a function of two-bit storage, i.e., storing the first DATA1 and the second DATA2 at the same time.

Further, as shown in fig. 1, the source region of first memory transistor MS110 is connected to first electrode S of flash memory cell MC100, which may also be referred to as source S of flash memory cell MC100, and the drain region of second memory transistor MD 130 is connected to second electrode D of flash memory cell MC100, which may also be referred to as drain D of flash memory cell MC 100.

Those skilled in the art will recognize that the source and drain of a flash memory cell are defined herein for ease of description, however the definition of source and drain of a flash memory cell is relative and the terms "source" and "drain" may be used interchangeably under different operating conditions.

Further, as shown in fig. 1, the first memory transistor MS110 has a gate structure including a channel region 111, a gate dielectric stack 112, a gate electrode 116, and a hard mask barrier 117 sequentially disposed in a vertical direction DR 2. The gate dielectric stack 112 has a first oxide layer 113, a storage dielectric layer 114, and a second oxide layer 115 sequentially stacked in a vertical direction. In addition, the second memory transistor MD 130 has a gate structure including a channel region 131, a gate dielectric stack 132, a gate electrode 136, and a hard mask barrier 137 sequentially disposed in the vertical direction DR 2. The gate dielectric stack 132 has a first oxide layer 133, a storage dielectric layer 134, and a second oxide layer 135 sequentially stacked in a vertical direction.

According to the embodiment of the present disclosure, the flash memory cell MC100 includes two memory transistors MS110 and MD 130, and thus a function of two-bit storage can be implemented.

According to an embodiment of the present disclosure, as shown in fig. 1, a flash memory cell MC100 for two-bit storage may be composed of three closely arranged transistors, namely, a gate transistor MG120 located in the middle of the flash memory cell MC100, a first memory transistor MS110 located at a first end of the flash memory cell MC100, and a second memory transistor MD 130 located at a second end of the flash memory cell MC 100.

As shown in fig. 1, flash memory cell MC100 may be formed over well region PW 102 in semiconductor substrate 101. Furthermore, to isolate well region PW 102 from substrate 101 for applying voltages to well region PW 102 under certain operating conditions, well region PW 102 may be formed in deep well region DNW103 as shown in fig. 1.

As shown in fig. 1, a source region 140 formed by N-type doping is disposed at a first end of the flash memory cell MC100, and a drain region 150 formed by N-type doping is also disposed at a second end of the flash memory cell MC 100. The source region 140 is connected to the metal source 142, i.e., the first electrode S, located at an upper layer through the contact hole 141, and the drain region 150 is connected to the metal drain 152, i.e., the second electrode D, located at an upper layer through the contact hole 151.

According to an embodiment of the present disclosure, the first and second electrodes S and D may include a metal or highly doped polysilicon. When the first electrode S and the second electrode D are formed of a metal, it may include at least one of the following materials: aluminum, titanium nitride, copper, tungsten, cobalt, and manganese.

As described above, the gate structure of the first memory transistor MS110 may have, in order from bottom to top, the channel region 111, the gate dielectric stack 112, the gate electrode 116, and the hard mask barrier 117 for sidewall self-alignment, as shown in fig. 1. According to embodiments of the present disclosure, the gate electrode 116 may comprise, for example, polysilicon, a metal gate, a metal silicide material, or a combination thereof. According to an embodiment of the present disclosure, the hard mask barrier 117 may include, for example, silicon oxide, silicon nitride, a silicon glass material, or a combination thereof.

Further, as shown in fig. 1, the gate dielectric stack 112 has a first oxide layer (tunnel oxide layer) 113, a storage dielectric layer (charge storage layer) 114, and a second oxide layer (blocking oxide layer) 115, which are sequentially stacked in a vertical direction. According to an embodiment of the present disclosure, the first oxide layer 113 and the second oxide layer 115 may include, for example, silicon oxide or aluminum oxide, etc.

According to embodiments of the present disclosure, the storage medium layer 114 may include one or more layers of storage media. In addition, according to an embodiment of the present disclosure, the storage medium forming the storage medium layer 114 may include: mono-or multi-component oxides such as hafnium oxide, tantalum oxide, titanium oxide, zirconium oxide, hafnium aluminum oxide; mono-or poly-nitrides such as silicon nitride; mono-or poly-oxynitrides such as silicon oxynitride; polycrystalline silicon or nanocrystalline materials; or a combination of the above materials.

According to an embodiment of the present disclosure, when the storage dielectric layer 114 is formed of, for example, a silicon nitride material, the first oxide layer 113, the storage dielectric layer 114, and the second oxide layer 115 may form the gate dielectric stack 112 as an ONO (oxide-nitride-oxide) composite storage dielectric. At this time, the first memory transistor MS110 may be a SONOS type memory transistor.

Further, according to an embodiment of the present disclosure, the first memory transistor MS110 may be another trap charge trapping type memory transistor having a similar operation mechanism as the SONOS type memory transistor, which employs a high-K material rich in charge traps, such as silicon oxynitride, hafnium oxide, tantalum oxide, titanium oxide, zirconium oxide, hafnium aluminum oxide, etc., instead of the silicon nitride material in the SONOS memory as the memory dielectric layer 114.

In addition, according to an embodiment of the present disclosure, the first memory transistor MS110 may also be a floating gate type memory transistor, which uses a polysilicon material instead of a silicon nitride material in a SONOS memory to form a floating gate for storing charges as the storage medium layer 114.

In addition, according to the embodiment of the present disclosure, the first memory transistor MS110 may also be a nano-crystal memory transistor (nano-crystal memory), which uses a nano-crystal material with quantum dots (quantum dots) instead of a silicon nitride material in a SONOS memory as the memory medium layer 114.

According to an embodiment of the present disclosure, the length of the gate electrode 116 of the first memory transistor MS110 may be defined by the length of the hard mask barrier 117 disposed on the gate electrode 116 through a self-aligned process. It should be noted by those skilled in the art that reference herein to "length" is intended to refer to the dimension of the stated object in the horizontal direction DR 1.

According to the embodiment of the present disclosure, the second memory transistor MD 130 has the same structure as the first memory transistor MS110 except disposed at the opposite side of the gate transistor MG120 and may be manufactured through the same process as the first memory transistor MS110, and thus a detailed description of the structure of the second memory transistor MD 130 will be omitted herein for the sake of brevity.

The gate structure of the gating transistor MG120 may include a channel region 121, a gate dielectric layer 122, and a gate electrode 123 in this order from bottom to top. According to the embodiment of the present disclosure, the gate electrode 123 of the gate transistor MG120 is connected to a word line, and the length of the gate electrode 123 thereof is defined by the process size of the photolithography process. According to an embodiment of the present disclosure, the gate dielectric layer 122 may include materials such as silicon oxide, silicon oxynitride, hafnium oxide, and the like. Further, according to an embodiment of the present disclosure, the gate electrode 123 may include, for example, polysilicon, a metal gate, a metal silicide material, or a combination thereof.

According to an embodiment of the present disclosure, the

channel regions

111, 131, and 121 of the first memory transistor MS110, the second memory transistor MD 130, and the gate transistor MG120 may each have a first doping type, and the doping concentration of the

channel regions

111 and 131 of the first memory transistor MS110 and the second memory transistor MD 130 may be lower than the doping concentration of the channel region 121 of the gate transistor MG 120.

Further, according to an embodiment of the present disclosure, the

channel regions

111 and 131 of the first and second memory transistors MS110 and MD 130 may have a second doping type or be an undoped intrinsic channel region, and the channel region 121 of the gate transistor MG120 may have a first doping type different from the second doping type.

For example, as shown in fig. 1, in the case where the first doping type is a P-type and the second doping type is an N-type, the doping concentration of the P-

type channels

111 and 131 of the first and second memory transistors MS110 and MD 130 is lower than that of the P-type channel 121 of the gate transistor MG 120. Furthermore, according to an embodiment of the present disclosure, the

channel regions

111 and 131 may also be undoped intrinsic channels or N-type doped channel regions.

According to an embodiment of the present disclosure, the flash memory cell MC100 further includes: a first isolation portion 124 provided between the first memory transistor MS110 and the gate transistor MG120 in the horizontal direction DR1 for isolating the gate electrode 116 of the first memory transistor MS110 and the gate electrode 123 of the gate transistor MG 120; and a second isolation portion 125 disposed between the gate transistor MG120 and the second memory transistor MD 130 in the horizontal direction DR1 for isolating the gate electrode 123 of the gate transistor MG120 and the gate electrode 136 of the second memory transistor MD 130.

Specifically, as shown in fig. 1, the gate electrode 123 of the gate transistor MG120 is provided at both sides with a first isolation portion 124 and a second isolation portion 125 in the form of sidewalls for electrically isolating from the gate electrode 116 of the first memory transistor MS110 and the gate electrode 136 of the second memory transistor MD 130, respectively, by a certain isolation gap length. According to an embodiment of the present disclosure, the first isolation portion 124 and the second isolation portion 125 may include the same material as the gate dielectric layer 122.

According to the flash memory unit disclosed by the embodiment of the disclosure, two storage transistors can be realized in one flash memory unit, so that the equivalent area of each storage bit can be greatly reduced, and further lower cost and higher integration density can be obtained.

In addition, the memory transistor in the flash memory cell according to the embodiment of the present disclosure may adopt a SONOS-type device structure with a simple structure, and has advantages of a simple process, a low gate electrode operating voltage, and good data retention reliability.

In addition, in the flash memory unit according to the embodiment of the disclosure, the mutual influence of two storage bits is isolated through the gating transistor, and the distribution width and the lateral diffusion of the storage charges are suppressed, so that a higher storage charge density can be obtained in the silicon nitride storage layer, the problems of wide charge distribution, large mutual interference, incapability of reducing the gate length and the like of the existing NROM storage unit which also adopts two-bit storage are avoided, and the storage window and the data reliability are remarkably improved.

In particular, the equivalent channel length of the flash memory cell according to the embodiment of the present disclosure is the sum of the lengths of the gate electrodes of the first storage transistor, the gate transistor, and the second storage transistor. As described above, the gate electrode length of the gate transistor is defined by the process Feature Size of the photolithography process, typically about equal to or slightly larger than the Critical Feature Size (Critical Feature Size), which is typically denoted as F (or CF). In addition, the gate electrode lengths of the first and second memory transistors are defined by the lengths of the self-aligned sidewall hard mask barriers, respectively, and thus may be smaller than F in size. Therefore, according to the embodiments of the present disclosure, a smaller channel length of the flash memory cell can be obtained under the same process feature size, thereby achieving the purpose of reducing the area and manufacturing cost of the flash memory cell.

In addition, in the flash memory array composed of the flash memory cells according to the embodiments of the present disclosure, for the flash memory cells that are not selected for operation, the gate electrodes of the gating transistor and the first and second storage transistors are grounded, so that the entire series channel of the flash memory cells is completely turned off, and the equivalent channel length is extended, thereby preventing the source-drain punch-through of the flash memory cells under the condition of high operating voltage under a smaller process feature size, and overcoming the problem that the gate electrode length of the existing flash memory cells cannot be reduced along with the reduction of the process feature size. Therefore, the flash memory cell according to the embodiment of the present disclosure has better process scaling capability, and thus can achieve smaller cell area and manufacturing cost by reducing the process feature size.

In addition, in the flash memory cell according to the embodiment of the present disclosure, by reducing the doping concentration of the P-type channel region of the first memory transistor and the second memory transistor or designing them as the N-type doped channel region, the threshold voltage of the memory transistor and the gate electrode operating voltage in the erasing and reading operations can be reduced, and thus the reliability of the memory transistor can be improved. Meanwhile, the punch-through resistant voltage of the flash memory unit can be improved by improving the doping concentration of the P-type channel region of the gating transistor, and the leakage current between the source region and the drain region of the non-selected flash memory unit is reduced.

Fig. 2 illustrates an equivalent circuit diagram of the flash memory cell MC100 according to an embodiment of the present disclosure.

Specifically, as shown in fig. 2, the flash memory cell MC100 includes a first memory transistor MS110, a gate transistor MG120, and a second memory transistor MD 130 connected in series in this order. The gating transistor MG120 may isolate the first and second memory transistors MS110 and MD 130 and perform a gating operation on the first and second memory transistors MS110 and MD 130.

Fig. 3 shows a circuit schematic of a flash cell pair 200 according to a first embodiment of the present disclosure. Fig. 4 shows a circuit schematic of a flash memory array according to a first embodiment of the present disclosure.

According to an embodiment of the present disclosure, a flash memory array may include: a plurality of flash memory cells arranged in a row direction and a column direction perpendicular to the row direction; a plurality of word line groups extending in a row direction; and a plurality of bit line groups extending in the column direction, wherein a flash memory cell pair is provided at an intersection of the word line group and the bit line group, the flash memory cell pair including a first flash memory cell and a second flash memory cell adjacent in the row direction sharing the same bit line group.

As shown in fig. 3 and 4, according to an embodiment of the present disclosure, a flash memory array may include a plurality of flash memory cells as shown in fig. 2, which may be arranged in an array of m × 2n in a row direction and a column direction perpendicular to the row direction, where m and n are natural numbers greater than 1. Thus, a plurality of flash memory cells form a flash memory array of m rows by 2n columns.

As shown in fig. 3, two flash memory cells adjacent in the row direction may constitute one flash memory cell pair 200 including a first flash memory cell 210 and a second flash memory cell 220 according to an embodiment of the present disclosure. For example, the first flash cell 210 may be a flash cell located in row 0, column 0 of the flash array, and the second flash cell 220 may be a flash cell located in row 0, column 1 of the flash array. Thus, according to embodiments of the present disclosure, a flash memory array may include pairs of flash memory cells arranged in m rows by n columns.

The first flash memory cell 210 includes a first storage transistor 211, a gating transistor 212, and a second storage transistor 213 sequentially connected in series in a column direction. The second flash memory cell 220 includes a first storage transistor 221, a gating transistor 222, and a second storage transistor 223 sequentially connected in series in a column direction.

According to an embodiment of the present disclosure, in the first flash memory cell 210, the source region of the first memory transistor 211 is connected to the first electrode S1 of the first flash memory cell 210, and the drain region of the second memory transistor 213 is connected to the second electrode D1 of the first flash memory cell 210.

Further, according to an embodiment of the present disclosure, in the second flash memory cell 220, the source region of the first memory transistor 221 is connected to the first electrode S2 of the second flash memory cell 220, and the drain region of the second memory transistor 223 is connected to the second electrode D2 of the second flash memory cell 220.

Further, according to an embodiment of the present disclosure, the pair of flash memory cells 200, i.e., the pair of the first and second

flash memory cells

210 and 220, share a bit line group extending in a column direction, the bit line group including the first bit line BSL0, the middle bit line BLM0, and the second bit line BLD 0. According to the first embodiment of the present disclosure, the first bit line BSL0 may be connected to the first electrode S1 of the first flash memory cell 210, the second bit line BLD0 may be connected to the second electrode D2 of the second flash memory cell 220, and the middle bit line BLM0 may connect the second electrode D1 of the first flash memory cell 210 and the first electrode S2 of the second flash memory cell 220.

As described above, according to the embodiment of the present disclosure, the first and second

flash memory cells

210 and 220 adjacent in the row direction are connected to the same first bit line BSL0, middle bit line BLM0, and second bit line BLD 0. That is, according to embodiments of the present disclosure, pairs of flash memory cells share the same set of bit lines in a flash memory array. For example, column 0 and column 1 flash memory cells share a group of bit lines including first bit line BLS0, middle bit line BLM0, and second bit line BLD0, and column 2 and column 3 flash memory cells share a group of bit lines including first bit line BLS1, middle bit line BLM1, and second bit line BLD1, up to column 2n-2 and column 2n-1 flash memory cells share a group of bit lines including first bit line BLS < n-1>, middle bit line BLM < n-1>, and second bit line BLD < n-1 >.

Further, according to an embodiment of the present disclosure, the flash memory array further includes a plurality of word line groups extending in the row direction, each of the word line groups including a first control line, a word line, and a second control line, wherein the first control line is connected to the gate electrode of the first memory transistor of the flash memory cell pair, the word line is connected to the gate electrode of the gating transistor of the flash memory cell pair, and the second control line is connected to the gate electrode of the second memory transistor of the flash memory cell pair.

According to an embodiment of the present disclosure, in a flash memory array, flash memory cells (pairs) of the same row share the same word line group, i.e., a first control line, a word line, and a second control line.

As shown in fig. 3 and 4, taking the flash memory cell pair 200 as an example, the flash memory cell pair 200, i.e., the first flash memory cell 210 and the second flash memory cell 220, is located in the 0 th row and shares the same word line group, i.e., the first control line MS0, the word line WL0, and the second control line MD0, with other flash memory cells (pairs) in the 0 th row. The first control line MS0 is connected to the gate electrodes of the

first memory transistors

211 and 221 of the first and second

flash memory cells

210 and 220, the word line WL0 is connected to the gate electrodes of the

gate transistors

212 and 222 of the first and second

flash memory cells

210 and 220, and the second control line MD0 is connected to the gate electrodes of the

second memory transistors

213 and 223 of the first and second

flash memory cells

210 and 220.

Similarly, the gate electrodes of the first memory transistors in the flash memory cell (pair) of the 1 st row are commonly connected to the first control line MS1, the gate electrodes of the gate transistors in the flash memory cells of the 1 st row are commonly connected to the word line WL1, and the gate electrodes of the second memory transistors in the flash memory cells of the 1 st row are commonly connected to the second control line MD 1. Similarly, the gate electrodes of the first memory transistors in the flash memory cells of the m-2 th row are commonly connected to a first control line MS < m-2>, the gate electrodes of the gate transistors in the flash memory cells of the m-2 th row are commonly connected to a word line WL < m-2>, and the gate electrodes of the second memory transistors in the flash memory cells of the m-2 th row are commonly connected to a second control line MD < m-2 >. Similarly, the gate electrodes of the first memory transistors in the flash memory cells of the m-1 th row are commonly connected to a first control line MS < m-1>, the gate electrodes of the gate transistors in the flash memory cells of the m-1 th row are commonly connected to a word line WL < m-1>, and the gate electrodes of the second memory transistors in the flash memory cells of the m-1 th row are commonly connected to a second control line MD < m-1 >.

Those skilled in the art will recognize that the flash memory cells according to the embodiments of the present disclosure have a symmetrical structure, and thus the flash memory cells adjacent in the column direction are oppositely disposed based on the connection relationship of the first control line, the word line, the second control line, the first bit line, the middle bit line, and the second bit line as described above, i.e., the first memory transistor of the flash memory cell of the current row is adjacent to the first memory transistor of the flash memory cell of the previous row in the column direction, and the second memory transistor of the flash memory cell of the current row is adjacent to the second memory transistor of the flash memory cell of the next row in the column direction; or, the second storage transistor of the flash memory cell of the current row is adjacent to the second storage transistor of the flash memory cell of the previous row in the column direction, and the first storage transistor of the flash memory cell of the current row is adjacent to the first storage transistor of the flash memory cell of the next row in the column direction.

According to an embodiment of the present disclosure, the first control line, the word line, and the second control line may be formed of at least one of polysilicon, silicide, and a metal gate. Further, according to an embodiment of the present disclosure, the intermediate bit line may be formed of a first metal layer, and the first bit line and the second bit line may be formed of a second metal layer different from the first metal layer. In other words, the metal layer used to form the intermediate bit lines is different from the metal layer used to form the first and second bit lines. In addition, the first bit line and the second bit line may be formed of the same metal layer.

According to an embodiment of the present disclosure, the first metal layer and the second metal layer may include at least one of the following materials: aluminum, titanium nitride, copper, tungsten, cobalt, and manganese.

According to an embodiment of the present disclosure, the intermediate bit line may include a first portion extending in a column direction and a second portion extending in a row direction, and the first bit line and the second bit line extend in the column direction.

As shown in (a) of fig. 5, taking the flash cell pair 200 as an example, the first electrodes S1 and S2 and the second electrodes D1 and D2 of the first and

second flash cells

210 and 220 may be formed of a first metal layer M1 disposed over a first control line MS0, a word line WL0, and a second control line MD0, e.g., polysilicon. As shown in fig. 5, the first control line MS0, the word line WL0, and the second control line MD0 extend parallel to each other in the row direction.

Further, as shown in (a) of fig. 5, the middle bit line BLM0 is formed of the first metal layer M1 in a continuous zigzag manner in the column direction, which includes a first portion P1 extending in the column direction and a second portion P2 extending in the row direction. According to an embodiment of the present disclosure, the second portion P2 of the middle bit line BLM0 may overlap with the word line WL0 therebelow.

Further, as shown in (b) of fig. 5, the first bit line BLS0 and the second bit line BLD0 may be formed of the second metal layer M2 in the column direction, and overlap the first portion P1 of the middle bit line BLM 0.

According to an embodiment of the present disclosure, the electrical connection between the first bit line BLS0 and the first electrode S1 of the first flash cell 210 may be achieved through a via V1 between the first metal layer M1 and the second metal layer M2, and the electrical connection between the second bit line BLD0 and the second electrode D2 of the second flash cell 220 may be achieved through a via V1 between the first metal layer M1 and the second metal layer M2.

According to the embodiments of the present disclosure, since the first portion of the middle bit line P1 may overlap the first bit line and the second portion of the middle bit line P2 may overlap the word line of polysilicon in the row direction, an additional area for disposing the middle bit line may be eliminated, thereby obtaining a more compact flash memory array. In addition, since the first bit line and the second bit line are both formed of metal, the need for providing a common source line in the prior art is eliminated, thereby further reducing the area of the flash memory array.

The embodiment shown in fig. 5 uses two metal layers to implement the arrangement of the first bit line, the middle bit line and the second bit line. However, the present disclosure is not limited thereto. According to the embodiment of the present disclosure, the arrangement of the first bit line, the middle bit line and the second bit line may be implemented using more metal layers according to an application scenario of the flash memory array.

Specifically, as shown in (a) of fig. 6, the first and second electrodes of the flash memory cell may be formed of a first metal layer M1 disposed over the first control line, the word line, and the second control line, e.g., polysilicon. Unlike fig. 5, the intermediate bit lines may be formed by the third metal layer M3 in a continuous zigzag manner in the column direction, as shown in (c) of fig. 6. That is, the intermediate bit line includes a first portion P1 extending in the column direction and a second portion P2 extending in the row direction.

Further, as shown in (d) of fig. 6, the first and second bit lines are formed in the column direction by the fourth metal layer M4, and overlap with the first portion P1 of the middle bit line in the column direction. As shown in (b) of fig. 6, the electrical connection of the middle bit line to the first and second electrodes may be achieved through the second metal layer M2 between the first metal layer M1 and the third metal layer M3 and the vias V1 and V2 between the respective metal layers M1 to M3. Further, as shown in (b) and (c) of fig. 6, the electrical connection between the first bit line and the first electrode may be achieved through the second and third metal layers M2 and M3 between the first and fourth metal layers M1 and M4 and the vias V1 to V3 between the respective metal layers M1 to M4. Further, as shown in (b) and (c) of fig. 6, the electrical connection between the second bit line and the second electrode may also be achieved through the second metal layer M2 and the third metal layer M3 between the first metal layer M1 and the fourth metal layer M4 and the vias V1 to V3 between the respective metal layers M1 to M4.

The four-level metal bit line layout shown in FIG. 6 may enable greater flexibility in the layout of the first bit line, the middle bit line, and the second bit line than the two-level metal bit line layout shown in FIG. 5.

Furthermore, those skilled in the art will recognize that the bit line arrangement of the flash memory array according to the present disclosure requires at least two metal layers, and thus although fig. 6 illustrates an embodiment in which the bit line arrangement of the flash memory array according to the present disclosure is implemented using four metal layers, the present disclosure is not limited thereto. A bit line arrangement for a flash memory array according to the present disclosure may be implemented using three metal layers or five or more metal layers by one of ordinary skill in the art in light of the teachings of the present disclosure.

Fig. 7 shows a circuit schematic of a flash cell pair 300 according to a second embodiment of the present disclosure. Fig. 8 shows a circuit schematic of a flash memory array according to a second embodiment of the present disclosure.

As shown in fig. 7, two flash memory cells adjacent in the row direction may constitute one flash memory cell pair 300 including a first flash memory cell 310 and a second flash memory cell 320 according to an embodiment of the present disclosure. For example, the first flash cell 310 may be a flash cell located in row 0, column 0 of the flash array, and the second flash cell 320 may be a flash cell located in row 0, column 1 of the flash array. Thus, according to embodiments of the present disclosure, a flash memory array may include pairs of flash memory cells arranged in m rows by n columns.

The first flash memory cell 310 includes a first storage transistor 311, a gate transistor 312, and a second storage transistor 313 connected in series in sequence in a column direction. The second flash memory cell 320 includes a first storage transistor 321, a gating transistor 322, and a second storage transistor 323 connected in series in sequence in a column direction.

According to an embodiment of the present disclosure, in the first flash memory cell 310, a source region of the first memory transistor 311 is connected to the first electrode S1 of the first flash memory cell 310, and a drain region of the second memory transistor 313 is connected to the second electrode D1 of the first flash memory cell 310.

In addition, according to an embodiment of the present disclosure, in the second flash memory cell 320, the source region of the first memory transistor 321 is connected to the first electrode S2 of the second flash memory cell 320, and the drain region of the second memory transistor 323 is connected to the second electrode D2 of the second flash memory cell 320.

The flash memory cell pair and the flash memory array of the second embodiment of the present disclosure shown in fig. 7 and 8 are substantially the same as the flash memory cell pair and the flash memory array of the first embodiment of the present disclosure of fig. 3 and 4, except for the connection manner of the bit line groups of the flash memory cell pair.

Specifically, as shown in fig. 7 and 8, according to the second embodiment of the present disclosure, the first bit line BSL0 may be connected to the second electrode D1 of the first flash memory cell 310, the second bit line BLD0 may be connected to the second electrode D2 of the second flash memory cell 320, and the middle bit line BLM0 may connect the first electrode S1 of the first flash memory cell 310 and the first electrode S2 of the second flash memory cell 320.

Specifically, as shown in (a) of fig. 9, the first and second electrodes of the flash memory cell may be formed of a first metal layer M1 disposed over the first control line, the word line, and the second control line, e.g., polysilicon. As shown in (c) of fig. 9, the intermediate bit lines may be formed by the third metal layer M3 in a continuous zigzag manner in the column direction. That is, the intermediate bit line includes a first portion P1 extending in the column direction and a second portion P2 extending in the row direction.

Further, as shown in (d) of fig. 9, the first and second bit lines are formed in the column direction by the fourth metal layer M4, and overlap with the first portion P1 of the middle bit line in the column direction. As shown in (b) of fig. 9, the electrical connection of the middle bit line to the first electrode may be achieved through the second metal layer M2 between the first metal layer M1 and the third metal layer M3 and the vias V1 and V2 between the respective metal layers M1 to M3. Further, as shown in (b) and (c) of fig. 9, the electrical connection between the first bit line and the second electrode may be achieved through the second metal layer M2 and the third metal layer M3 between the first metal layer M1 and the fourth metal layer M4 and the vias V1 to V3 between the respective metal layers M1 to M4. Further, as shown in (b) and (c) of fig. 9, the electrical connection between the second bit line and the second electrode may also be achieved through the second metal layer M2 and the third metal layer M3 between the first metal layer M1 and the fourth metal layer M4 and the vias V1 to V3 between the respective metal layers M1 to M4.

The flash memory array according to the above embodiment of the present disclosure may improve the arrangement density of the bit lines and may reduce the bit line parasitic resistance without increasing the array size. Furthermore, the flash memory array according to the present disclosure also has better process compatibility and scaling characteristics than the prior art flash memory array.

Further, according to the embodiment of the present disclosure, the first control line or the second control line adjacent in the column direction may be connected together through a metal layer. FIG. 10 shows a schematic diagram of a layout of control lines of a flash array according to an embodiment of the present disclosure.

As shown in fig. 10, for example, on the basis of the flash memory array shown in fig. 4, adjacent first control lines can be connected together in the column direction using first metal control lines MCS <0: m/2-1> formed by metal layers. Further, second control lines adjacent in the column direction may also be connected together using second metal control lines MCD <1: m/2> formed through the metal layer.

According to an embodiment of the present disclosure, the metal layers for forming the first metal control line MCS <0: m/2-1> and the second metal control line MCD <1: m/2> may be different from the metal layers for forming the bit lines (including the first bit line, the middle bit line, and the second bit line). According to an embodiment of the present disclosure, a metal layer for forming the first metal control line MCS <0: m/2-1> and the second metal control line MCD <1: m/2> may be disposed over a metal layer for forming the bit line (including the first bit line, the middle bit line, and the second bit line).

According to an embodiment of the present disclosure, two flash memory cells adjacent in a column direction may share a control line (a first control line or a second control line) through a metal control line (a first metal control line or a second metal control line). By connecting the first control line and the second control line together by using the first metal control line and the second metal control line, parasitic resistance of the first control line and the second control line such as polysilicon can be effectively reduced, thereby effectively improving the operation speed of the flash memory array. In addition, the first control line and the second control line are connected together using the first metal control line and the second metal control line, and the wiring density and the process complexity of the metal control lines can be reduced. In addition, the flash memory array sharing the control lines can reduce the number of peripheral circuits of the flash memory array for driving the control lines, thereby reducing the area overhead of the peripheral circuits and the manufacturing cost of the memory chip.

Those skilled in the art will recognize that although the flash memory array of the present disclosure is described above in connection with the flash memory cell MC100 shown in fig. 1, the flash memory array of the present disclosure is not limited to the flash memory cell MC100 shown in fig. 1. Those skilled in the art with access to the teachings of the present disclosure may conceive of applying the flash memory array of the present disclosure to other types of flash memory cells, such as flash memory cells including only one memory transistor or flash memory cells storing two bits of data using one memory transistor, and all such variations are intended to be within the scope of the present disclosure.

Although the present disclosure has been described with reference to the embodiments thereof, those skilled in the art will appreciate that various modifications and changes can be made to the present disclosure without departing from the spirit and scope of the present disclosure disclosed in the appended claims.

Claims

1. A flash memory array, comprising:

a plurality of flash memory cells arranged in a row direction and a column direction perpendicular to the row direction;

a plurality of word line groups extending in the row direction; and

a plurality of bit line groups extending in the column direction,

wherein a flash memory cell pair is provided at an intersection of the word line group and the bit line group, the flash memory cell pair including a first flash memory cell and a second flash memory cell sharing the same bit line group that are adjacent in the row direction.

2. The flash memory array of claim 1,

wherein each of the first flash memory cell and the second flash memory cell includes a first storage transistor, a gating transistor, and a second storage transistor sequentially connected in series in the column direction, an

Wherein in each of the first and second flash memory cells, a source region of the first memory transistor is connected to a first electrode of the flash memory cell, and a drain region of the second memory transistor is connected to a second electrode of the flash memory cell.

3. The flash memory array of claim 2,

wherein each bit line group comprises a first bit line connected to a first electrode of a first flash cell of the flash cell pair, an intermediate bit line connected to a second electrode of a second flash cell of the flash cell pair, and a second bit line connecting the second electrode of the first flash cell and the first electrode of the second flash cell.

4. The flash memory array of claim 2,

wherein each bit line group comprises a first bit line connected to the second electrode of a first flash cell of the flash cell pair, an intermediate bit line connected to the first electrode of the first flash cell and the first electrode of the second flash cell of the flash cell pair, and a second bit line.

5. The flash memory array of claim 3 or 4,

wherein each word line group includes a first control line, a word line, and a second control line extending in the row direction, the first control line being connected to the gate electrode of the first memory transistor, the word line being connected to the gate electrode of the gate transistor, and the second control line being connected to the gate electrode of the second memory transistor.

6. The flash memory array of claim 5,

two first control lines adjacent in the column direction are connected together by a first common control line, an

Wherein two second control lines adjacent in the column direction are connected together by a second common control line.

7. The flash memory array of claim 5,

the first control line, the word line and the second control line are formed of at least one of polysilicon, silicide and metal gate.

8. The flash memory array of claim 6,

the first common control line and the second common control line are formed of a metal layer.

9. The flash memory array of claim 3 or 4,

the intermediate bit line is formed from a first metal layer, an

The first bit line and the second bit line are formed of a second metal layer different from the first metal layer.

10. The flash memory array of claim 9,

the intermediate bit line includes a first portion extending in the column direction and a second portion extending in the row direction, an

The first bit line and the second bit line extend in the column direction.