CN110120380A - 半导体封装 - Google Patents

半导体封装 Download PDF

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Publication number
CN110120380A
CN110120380A CN201810281728.4A CN201810281728A CN110120380A CN 110120380 A CN110120380 A CN 110120380A CN 201810281728 A CN201810281728 A CN 201810281728A CN 110120380 A CN110120380 A CN 110120380A
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CN
China
Prior art keywords
conductive
conductive layer
cap
hardness
layer
Prior art date
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Pending
Application number
CN201810281728.4A
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English (en)
Inventor
邱咏达
王秀枝
黄上坤
邱盈达
唐心陆
洪志斌
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Application filed by Advanced Semiconductor Engineering Inc filed Critical Advanced Semiconductor Engineering Inc
Publication of CN110120380A publication Critical patent/CN110120380A/zh
Pending legal-status Critical Current

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Abstract

本发明涉及一种半导体封装，其包含电连接结构。所述电连接结构包含：第一导电层；所述第一传导层上的第二导电层；以及所述第一导电层与所述第二导电层之间的导电盖，所述导电性盖的硬度比所述第一导电层的硬度更大。

Description

半导体封装
技术领域
本发明大体上涉及半导体封装，且更确切地说涉及包含电连接结构的半导体封装，所述电连接结构具有改进剪切强度。
背景技术
铜对铜(Cu对Cu)接合技术可具有避免使用焊接材料或避免形成金属间化合物(IMC)的优势。然而，提高或增强由Cu对Cu接合技术形成的接合结构的接合力具有挑战性。
发明内容
在一些实施例中，具有相对较大硬度的导电盖(或杯)应用于导电层的顶部和侧部或侧面以接合到另一导电层。具有较大硬度的导电盖可在接合层之间的界面中产生改进剪切强度。
在一些实施例中，提供半导体封装。半导体封装包含电连接结构。电连接结构包含：第一导电层；第一传导层上的第二导电层；以及第一导电层与第二导电层之间的导电盖，导电性盖的硬度比第一导电层的硬度更大。
在一些实施例中，提供半导体封装。半导体封装包含：衬底；衬底上的第一导电层，所述第一导电层包含具有第一平均尺寸的晶粒；第一导电层上的第二导电层，所述第二导电层包含具有第二平均尺寸的晶粒；以及顶盖层，其覆盖第一导电层的第一表面和第一导电层的第二表面，所述顶盖层包含具有第三平均尺寸的晶粒；其中第三平均尺寸比第一平均尺寸以及第二平均尺寸更小。
在一些实施例中，提供一种形成电连接结构的方法。方法包含：提供第一导电层；在第一导电层上形成导电盖，导电盖的硬度比第一导电层的硬度更大；以及将第二导电层接合到导电盖。
附图说明
当结合附图阅读时，从以下详细描述最好地理解本发明的各方面。应注意，各种特征可能未按比例绘制，且各种特征的尺寸可出于论述的清楚起见而任意增大或减小。
图1是根据本发明的一些实施例的电连接结构的横截面视图。
图2是根据本发明的一些实施例的包含电连接结构的半导体封装的横截面视图。
图3A、图3B和3C是根据本发明的一些实施例的电连接结构的横截面视图。
图4A、图4B、图4C、图4D和图4E示意性地说明用于制造根据本发明的一些实施例的电连接结构的操作。
具体实施方式
在下文详细论述本发明的一些实施例的结构、制造和使用。然而，应了解，一些实施例阐述具有可在各种具体上下文中体现的多个适用的概念。应理解，以下揭示内容提供实施各种实施例的不同特征的许多不同实施例或实例。下文出于论述的目的描述组件和布置的具体实例。当然，这些只是实例且并不意欲为限制性的。
下文使用特定语言揭示图中所说明的一些实施例或实例。然而，将理解，所述实施例和实例并不希望是限制性的。如相关领域的普通技术人员通常将想到，所揭示的实施例中的一些的任何变更和修改以及本文件中所揭示的原理的任何进一步应用属于本发明的范围。
另外，应理解，可简要地描述设备的若干处理阶段(例如，操作)和/或特征。另外，在实施本文所描述的方法时或在使用本文中所描述的系统和设备时，可添加额外处理阶段和/或特征，且可移除或改变本文中所描述的某些处理阶段和/或特征。因此，以下描述应理解为表示实例，且并不希望指示每一实施方案包含一或多个阶段或特征。
此外，本发明可在各种实例中重复参考标号和/或字母。这种重复是出于简化和清楚的目的，且本身并不指示所论述的各种实施例和/或配置之间的关系。
另外，为易于描述，空间相关的术语(例如，“下方”、“下面”、“下部”、“上方”、“上部”及类似者)在本文中可用于描述如图中所说明的一个元件或特征与另一元件或特征的关系。除图中所描绘的定向以外，空间相关术语意欲包涵设备在使用或操作中的不同定向。装置可以其它方式定向(例如，旋转90度或处于其它定向)，且本文中所使用的空间相关描述词可相应地进行解释。
图1是根据本发明的一些实施例的电连接结构100的横截面视图。电连接结构100包含载体101和载体102。多个导电柱(例如，支柱、凸块或其它导电层或结构)103提供于载体101上。多个导电柱103可安置于载体101的表面101a上。多个导电衬垫104(或其它导电层或结构)提供于载体102上。多个导电柱103中的每一个与对应导电衬垫104对准。多个导电衬垫104可安置于载体102的表面102a上。
电连接结构100进一步包含多个导电盖105。多个导电盖105中的每一个提供于导电柱103与对应导电衬垫104之间。导电盖105与导电柱103直接接触。导电盖105还与导电衬垫104直接接触。具体地说，导电柱103和对应导电衬垫104经由导电盖105而非焊接材料接合在一起。
选择导电盖105的材料使得导电盖105具有较大硬度。替代地或者相结合，设计导电盖105的制造工艺使得导电盖105具有较大硬度。导电盖105的硬度可大于导电柱103的硬度，例如比导电柱103的硬度大至少约1.1倍或更大、至少约1.3倍或更大、或至少约1.5倍或更大。导电盖105的硬度可大于导电衬垫104的硬度，例如比导电衬垫104的硬度大至少约1.1倍或更大、至少约1.3倍或更大、或至少约1.5倍或更大。导电盖105的硬度可大于导电柱103的硬度以及导电衬垫104的硬度。在一些实施例中，导电盖105的硬度是至少1GPa或大于约1GPa(根据维氏硬度试验以SI为单位的压痕硬度)，例如约1.2GPa或更大、约1.5GPa或更大、约1.8GPa或更大、或约2GPa或更大。在一些实施例中，导电盖105的硬度是至多3.5GPa或小于约3.5GPa。在一些实施例中，导电盖105的硬度范围介于约1.2GPa到约3.1GPa。导电柱103、导电衬垫104和导电盖105可由相同导电材料(例如，具有相同元素组成)形成。导电柱103、导电衬垫104和导电盖105可由铜形成(其中导电盖105由具有较大硬度的铜形成)。导电柱103、导电衬垫104和导电盖105可由另一金属或金属合金形成，且可由不同导电材料形成。
在一些实施例中，导电盖105形成为导电杯(杯形导电结构)。导电杯覆盖导电柱103(面朝导电衬垫104)的上表面103a和导电柱103的侧面103b，其中上表面103a和侧面103b是非平行表面，且侧面103b与上表面103a相交并且相对于上表面103a成非零角度定向(例如，大体上垂直)。导电杯包围导电柱103的外部表面(包含上表面103a和侧面103b)且定义内腔从而容纳导电柱103且在其中安置导电柱103。导电杯可包含保形地形成于导电柱103的上表面103a上和导电柱103的侧面103b上的导电膜或顶盖层。在一些实施例中，导电膜的厚度是至少0.1μm或大于约0.1μm，例如约0.3μm或更大、或约0.5μm或更大。在一些实施例中，导电膜的厚度是至少1μm或大于约1μm，例如约1.1μm或更大、或约1.2μm或更大。
载体101可以是半导体芯片(或管芯)、插入件或封装衬底。类似地，载体102可以是半导体芯片、插入件或封装衬底。图2是根据本发明的一些实施例的包含电连接结构的半导体封装200的横截面视图。半导体封装200包含半导体芯片201和插入件202。多个铜柱203提供于半导体芯片201的表面201a上。多个铜衬垫204提供于插入件202上。多个铜柱203中的每一个与对应铜衬垫204对准。多个铜衬垫204可安置于插入件202的表面202a上。半导体封装200进一步包含提供于铜柱203与铜衬垫204之间的多个铜盖205。铜柱203和铜衬垫204经由铜盖205接合在一起。铜衬垫204通过插入件202中的互连结构207来电耦合到焊料凸块206。焊料凸块206电耦合到封装衬底208。
图3A是根据本发明的一些实施例的电连接结构300的横截面视图。电连接结构300包含载体301和载体302。多个铜柱303提供于载体301上。多个铜柱304提供于载体302上。电连接结构300进一步包含提供于铜柱303与铜柱304之间的多个铜盖305。铜柱303和铜柱304经由铜盖305接合在一起。
铜柱303包含具有第一平均尺寸的晶粒。铜柱304包含具有第二平均尺寸的晶粒。铜盖305包含具有第三平均尺寸的晶粒。在一些实施例中，第三平均尺寸小于第一平均尺寸，例如是第一平均尺寸的约0.9倍或更小、约0.8倍或更小、或约0.7倍或更小。在一些实施例中，第三平均尺寸小于第二平均尺寸，例如是第二平均尺寸的约0.9倍或更小、约0.8倍或更小、或约0.7倍或更小。在一些实施例中，第三平均尺寸小于第一平均尺寸以及第二平均尺寸。在一些实施例中，第一平均尺寸与第二平均尺寸大体上相同。在一些实施例中，第一平均尺寸不同于第二平均尺寸。
图3B和图3C展示图3A中如由虚线矩形块标记为306所指示的电连接结构300的一部分。如可看出，铜盖305的第三平均晶粒尺寸小于铜柱303的第一平均晶粒尺寸以及铜柱304的第二平均晶粒尺寸。由于晶粒平均尺寸的差异，铜柱304与铜盖305之间的接合力大大增强。
图4A到图4E示意性地说明用于制造根据本发明的一些实施例的电连接结构的操作。
在图4A中，提供载体401。载体401设置有多个铜柱403。铜柱403在载体401上的形成可包含以下阶段：在载体401上溅镀凸块下金属化(UBM)层，在UBM层上涂覆光阻层，使光阻层图案化从而形成暴露下面的UBM层的开口，用铜填充开口，剥去其余的光阻层且蚀刻UBM层的非所需部分。
在图4B中，藉由电镀将具有增强硬度的铜膜405涂覆到载体401的上表面上。铜膜覆盖铜柱403的上表面和侧面。在电解质溶液中用一或多种添加剂进行电镀，所述添加剂可增强待电镀的铜膜405的硬度。这些添加剂可包含以10ml/L或低于约10ml/L的浓度作为硬化剂添加到电解质溶液的含硫化合物(例如，有机硫化合物[备注：如果存在特定含硫化合 物作为添加剂，那么请识别为实例])。电镀铜膜405的硬度一般随添加剂浓度增加而增大。举例而言，在添加剂浓度是约2ml/L情况下，电镀铜膜405的硬度是约1.98GPa；在添加剂浓度是约6ml/L情况下，电镀铜膜405的硬度是约2.86GPa；以及在添加剂浓度是约10ml/L情况下，电镀铜膜405的硬度是约3.05GPa。应注意，当浓度高于10ml/L时，电镀铜膜405的硬度与使用约10ml/L浓度的硬度相比不存在进一步显著增大。
在图4C中，通过蚀刻移除安置于载体401上的铜膜405的一部分。
在图4D中，提供载体402。载体402设置有多个铜衬垫404。铜衬垫404与铜柱403对准。
在图4E中，铜衬垫404通过直接铜对铜接合技术(例如，扩散接合)来接合到铜膜405。可在指定接合条件下进行接合。接合条件包含例如温度在约200℃到约250℃之间以及压力在约15MPa到约20MPa之间。由于铜膜405具有增强硬度，铜膜405与铜衬垫404之间的接合在铜膜405与铜衬垫404之间的界面处产生改进剪切强度，因此有效地降低在界面处的剥落。
在一些实施例的描述中，提供或安置于另一组件“上”或“上方”的组件可涵盖前一组件直接在后一组件上(例如，与后一组件物理或直接接触)的情况，以及一或多个中间组件位于前一组件与后一组件之间的情况。
此外，有时在本文中以范围格式呈现量、比率和其它数值。应理解，这类范围格式是为了便利和简洁而使用，且应灵活地理解，不仅包含明确地指定为范围极限的数值，而且包含涵盖于那个范围内的所有个别数值或子范围，如同明确地指定每一数值和子范围一般。
如本文中所使用，术语“大约”、“大体上”、“实质上”以及“约(around/about)”用以描述和考虑较小变化。当与事件或情况结合使用时，所述术语可指事件或情况精确发生的例子以及事件或情况极近似地发生的例子。举例来说，当结合数值使用时，术语可指小于或等于所述数值的±10％的变化范围，例如小于或等于±5％、小于或等于±4％、小于或等于±3％、小于或等于±2％、小于或等于±1％、小于或等于±0.5％、小于或等于±0.1％，或小于或等于±0.05％。举例来说，如果两个数值之间的差值小于或等于所述值的平均值的±10％，例如小于或等于±5％、小于或等于±4％、小于或等于±3％、小于或等于±2％、小于或等于±1％、小于或等于±0.5％、小于或等于±0.1％、或小于或等于±0.05％，那么可认为所述两个数值“大体上”相同。举例来说，“大体上”平行可指代相对于0°的小于或等于±10°的角度变化范围，例如小于或等于±5°、小于或等于±4°、小于或等于±3°、小于或等于±2°、小于或等于±1°、小于或等于±0.5°、小于或等于±0.1°、或小于或等于±0.05°。举例来说，“大体上”垂直可指代相对于90°的小于或等于±10°的角度变化范围，例如小于或等于±5°、小于或等于±4°、小于或等于±3°、小于或等于±2°、小于或等于±1°、小于或等于±0.5°、小于或等于±0.1°、或小于或等于±0.05°。
如本文中所使用，术语“导电(conductive/electrically conductive)”和“电导率”指代传递电流的能力。导电材料通常指示对电流流动呈现极少或零对抗的那些材料。电导率的一个量度是西门子每米(S/m)。通常，导电材料是导电率大于大约104S/m，例如至少105S/m或至少106S/m的一种材料。材料的电导率有时可随温度而变化。除非另外指定，否则材料的电导率是在室温下测量。
尽管已参考本发明的特定实施例描述并说明本发明，但这些描述和说明并不限制本发明。所属领域的技术人员应理解，可在不脱离如由随附权利要求书界定的本发明的真实精神和范围的情况下，作出各种改变且取代等效物。说明可能未必按比例绘制。由于制造工艺和公差，本发明中的艺术再现与实际装置之间可存在区别。可存在并未特定说明的本发明的其它实施例。应将本说明书和图式视为说明性而非限定性的。可进行修改，以使特定情形、材料、物质组成、方法或工艺适宜于本发明的目标、精神和范围。所有这类修改是既定在随附权利要求书的范围内。虽然本文中所揭示的方法已参考按特定次序执行的特定操作加以描述，但应理解，可在不脱离本发明的教示的情况下组合、细分或重新排序这些操作以形成等效方法。因此，除非本文中特别指示，否则操作的次序和分组并非本发明的限制。

Claims (20)

1.一种电连接结构，其包括：
第一导电层；
第二导电层；以及
所述第一导电层与所述第二导电层之间的导电盖，所述导电盖的硬度比所述第一导电层的硬度更大。
2.根据权利要求1所述的电连接结构，其中所述导电盖的所述硬度比所述第二导电层的硬度更大。
3.根据权利要求1所述的电连接结构，其中所述导电盖的所述硬度是至少约1GPa。
4.根据权利要求3所述的电连接结构，其中所述导电盖的所述硬度是至多约3.5GPa。
5.根据权利要求4所述的电连接结构，其中所述导电盖的所述硬度介于约1.2GPa到约3.1GPa范围内。
6.根据权利要求1所述的电连接结构，其中所述导电盖覆盖所述第一导电层的第一表面和所述第一导电层的第二表面，且所述第一表面相对于所述第二表面成非零角度定向。
7.根据权利要求6所述的电连接结构，其中所述导电盖是保形地形成于所述第一导电层的所述第一表面和所述第二表面上的导电膜。
8.根据权利要求7所述的电连接结构，其中所述导电膜的厚度是至少约0.1μm。
9.根据权利要求7所述的电连接结构，其中所述导电膜的厚度是至少约1μm。
10.一种半导体封装，其包括：
衬底；
衬底上的第一导电层，所述第一导电层包含具有第一平均尺寸的晶粒；
第一导电层上的第二导电层，所述第二导电层包含具有第二平均尺寸的晶粒；以及
顶盖层，其覆盖所述第一导电层的第一表面和所述第一导电层的第二表面，所述顶盖层包括具有第三平均尺寸的晶粒，
其中所述第三平均尺寸比所述第一平均尺寸以及所述第二平均尺寸更小。
11.根据权利要求10所述的半导体封装，其中所述第一平均尺寸与所述第二平均尺寸大体上相同。
12.根据权利要求10所述的半导体封装，其中所述第一平均尺寸不同于所述第二平均尺寸。
13.根据权利要求10所述的半导体封装，其中所述第一导电层、所述第二导电层和所述顶盖层包含相同元素组成。
14.根据权利要求10所述的半导体封装，其中所述第一导电层、所述第二导电层和所述顶盖层包含相同金属。
15.根据权利要求10所述的半导体封装，其中所述第一导电层、所述第二导电层和所述顶盖层各自包含铜。
16.根据权利要求10所述的半导体封装，其中所述第一导电层的所述第一表面相对于所述第一导电层的所述第二表面成非零角度定向。
17.根据权利要求10所述的半导体封装，其中所述第一导电层的所述第一表面大体上垂直于所述第一导电层的所述第二表面。
18.一种形成电连接结构的方法，其包括：
提供第一导电层；
在所述第一导电层上形成导电盖，所述导电盖的硬度比所述第一导电层的硬度更大；以及
将第二导电层接合到所述导电盖。
19.根据权利要求18所述的方法，其中在所述第一导电层上形成所述导电盖包含将铜膜电镀在所述第一导电层上。
20.根据权利要求18所述的方法，其中将所述第二导电层接合到所述导电盖是在温度介于约200℃到约250℃范围内且压力介于约15MPa到约20MPa范围内条件下进行。
CN201810281728.4A 2018-02-07 2018-04-02 半导体封装 Pending CN110120380A (zh)

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