CN110097858B

CN110097858B - Source driver

Info

Publication number: CN110097858B
Application number: CN201810156962.4A
Authority: CN
Inventors: 黄智全; 吕骅洺
Original assignee: Raydium Semiconductor Corp
Current assignee: Raydium Semiconductor Corp
Priority date: 2018-01-30
Filing date: 2018-02-24
Publication date: 2021-06-08
Anticipated expiration: 2038-02-24
Also published as: CN110097858A; TW201933312A; TWI646516B

Abstract

The invention discloses a source driver. The source driver includes a first operational amplifier, a boost circuit, and a first switch unit. The first operational amplifier is controlled by a control signal, and the highest potential of the control signal is a working voltage. The boost circuit is used for boosting the working voltage into a boost voltage and generating an exchange switch control signal according to the boost voltage, wherein the highest potential of the exchange switch control signal is the boost voltage, and the boost voltage is higher than the working voltage. The first switch unit is coupled to the first operational amplifier. The first exchange switch unit has an on-resistance when being controlled by the exchange switch control signal to be conducted. If the first switch unit has the original on-resistance when being controlled by the control signal and is switched on, the on-resistance is smaller than the original on-resistance.

Description

Source driver

Technical Field

The present invention relates to a display device, and more particularly, to a source driver applied to a display device.

Background

Generally, as the size of the lcd panel is larger, the output load of the driver IC of the display device is heavier, and the driver IC of the display device is exposed to a problem of over-temperature.

In detail, in the conventional source driver, the highest potential of the control signal of the swap switch coupled to the output terminal of the operational amplifier of each channel is usually the same as the control signal of the operational amplifier and is a working voltage, which causes that the equivalent impedance (i.e., the On-resistance) of the swap switch cannot be effectively reduced, so that the Slew rate (Slew rate) of the operational amplifier is not good. When the output current generated by the operational amplifier charging or discharging the load flows through a large on-resistance, a large power loss is generated and the temperature of the driving IC is too high, which needs to be overcome.

Disclosure of Invention

Accordingly, the present invention is directed to a source driver, which effectively solves the above-mentioned problems encountered in the prior art.

One embodiment according to the present invention is a source driver. In this embodiment, the source driver includes a first operational amplifier, a voltage boosting circuit, and a first switch unit. The first operational amplifier is controlled by a control signal, and the highest potential of the control signal is a working voltage. The boost circuit is used for boosting the working voltage into a boost voltage and generating an exchange switch control signal according to the boost voltage, wherein the highest potential of the exchange switch control signal is the boost voltage, and the boost voltage is higher than the working voltage. The first switch unit is coupled to the first operational amplifier. The first exchange switch unit has an on-resistance when being controlled by the exchange switch control signal to be conducted. If the first switch unit is controlled by the control signal and has an original on-resistance when being switched on, the on-resistance is smaller than the original on-resistance.

In one embodiment, the power consumption is generated when the output current outputted by the first operational amplifier flows through the first switch unit having the on-resistance, and the power consumption is smaller than the original power consumption generated when the output current flows through the first switch unit having the original on-resistance.

In one embodiment, the amount of temperature increase caused by power consumption is less than the original amount of temperature increase caused by the original power consumption.

In one embodiment, the source driver further includes a second operational amplifier and a second switch unit. The second operational amplifier is controlled by the working voltage. The second switch unit is coupled to the second operational amplifier, and has a conducting resistance smaller than the original conducting resistance when the second switch unit is controlled by the switch control signal to be conducted.

In one embodiment, when the output current outputted by the second operational amplifier flows through the second switch unit having the on-resistance, the power consumption is less than the original power consumption generated when the output current flows through the second switch unit having the original on-resistance.

In one embodiment, the source driver further includes a timing control circuit (Sequence control circuit) coupled between the boost circuit and the first switch unit and controlled by the boost voltage.

In one embodiment, the boost circuit is a Charge pump (Charge pump) circuit.

In one embodiment, the charge pump circuit includes a first switch, a second switch, a third switch, a fourth switch and a capacitor. The first switch and the second switch are connected between the working voltage and the grounding voltage in series, the third switch and the fourth switch are connected between the working voltage and the voltage difference obtained by subtracting the working voltage from the boosting voltage, one end of the capacitor is coupled between the first switch and the second switch, the other end of the capacitor is coupled between the third switch and the fourth switch, the first switch and the fourth switch are controlled by a first clock signal, the second switch and the third switch are controlled by a second clock signal, and the first clock signal and the second clock signal are opposite in phase.

In one embodiment, the boost circuit is a Bootstrap circuit (Bootstrap circuit).

In one embodiment, the bootstrap circuit includes a first switch, a second switch, a first resistor, a second resistor, a diode and a capacitor. The first switch and the first resistor are connected between the working voltage and the grounding voltage in series, the second resistor and the second switch are connected between the boosting voltage minus the working voltage and the grounding voltage in series, one end of the capacitor is coupled between the first switch and the first resistor, the other end of the capacitor is coupled between the boosting voltage minus the working voltage, the diode is coupled between the working voltage and the boosting voltage, the first switch is also coupled between the second resistor and the second switch, and the second switch is controlled by a clock signal.

Compared with the prior art, the source driver according to the invention utilizes the booster circuit to increase the highest potential of the control signal of the swap switch in the source driver from the original working voltage to a boosted voltage, so that the on-resistance of the swap switch is reduced, the power consumption of the swap switch when the output current flows through can be reduced, the temperature of the source driver is effectively reduced, and the slew rate of the operational amplifier of each channel can be increased, thereby effectively overcoming the problems encountered in the prior art.

The advantages and spirit of the present invention can be further understood by the following detailed description of the invention and the accompanying drawings.

Drawings

Fig. 1 is a schematic diagram of a source driver according to a preferred embodiment of the invention.

Fig. 2 shows an embodiment in which the boosting circuit is a charge pump circuit.

FIG. 3 is an embodiment of a boost circuit as a bootstrap circuit.

Fig. 4 is a graph of the switch control signals having different maximum potentials resulting in different on-resistances of the switch.

FIG. 5A is a graph comparing the commutation switch control signals before and after the boost process; fig. 5B is a comparison diagram of the influence of the change-over switch control signal before and after the voltage boosting process on the waveform of the output signal.

Fig. 6 is a graph comparing the influence of the on-resistance of the commutation switch before and after the commutation switch control signal is boosted.

Description of the main element symbols:

SD: source driver

PDAC: a first digital-to-analog converter

NDAC: second digital-to-analog converter

And MUX: multiplexer

OP 1: a first operational amplifier

OP 2: a second operational amplifier

SU 1: first exchange switch unit

SU 2: second exchange switch unit

BVC: voltage booster circuit

SC: sequential control circuit

OUT 1: a first output terminal

OUT 2: second output terminal

+: positive input end

-: negative input terminal

AVDD: operating voltage

STB: exchanging switch control signals

VBST: boosted voltage

IOUT: output current

SW 1-SW 4: first to fourth switches

C1: capacitor with a capacitor element

GND: ground voltage

VBST-AVDD: voltage difference of boosted voltage minus working voltage

CLK 1-CLK 2: first to second clock signals

CLK: clock signal

M1-M2: first to second transistor switches

R1-R2: first to second resistors

D: diode with a high-voltage source

RON: on-resistance

VG 1-VG 3: maximum potential

VDS 1: drain-source voltage

VMIN: lowest potential

RON 1-RON 3: on-resistance

STB1 to STB 3: exchanging switch control signals

ON: open state

OFF: closed state

STB 0: primitive swap switch control signal

And (3) SOUT: output signal

SOUT 0: raw output signal

T0-T8: time of day

RON 0: original on-resistance

Detailed Description

One embodiment according to the present invention is a source driver. In this embodiment, the source driver is disposed in the display device for driving the liquid crystal display panel.

Referring to fig. 1, fig. 1 is a schematic diagram of a source driver in this embodiment. As shown in fig. 1, the source driver SD includes a first digital-to-analog converter PDAC, a second digital-to-analog converter NDAC, a multiplexer MUX, a first operational amplifier OP1, a second operational amplifier OP2, a first switch unit SU1, a second switch unit SU2, a boost circuit BVC, a timing control circuit SC, a first output end OUT1, and a second output end OUT 2.

The output ends of the first digital-to-analog converter PDAC and the second digital-to-analog converter NDAC are respectively coupled to two input ends of the multiplexer MUX; two output ends of the multiplexer MUX are respectively coupled to the positive input ends + of the first operational amplifier OP1 and the second operational amplifier OP 2; the negative inputs of the first operational amplifier OP1 and the second operational amplifier OP2 are coupled to their own outputs, respectively; the output ends of the first operational amplifier OP1 and the second operational amplifier OP2 are respectively coupled to the first switch unit SU1 and the second switch unit SU 2; the boosting circuit BVC is coupled to the timing control circuit SC; the timing control circuit SC is respectively coupled to the first switch unit SU1 and the second switch unit SU 2; the first output end OUT1 is coupled to the first switch unit SU1 and the second switch unit SU2 respectively; the second output terminal OUT2 is coupled to the first and second switch units SU1 and SU2, respectively.

The first operational amplifier OP1 and the second operational amplifier OP2 are both controlled by the working voltage AVDD. The output terminals of the first operational amplifier OP1 and the second operational amplifier OP2 respectively output an output current IOUT to the first switch unit SU1 and the second switch unit SU 2.

When the boost circuit BVC receives the working voltage AVDD, the boost circuit BVC boosts the working voltage AVDD to form a boost voltage VBST, and then generates the swap switch control signal STB to the first swap switch unit SU1 and the second swap switch unit SU2 according to the boost voltage VBST.

It should be noted that the highest level of the swap switch control signal STB is the boost voltage VBST, and the boost voltage VBST is higher than the operating voltage AVDD. In practice, the boost voltage VBST may have a proportional relationship with the operating voltage AVDD and may be adjusted according to actual requirements, for example, but not limited to, the boost voltage VBST is 1.5 times the operating voltage AVDD or 2 times the operating voltage AVDD.

In addition, a timing control circuit SC may be coupled between the boost circuit BVC and the first and second switching units SU1 and SU 2. The timing control circuit SC is controlled by the boost voltage VBST to control the timing of transmitting the switch control signal STB to the first switch unit SU1 and the second switch unit SU 2.

In this embodiment, the first switch unit SU1 includes a first switch M1 and a second switch M2. The first swap switch M1 is coupled between the output terminal of the first operational amplifier OP1 and the first output terminal OUT1, and its gate is controlled by the swap switch control signal STB; the second switch M2 is coupled between the output terminal of the first operational amplifier OP1 and the second output terminal OUT2, and has a gate controlled by the switch control signal STB.

It should be noted that, it is assumed that the first swap switch M1 and the second swap switch M2 of the first swap switch unit SU1 of the present invention are controlled by the swap switch control signal STB with the highest voltage level being the boost voltage VBST and have the on-resistance RON when turned on, while the first swap switch M1 and the second swap switch M2 of the first swap switch unit SU1 of the prior art are controlled by the control signal with the highest voltage level being the working voltage AVDD and have the original on-resistance RON0 when turned on, and since the boost voltage VBST is higher than the working voltage AVDD, the on-resistance RON when turned on of the swap switch of the present invention is smaller than the original on-resistance RON0 when turned on of the swap switch of the prior art.

It is assumed that the consumed power P is generated when the output current IOUT outputted from the output terminal of the first operational amplifier OP1 of the present invention flows through the first switch unit SU1 having the on-resistance RON, whereas the original consumed power P0 is generated when the output current IOUT flows through the first switch unit SU1 having the original on-resistance RON0 in the prior art. The power consumption P of the switch of the present invention is equal to the square of the output current IOUT multiplied by the on-resistance RON, and the original power consumption P0 of the switch of the prior art is equal to the square of the output current IOUT multiplied by the original on-resistance RON 0. Since the on-resistance RON is smaller than the original on-resistance RON0, the power consumption P of the switch of the present invention is smaller than the original power consumption P0 of the switch of the prior art, and the temperature rise T caused by the power consumption P of the switch of the present invention is smaller than the original temperature rise T0 caused by the original power consumption P0 of the switch of the prior art.

Similarly, the second switch unit SU2 includes a third switch M3 and a fourth switch M4. The third swap switch M3 is coupled between the output terminal of the second operational amplifier OP2 and the first output terminal OUT1, and its gate is controlled by the swap switch control signal STB; the fourth switch M4 is coupled between the output terminal of the second operational amplifier OP2 and the second output terminal OUT2, and has a gate controlled by the switch control signal STB.

Assuming that the third swap switch M3 and the fourth swap switch M4 of the second swap switch unit SU2 of the present invention are controlled by the swap switch control signal STB with the highest voltage level being the boost voltage VBST and have the on-resistance RON when turned on, and the third swap switch M3 and the fourth swap switch M4 of the second swap switch unit SU2 of the prior art are controlled by the control signal with the highest voltage level being the working voltage AVDD and have the original on-resistance RON0 when turned on, since the boost voltage VBST is higher than the working voltage AVDD, the on-resistance RON when the swap switch of the present invention is turned on is smaller than the original on-resistance RON0 when the swap switch of the prior art is turned on.

Assuming that the output current IOUT outputted from the output terminal of the second operational amplifier OP2 of the present invention generates the consumed power P when flowing through the third switch M3 and the fourth switch M4 of the second switch unit SU2 having the on-resistance RON, and the output current IOUT of the prior art generates the original consumed power P0 when flowing through the switch having the original on-resistance RON0, the consumed power P of the switch of the present invention is smaller than the original consumed power P0 of the switch of the prior art because the on-resistance RON is smaller than the original on-resistance RON0, and the temperature increase T caused by the consumed power P of the switch of the present invention is lower than the original temperature increase T0 caused by the original consumed power P0 of the switch of the prior art.

In practical applications, the boost circuit BVC may be a Charge pump (Charge pump) circuit or a Bootstrap circuit (Bootstrap circuit), but is not limited thereto.

Referring to fig. 2, fig. 2 shows an embodiment of the charge pump circuit as the boost circuit BVC.

As shown in fig. 2, the boost circuit (charge pump circuit) BVC may include a first switch SW1, a second switch SW2, a third switch SW3, a fourth switch SW4, and a capacitor C1. The first switch SW1 and the second switch SW2 are connected in series between the working voltage AVDD and the ground voltage GND, and the third switch SW3 and the fourth switch SW4 are connected in series between the working voltage AVDD and (the voltage difference between the boosted voltage VBST minus the working voltage AVDD). One end of the capacitor C1 is coupled between the first switch SW1 and the second switch SW2, and the other end of the capacitor C1 is coupled between the third switch SW3 and the fourth switch SW 4.

It should be noted that the first switch SW1 and the fourth switch SW4 are controlled by the first clock signal CLK1, and the second switch SW2 and the third switch SW3 are controlled by the second clock signal CLK 2. The first clock signal CLK1 and the second clock signal CLK2 are inverted with respect to each other. That is, when the first switch SW1 and the fourth switch SW4 are controlled by the first clock signal CLK1 to be turned on, the second switch SW2 and the third switch SW3 are controlled by the second clock signal CLK2 to be turned off; when the first switch SW1 and the fourth switch SW4 are controlled by the first clock signal CLK1 to be turned off, the second switch SW2 and the third switch SW3 are controlled by the second clock signal CLK2 to be turned on.

Referring to fig. 3, fig. 3 shows an embodiment in which the boost circuit BVC is a bootstrap circuit.

As shown in fig. 3, the boost circuit (bootstrap circuit) BVC may include a first transistor switch M1, a second transistor switch M2, a first resistor R1, a second resistor R2, a diode D, and a capacitor C1. The first transistor switch M1 and the first resistor R1 are connected in series between the operating voltage AVDD and the ground voltage GND, the second resistor R2 and the second transistor switch M2 are connected in series between the boost voltage VBST and the ground voltage GND, one end of the capacitor C1 is coupled between the first transistor switch M1 and the first resistor R1, the other end of the capacitor C1 is coupled to the boost voltage VBST, the first transistor switch M1 is also coupled between the second resistor R2 and the second transistor switch M2, and the second transistor switch M2 is controlled by the clock signal CLK.

Referring to FIG. 4, FIG. 4 is a graph of the switching switch control signals STB 1-STB 3 with different maximum voltages VG 1-VG 3 causing the switching switch to have different on-resistances RON 1-RON 3. As can be seen from fig. 4: for the same switch drain-source voltage VDS1, when the highest level of the switch control signal is boosted from VG1, which is originally lower, to VG3, the on-resistance of the switch controlled by the switch control signal is correspondingly reduced from RON1, which is originally higher, to RON3, which is lower.

Referring to fig. 5A and 5B, fig. 5A is a comparison diagram of the control signals of the swap switch before and after the boosting process; fig. 5B is a comparison diagram of the influence of the change-over switch control signal before and after the voltage boosting process on the waveform of the output signal.

As shown in fig. 5A and 5B, the highest potential of the swap switch control signal STB0 without voltage boosting is the operating voltage AVDD, and the highest potential of the swap switch control signal STB after voltage boosting is the boost voltage VBST, and the boost voltage VBST is significantly higher than the operating voltage AVDD.

At time T0, as can be seen from fig. 5A: the non-boosted switch control signal STB0 rises from the lowest level VMIN to the operating voltage AVDD, and the boosted switch control signal STB rises from the lowest level VMIN to the boosted voltage VBST, i.e., both are switched from the OFF (OFF) state to the ON (ON) state. As can be seen from fig. 5B: the waveform of the output signal SOUT affected by the boosted switch control signal STB rises faster to reach the desired value at time T1, while the waveform of the output signal SOUT0 affected by the non-boosted switch control signal STB0 rises slower to reach the desired value at time T2.

During the time period from T0 to T3, the non-boosted STB0 and the boosted STB are both maintained in the ON (ON) state.

At time T3, as can be seen from fig. 5A: the non-boosted STB0 is lowered from the AVDD to the VMIN and maintained to the time T4, and the boosted STB is lowered from the VBST to the VMIN and maintained to the time T4, i.e. both are switched from the ON (ON) state to the OFF (OFF) state and maintained to the time T4 at the time T3. As can be seen from fig. 5B: during the time period from T3 to T4, the waveforms of the original output signal SOUT0 affected by the non-boosted swap switch control signal STB0 and the output signal SOUT affected by the boosted swap switch control signal STB are maintained at their ideal values.

At time T4, as can be seen from fig. 5A: the non-boosted switch control signal STB0 rises from the lowest level VMIN to the operating voltage AVDD, and the boosted switch control signal STB rises from the lowest level VMIN to the boosted voltage VBST, i.e., both are switched from the OFF (OFF) state to the ON (ON) state. As can be seen from fig. 5B: the waveform of the output signal SOUT affected by the boosted switch control signal STB falls faster to reach the desired value at time T5, while the waveform of the original output signal SOUT0 affected by the non-boosted switch control signal STB0 falls slower to reach the desired value at time T6.

During the time period from T4 to T7, the non-boosted STB0 and the boosted STB are both maintained in the ON (ON) state.

At time T7, as can be seen from fig. 5A: the non-boosted STB0 is lowered from the AVDD to the VMIN and maintained to the time T4, and the boosted STB is lowered from the VBST to the VMIN and maintained to the time T4, i.e. both are switched from the ON (ON) state to the OFF (OFF) state and maintained to the time T8 at the time T7. As can be seen from fig. 5B: during the time period from T7 to T8, the waveforms of the original output signal SOUT0 affected by the non-boosted swap switch control signal STB0 and the output signal SOUT affected by the boosted swap switch control signal STB are maintained at the ideal values. The rest can be analogized from the above, and the description is omitted.

Referring to fig. 6, fig. 6 is a graph comparing the influence of the boost of the commutation switch control signal on the on-resistance of the commutation switch. As shown in fig. 6, assuming that the switch controlled by the boosted switch control signal STB has the on-resistance RON when it is turned on, and the switch controlled by the non-boosted switch control signal STB0 has the original on-resistance RON0 when it is turned on, since the highest potential (boost voltage VBST) of the boosted switch control signal STB is higher than the highest potential (operating voltage AVDD) of the non-boosted switch control signal STB0, it can be clearly seen by comparing the on-resistance RON curve in fig. 6 with the original on-resistance RON0 curve: the on-resistance RON when the switch controlled by the boosted switch control signal STB is turned on is less than the original on-resistance RON0 when the switch controlled by the non-boosted switch control signal STB0 is turned on, so that the effect of reducing the on-resistance when the switch is turned on can be achieved.

In addition, since the on-resistance RON when the switch controlled by the boosted switch control signal STB is turned on is smaller than the original on-resistance RON0 when the switch controlled by the non-boosted switch control signal STB0 is turned on, the power consumption of the output current flowing through the switch controlled by the boosted switch control signal STB is smaller than the power consumption of the output current flowing through the switch controlled by the non-boosted switch control signal STB0, thereby effectively reducing the temperature of the source driver. For example, from experimental data it can be found that: the temperature of the source driver after the boosting process can be reduced by about 3 to 4 ℃ compared with the temperature of the source driver without the boosting process, so that the influence of the over-high temperature of the source driver on the performance can be effectively avoided.

The above embodiments are combined to show that: compared with the prior art, the source driver according to the invention utilizes the booster circuit to increase the highest potential of the control signal of the swap switch in the source driver from the original working voltage to a boosted voltage, so that the on-resistance of the swap switch is reduced, the power consumption of the swap switch when the output current flows through can be reduced, the temperature of the source driver is effectively reduced, and the slew rate of the operational amplifier of each channel can be increased, thereby effectively overcoming the problems encountered in the prior art.

The foregoing detailed description of the preferred embodiments is intended to more clearly illustrate the features and spirit of the present invention, and not to limit the scope of the invention by the preferred embodiments disclosed above. On the contrary, it is intended to cover various modifications and equivalent arrangements included within the scope of the claims.

Claims

1. A source driver, comprising:

the first operational amplifier is controlled by a control signal, and the highest potential of the control signal is a working voltage;

the boost circuit is used for boosting the working voltage into a boost voltage and generating an exchange switch control signal according to the boost voltage, wherein the highest potential of the exchange switch control signal is the boost voltage, and the boost voltage is higher than the working voltage; and

a first switch unit coupled to the first operational amplifier and having a conducting resistance when the first switch unit is controlled by the switch control signal to be conducted;

if the first exchange switch unit is controlled by the control signal and has an original on-resistance when being conducted, the on-resistance is smaller than the original on-resistance.

2. The source driver of claim 1, wherein a power consumption is generated when an output current outputted from the first operational amplifier flows through the first switch unit having the on-resistance, and the power consumption is smaller than an original power consumption generated when the output current flows through the first switch unit having the original on-resistance.

3. The source driver of claim 2, wherein a temperature rise caused by the consumed power is lower than an original temperature rise caused by the original consumed power.

4. The source driver of claim 1, further comprising:

a second operational amplifier controlled by the working voltage; and

and the second exchange switch unit is coupled with the second operational amplifier, has the on-resistance when being controlled by the exchange switch control signal to be conducted, and is smaller than the original on-resistance.

5. The source driver of claim 4, wherein a power consumption is generated when an output current outputted from the second operational amplifier flows through the second switch unit having the on-resistance, and the power consumption is smaller than an original power consumption generated when the output current flows through the second switch unit having the original on-resistance.

6. The source driver of claim 5, wherein a temperature rise caused by the consumed power is lower than an original temperature rise caused by the original consumed power.

7. The source driver of claim 1, further comprising:

and the time sequence control circuit is coupled between the boosting circuit and the first exchange switch unit and is controlled by the boosting voltage.

8. The source driver of claim 1, wherein the boost circuit is a charge pump circuit.

9. The source driver as claimed in claim 8, wherein the charge pump circuit comprises a first switch, a second switch, a third switch, a fourth switch and a capacitor, the first switch and the second switch are connected in series between the working voltage and a ground voltage, the third switch and the fourth switch are connected in series between the working voltage and a voltage difference obtained by subtracting the working voltage from the boost voltage, one end of the capacitor is coupled between the first switch and the second switch, the other end of the capacitor is coupled between the third switch and the fourth switch, the first switch and the fourth switch are controlled by a first clock signal, the second switch and the third switch are controlled by a second clock signal, and the first clock signal and the second clock signal are inverted with respect to each other.

10. The source driver of claim 1, wherein the boost circuit is a bootstrap circuit.

11. The source driver as claimed in claim 10, wherein the bootstrap circuit comprises a first switch, a second switch, a first resistor, a second resistor, a diode and a capacitor, the first switch and the first resistor are connected in series between the working voltage and a ground voltage, the second resistor and the second switch are connected in series between the boost voltage minus the working voltage and the ground voltage, one end of the capacitor is coupled between the first switch and the first resistor, the other end of the capacitor is coupled between the boost voltage minus the working voltage, the diode is coupled between the working voltage and the boost voltage, the first switch is also coupled between the second resistor and the second switch, and the second switch is controlled by a clock signal.