CN116097560A - Driver circuit - Google Patents

Driver circuit Download PDF

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Publication number
CN116097560A
CN116097560A CN202180056053.3A CN202180056053A CN116097560A CN 116097560 A CN116097560 A CN 116097560A CN 202180056053 A CN202180056053 A CN 202180056053A CN 116097560 A CN116097560 A CN 116097560A
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China
Prior art keywords
node
capacitor
switch
voltage
driver
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CN202180056053.3A
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Chinese (zh)
Inventor
A·S·多伊
E·金
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Cirrus Logic International Semiconductor Ltd
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Cirrus Logic International Semiconductor Ltd
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Priority claimed from US17/314,890 external-priority patent/US11684950B2/en
Priority claimed from US17/314,917 external-priority patent/US11277129B2/en
Priority claimed from US17/343,479 external-priority patent/US11606642B2/en
Application filed by Cirrus Logic International Semiconductor Ltd filed Critical Cirrus Logic International Semiconductor Ltd
Publication of CN116097560A publication Critical patent/CN116097560A/en
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/181—Low frequency amplifiers, e.g. audio preamplifiers
    • H03F3/183—Low frequency amplifiers, e.g. audio preamplifiers with semiconductor devices only
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/12—Arrangements for reducing harmonics from ac input or output
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/483—Converters with outputs that each can have more than two voltages levels
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H02M7/5387—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H02M7/5387—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
    • H02M7/53871—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H02M7/539—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters with automatic control of output wave form or frequency
    • H02M7/5395—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters with automatic control of output wave form or frequency by pulse-width modulation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/181—Low frequency amplifiers, e.g. audio preamplifiers
    • H03F3/183—Low frequency amplifiers, e.g. audio preamplifiers with semiconductor devices only
    • H03F3/185—Low frequency amplifiers, e.g. audio preamplifiers with semiconductor devices only with field-effect devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F3/217—Class D power amplifiers; Switching amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F3/217—Class D power amplifiers; Switching amplifiers
    • H03F3/2171—Class D power amplifiers; Switching amplifiers with field-effect devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F3/217—Class D power amplifiers; Switching amplifiers
    • H03F3/2173—Class D power amplifiers; Switching amplifiers of the bridge type
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/483—Converters with outputs that each can have more than two voltages levels
    • H02M7/4837—Flying capacitor converters

Abstract

A switch driver (401) for outputting a drive signal at an output node (402) for driving a load such as a transducer is described. The driver receives respective high-side and low-side voltages (VinH, vinL) defining an input voltage at a first and second input node and has connections for first and second capacitors (403H, 403L). The switched path network is configured to enable each of the first capacitor and the second capacitor to be selectively charged to the input voltage, the first input node being selectively couplable to a first node (N1) through a path that includes or bypasses the first capacitor, and the second input node being selectively couplable to a second node (N2) through a path that includes or bypasses the second capacitor. The output node (402) is switchable between two switching voltages at the first node or the second node. The driver is selectively operable in different modes of operation, wherein the switching voltage is different in each of the modes.

Description

Driver circuit
The field of representative embodiments of the present disclosure relates to methods, apparatus, and/or implementations related to driver circuits, and in particular, to switch driver circuits that may be used to drive transducers.
Many electronic devices include a transducer driver circuit for driving a transducer using a suitable drive signal, for example, for driving an audio output transducer of a host device or a connected accessory using an audio drive signal.
In some applications, the driver circuit may include a switching amplifier stage, such as a class D amplifier stage, for generating a drive signal for driving the transducer. The switching amplifier stage may be relatively power efficient and thus may be advantageously used in some applications. The switching amplifier stage generally operates to switch the output node between a defined high voltage and low voltage at a duty cycle that provides a desired average output voltage over time.
To provide for suppression of switching ripple, some series inductances may be included in the output path. In some implementations, the inductance may be provided by the load itself. For example, for audio applications driving a conventional cone and voice coil type loudspeaker, the self inductance of the voice coil of the loudspeaker may be sufficient. However, in some implementations, it may be advantageous to include an inductor in the output path as a component separate from the load. For example, piezoelectric or ceramic transducers may be advantageously used in some applications, particularly due to their relatively thin form factor. The capacitive nature of such transducers means that it may generally be beneficial to include an inductor in series with the transducer.
In applications that include an inductor as a separate component in the output path, the inductor will be selected to allow the peak expected current to flow without saturation. In some cases, this may require a relatively large inductance, which may be undesirable.
Embodiments of the present disclosure relate to a driving circuit that at least alleviates at least the above problems.
According to an aspect of the present disclosure, there is provided a driver circuit including a first switch driver for generating a first driving signal, the first switch driver including:
a first input node and a second input node for connection to respective high-side and low-side voltages defining an input voltage;
a capacitor node for connection to a first capacitor and a second capacitor;
a driver output node for outputting a first drive signal; and
a switch path network;
wherein the switch path network is configured such that, in use:
each of the first capacitor and the second capacitor may be selectively connected in series between the first input node and the second input node to charge to an input voltage; the first input node may be selectively coupled to the first selective boost node by a path including the first capacitors in series or by a path bypassing the first capacitors;
The second input node may be selectively coupled to the second selective boost node through a path including a second capacitor in series or through a path bypassing the second capacitor; and
a driver output node may be selectively coupled to the first selective boost node or the second selective boost node;
wherein the first switch driver is selectively operable in a plurality of different modes of operation, wherein in each of the modes of operation the driver output node is switched between two switching voltages, and the switching voltages are different in each of the modes.
In some examples, the first switch driver may be capable of selectively operating in any two or more of the following modes:
a first mode in which the two switching voltages are a high side voltage and a low side voltage;
a second mode in which the two switch voltages are a high-side voltage and a boosted high-side voltage, the boosted high-side voltage being greater than the high-side voltage by an amount substantially equal to the input voltage; and
a third mode in which the two switch voltages are a low side voltage and a boosted low side voltage, the boosted low side voltage being lower than the low side voltage by an amount substantially equal to the input voltage.
In the first mode, the first switch driver may be operable in two switch states, the switch states including:
a first state of the first mode, wherein the first input node is coupled to the first selectively boost node through a path that bypasses the first capacitor, the driver output node is connected to the first selectively boost node, and the first capacitor is connected between the first selectively boost node and the second input node; and
a second state of the first mode, wherein the second input node is coupled to the second selective boost node through a path that bypasses the second capacitor, the driver output node is connected to the second selective boost node, and the second capacitor is connected between the first selective boost node and the second input node.
If operable in the second mode, the first switch driver may be operable in two switch states, including:
a first state of the second mode, wherein the first input node is coupled to the first selective boost node through a path including a first capacitor in series, the driver output node is connected to the first selective boost node, and the second capacitor is connected between the first selective boost node and the second input node; and
A second state of the second mode, wherein the first input node is coupled to the first selective boost node through a path that bypasses the first capacitor, the driver output node is connected to the first selective boost node, and the first capacitor is connected between the first selective boost node and the second input node.
If operable in the third mode, the first switch driver may be operable in two switch states, including:
a first state of the third mode, wherein the second input node is coupled to the second selective boost node through a path that bypasses the second capacitor, the driver output node is connected to the second selective boost node, and the second capacitor is connected between the first selective boost node and the second input node; and
a second state of the third mode, wherein the second input node is coupled to the second selective boost node through a path including a second capacitor in series, the driver output node is connected to the second selective boost node, and the first capacitor is connected between the first selective boost node and the second input node.
The capacitor nodes may include first and second capacitor nodes for connection to opposite sides of the first capacitor and third and fourth capacitor nodes for connection to opposite sides of the second capacitor, and wherein the first capacitor node is connected to the first selective boost node and the fourth capacitor node is connected to the second selective boost node. In some examples, the second capacitor node and the third capacitor node may be connected to each other.
In some implementations, the switch path network may include:
a first input switch path for connecting a first input node to a first selective boost node;
a second input switch path for connecting the first input node to a second capacitor node;
a third input switch path for connecting the second input node to a third capacitor node;
a fourth input switch path for connecting the second input node to the second selective boost node.
In some examples, each of the first, second, third, and fourth input switch paths may include a respective FET switch.
In some examples, the switch path network may include a first output switch path for connecting the driver output node to a first selective boost node, and a second output switch path for connecting the driver output node to a second selective boost node. Each of the first output path and the second output path may include a plurality of FET switches in series. In some examples, there may be a bias controller for each of the first output switch path and the second output switch path. Each bias controller may be configured to control a bias voltage between two of the plurality of FETs of the associated first or second output switch path when the associated one of the first or second output switch path is non-conductive. In some examples, the bias controller for the first output switch path may include a transistor for connecting a midpoint node between the first capacitor and the second capacitor to an associated one of the first output switch path or the second output switch path selectively at a point between the two FETs.
In some examples, the first selective boost node and the second selective boost node may include output nodes of a first boost stage, and the switch driver circuit includes at least one additional boost stage. Each additional boost stage may include a first additional capacitor and a second additional capacitor. The switch path network may be operable such that the first and second additional capacitors are selectively connectable in series in or bypassed in a connection between the respective first and second voltage inputs to the respective first and second selective boost nodes of the additional boost stage. Each additional boost stage may be configured to receive voltages at first and second selective boost nodes of a previous boost stage at its first and second inputs, and the switch path network may be configured to selectively connect the output driver node to the selective boost node of a last of the additional boost stages.
In some examples, each additional boost stage may be further configured to receive a midpoint voltage from the previous boost stage at the third input node, the midpoint voltage being a midpoint between voltages at the first and second selective boost nodes of the previous boost stage. The additional boost stage may be operable to selectively connect a first additional capacitor between the first and third input nodes of that additional boost stage to charge the first capacitor, and to selectively connect a second additional capacitor between the third and second input nodes of that additional boost stage to charge the second additional capacitor.
The driver circuit may further include a controller configured to selectively control the first switch driver to controllably vary the operating mode and the driver output node to switch the duty cycle used between associated switching voltages having a certain duty cycle.
In some implementations, the driver circuit may further include a second switch driver for generating a second drive signal, the driver circuit configured to drive the load using the first drive signal and the second drive signal in a bridged load configuration. The second switch driver may have the same structure as the first switch driver and may be operable in the same manner as the first switch driver.
Aspects also relate to a driver circuit including a load configured to be driven by a first drive signal. In some examples, the load may be connected to the driver output node of the first switch driver via a series inductor. The load may be at least one of an audio output transducer and a haptic output transducer. In some examples, the load may be a piezoelectric transducer or a ceramic transducer.
Aspects also relate to an electronic device including a driver circuit of any of the implementations described herein.
In another aspect, there is provided a switch driver for generating a driving signal, the switch driver comprising:
a first voltage input node and a second voltage input node for receiving a first voltage input and a second voltage input;
a capacitor node for connection to a first capacitor and a second capacitor;
a driver output node for outputting a first drive signal; and
a switch path network;
the switch driver is operable in use to:
selectively driving the first selectively boosted node to a first voltage input or a first voltage input positively boosted by a voltage of a first capacitor;
selectively driving the second selectively boosted node to a second voltage input or a second voltage input negatively boosted by a voltage of a second capacitor; and
connecting the driver output node to a selected one of the first selective boost node and the second selective boost node;
wherein the first switch driver is selectively operable in a plurality of different modes of operation, wherein in each of the modes of operation the driver output node is switched between two switching voltages, and the switching voltages are different in each of the modes.
In another aspect, there is provided a switch driver for generating a drive signal within a defined output voltage range for driving a load, the switch driver comprising:
a first voltage input node and a second voltage input node for receiving respective high-side and low-side voltage inputs defining an input voltage;
a capacitor node for connection to at least one capacitor;
the output node is used for outputting a driving signal; and
a switch path network;
wherein the switch driver is operable to generate the driver signal by selectively operating in one of a plurality of different modes, wherein in each of the modes the driver output node switches between two switch voltages with a controlled duty cycle, wherein the switch voltages are different in each mode, and the switch voltages in each mode provide only a portion of the defined output voltage range.
Aspects also relate to a switch driver for driving a load, the switch driver comprising a switch network for switching a driver output node between different switch voltages and a capacitor node for connecting to a first capacitor and a second capacitor, wherein the switch network is operable such that the first capacitor is selectively connectable to provide a positively boosted switch voltage and the second capacitor is connectable to provide a negatively boosted switch voltage.
It should be noted that any feature described herein may be implemented in combination with any one or more of the other described features, unless explicitly indicated to the contrary or otherwise clearly incompatible therewith.
For a better understanding of the examples of the present disclosure, and to show more clearly how the examples may be implemented, reference will now be made, by way of example only, to the following drawings in which:
FIG. 1 shows an example of a conventional driving circuit;
FIG. 2 illustrates an output waveform of one of the switch drivers of FIG. 1;
FIG. 3 depicts an exemplary output waveform of a switch driver according to one embodiment;
FIG. 4 depicts one example of a switch driver according to one embodiment;
FIGS. 5a and 5b illustrate two states of operation of the switch driver of FIG. 4 in a first mode of operation;
FIGS. 6a and 6b illustrate two states of operation of the switch driver of FIG. 4 in a first mode of operation;
FIGS. 7a and 7b illustrate two states of operation of the switch driver of FIG. 4 in a third mode of operation;
FIG. 8 depicts an example of a drive circuit according to one embodiment;
FIG. 9 illustrates one example of an implementation of a switch driver in more detail;
FIG. 10 depicts an example of a switch driver with multiple boost stages according to one embodiment; and
Fig. 11 illustrates another example of a switch driver with multiple boost stages according to one embodiment.
The following description sets forth exemplary embodiments according to the present disclosure. Other exemplary embodiments and implementations will be apparent to those of ordinary skill in the art. Furthermore, one of ordinary skill in the art will recognize that various equivalent techniques may be applied as alternatives to or in combination with the embodiments discussed below, and that all such equivalents are to be considered as encompassed by the present disclosure.
Fig. 1 shows one example of a conventional driver circuit 100 for driving a load 101. In this example, load 101 is connected in a bridge-type load (BTL) configuration, and each side of the load is connected to a respective half-bridge switch driver 102-1 and 102-2 (which may be collectively or individually referred to as switch driver 102). However, it will be appreciated that a single ended drive circuit may be used in some implementations, wherein one side of the load is connected to the switch driver 102 and the other side of the load is coupled to a defined voltage, such as ground, in use.
Each switch driver 102 includes a switch 103a and 103b, which may typically comprise a MOSFET, for selectively connecting the output node 104 to either the high side voltage VH or the low side voltage VL. In some examples, the high side voltage VH may be a supply voltage and the low side voltage may be ground.
The switches 103a and 103b of the switch driver 102 are controlled by switching signals generated by respective modulators 105-1 and 105-2 (which may be collectively or individually referred to as modulators 105) based on an input signal Sin, which may be, for example, an input audio signal. Those skilled in the art will appreciate that modulator 105 may generate PWM or PDM switching signals based on the input signal.
Fig. 1 also shows that the output path from the switch driver 102-1 to the load 101 includes a series inductance 106. A series inductor 106 may be included to suppress switching fluctuations in the output voltage and present a high impedance at the output node 104 of FET switches 103a and 103b at and above the switching frequency while allowing current to flow to the load 101 in the signal band of interest (e.g., at audio frequencies).
As described above, the sizing of the inductor may be limiting in some cases, particularly with respect to peak currents that may flow unsaturatedly.
The skilled person will appreciate that the rate of change of current through the inductor (di/dt) is related to the voltage V across the inductor and the inductance L L The correlation is as follows:
di/dt ＝ V L l equation (1)
Thus, in general, a greater inductance may be required to limit the maximum current change rate.
In the example of the conventional driver circuit of fig. 1, the high side voltage VH and the low side voltage VL are selected to provide a specifically defined output voltage range for each output switch circuit 102. That is, the switch driver 102-1 is operable to provide an average output voltage over time in a range of voltages at or just above VL (by connecting the output node 104 to VL during substantially the entire duty cycle) to voltages at or just below VH (by connecting the output node 104 to VH during substantially the entire duty cycle).
Fig. 2 shows an example of a switching waveform at the output node 104 of the switch driver 102-1 along with an average demand voltage 201 (i.e., a desired output signal). The output node 104 switches between the switching voltages VH and VL having a duty ratio (typically expressed in proportion to the time taken to connect to the high-side voltage VH) that varies according to the demand voltage 201.
When the output node 104 switches between the switching voltages VH and VL, the inductor current will ramp up or down. The amount of fluctuation in the inductor current will depend on the duty cycle of the switching voltage and on the difference between the switching voltages VL and VH. The relatively high voltage difference between VL and VH may thus result in a larger magnitude of current ripple, which may be undesirable.
Embodiments of the present disclosure relate to a driver circuit adapted to drive a transducer, the driver circuit comprising at least one switch driver for generating a drive signal in a defined output voltage range at an output node, wherein the switch driver is operable in a plurality of different modes of operation, wherein in each of the different modes of operation the output node switches between two voltages providing only a part of the defined output voltage range, that is, the voltage range between the two switch voltages in a given mode forms a subset of the defined voltage range.
The switch driver thus switches between two defined switch voltages with a controlled duty cycle to provide a desired average output voltage, wherein the average output voltage is variable within a defined voltage range between a high voltage VH and a low voltage VL. However, rather than merely switching between these peak high and low voltage levels of the output range as discussed with respect to fig. 1 and 2, the switch drivers of embodiments of the present disclosure switch between two switch voltages that form a subset or only a portion of the entire output range. Thus, the output node switches between two switching voltages that differ from each other by less than the entire output range.
In practice, a switch driver may be considered to operate under a variable voltage rail, where the voltage rail is controllably changed in different modes of operation to provide different ranges of operation.
Fig. 3 illustrates this principle. Fig. 3 illustrates a switching waveform and average voltage requirement 301 at an output node of a switching driver according to one example. In this example, the average voltage requirement is the same as that depicted in fig. 2, and may vary throughout the output range between the low voltage VL and the high voltage VH. However, in this example, the switch driver is capable of operating in different modes. In one mode of operation, the output node may be switched between the low voltage VL and the first intermediate voltage VA. In another mode of operation, the output node may be switched between the first intermediate voltage VA and the second intermediate voltage VB. In yet another mode of operation, the output node may be switched between the second intermediate voltage VB and the high voltage VH.
When the average voltage requirement is lower than the intermediate voltage VA, the output stage may operate in a mode that switches between VL and VA. When the average voltage demand is greater than the first intermediate voltage VA but less than the second intermediate voltage, the output node may switch between VA and VB, and if the voltage demand is greater than VB, the switch driver may operate in the mode to switch the voltage at the output node between VB and the high voltage VH. In each case, the duty cycle is appropriately controlled to provide the desired average voltage.
Operating in this way means that the voltage difference between the two switching voltages used at any time is reduced compared to the example of fig. 2. This advantageously reduces maximum voltage fluctuations in use.
FIG. 3 depicts providing the entire output range between VL and VH through three different modes of operation. In at least some embodiments, it may be desirable for the voltage ranges of each mode of operation, i.e., the voltage differences between the associated two switching voltages VL and VA, VA and VB, or VB and VH, to be the same as each other. However, in other implementations, there may be a different number of modes of operation across the entire output range of the switching output stage, e.g., in some implementations, there may be only two modes of operation or there may be more than three modes of operation.
Fig. 4 depicts one example of a switch driver 401 according to one embodiment. The switch driver 401 includes first and second inputs for connection to a high-side voltage VinH and a low-side voltage VinL (e.g., positive supply voltage and ground), respectively. It will be appreciated that reference to high and low side voltages (or sometimes only high and low voltages) will indicate that the high side voltage is relatively more positive than the low side voltage, and does not imply the magnitude of such voltages. The difference between the low-side voltage VinL and the high-side voltage VinH defines the input voltage Vin of the output stage. The switch driver 401 also has a driver output node 402 for outputting a drive signal Vout.
The switch driver 401 further comprises first and second capacitors 403H and 403L and a switch path network. The switched path network is arranged such that the first and second capacitors 403H and 403L are selectively chargeable by the input voltage Vin and, in at least one mode of operation, are selectively coupled in series with one of the voltage inputs VinH or VinL to the output node 402 so as to facilitate an output voltage, for example, to provide a positive or negative boost of the relevant voltage input. Each switch path includes one or more switches, which may typically be MOSFETs, as will be described in more detail below.
One side of the first capacitor is connected to the first node N1. The switch path network includes a switch path SWHA for selectively connecting the first input terminal to the first node N1 through a path bypassing the first capacitor 403H so that the first node can be driven to be substantially equal to the high-side voltage VinH. The switch path SWHB is arranged to selectively connect the first input to the first node N1 via a path comprising a first capacitor 403H in series, such that the voltage on this capacitor contributes to the voltage at node N1. Node N1 may thus be considered a selective boost node that may be selectively boosted to a voltage higher than the high-side input voltage.
Similarly, one side of the second capacitor 403L is connected to the second node N2, and the switch path network comprises a switch path SWLA for selectively connecting the second input to the second node N2 bypassing the second capacitor 403L, and a switch path SWLB for connecting the second capacitor 403L in series between the second input and the second node N2, such that the voltage on the second capacitor 403L contributes to the voltage at the node N2, in this case by reducing said voltage or negatively boosting said voltage. Node N2 may thus be considered a second selectively boosted node that may be selectively controlled to a voltage equal to or lower than the low-side voltage VinL.
Output switch paths SWO1 and SWO2 are provided to allow driver output node 402 to be selectively connected to either first selective boost node N1 or second selective boost node N2.
The switch path network is also operable to allow the first and second capacitors 403H and 403L to be charged by the input voltage Vin (i.e., the difference between VinH and VinL). In the embodiment of fig. 3, the capacitors are connected to a common midpoint node N3, and thus the first capacitor 403H may be selectively connected to the second input or the second capacitor 403L may be selectively connected to the first input using switch paths SWHB and SWLB, as will be discussed in more detail below. However, in other arrangements, there may be additional switching paths for charging the capacitor if desired, at the expense of additional circuitry.
It will be appreciated that the switch driver may be implemented as an Integrated Circuit (IC), but in some embodiments the first and second capacitors may not include integrated components and may be separate components that are connected to the IC in use, i.e. the capacitors may be off-chip. The first capacitor 403H may thus be connected between a first capacitor node and a second capacitor node, and the second capacitor may be connected between a third capacitor node and a fourth capacitor node (not separately identified in fig. 4) that may be connected to appropriate contacts of the IC for connection to an external capacitor.
The switch driver 401 of fig. 4 may be capable of operating in three different modes of operation. In a first mode of operation, the output node 402 may be switched between VinH and VinL to provide an average output voltage in a range between VinL and VinH. The first mode may be considered a non-boost operating mode. In the second mode of operation, the output node 402 may switch between VinH and vinh+ (VinH-VinL) to provide an average output voltage in a range between VinH and 2VinH-VinL (i.e., a voltage range higher than VinH by Vin (=vinh-VinL)). The second mode may be considered a positive boost operating mode. In a third mode of operation, the output node 402 may switch between VinL and VinL- (VinH-VinL) in order to provide an average output voltage in a range between 2VinL-VinH and VinL (i.e., a voltage range lower than VinL by Vin). The third mode may be considered a negative boost operating mode.
The output voltage of the switch driver can be controlled to have an average value that can take any value within a voltage range equal to three times the input voltage Vin by selectively operating in an appropriate operation mode. Each of the operating modes may provide an average output voltage in a different sub-range, where each sub-range is equal in magnitude to the input voltage Vin.
Fig. 5a and 5b, fig. 6a and 6b, and fig. 7a and 7c illustrate operation in a first mode, a second mode, and a third mode, respectively, of an example in which the switch driver is connected to receive the supply voltage VS at a first input and to ground (i.e., 0V) at a second input.
Fig. 5a and 5b illustrate operation in the first mode. In this first mode, the switch driver may be controlled to assume a first state to provide a voltage at the output node 402 equal to +VS, and a second state to provide a voltage at the output node 402 equal to 0V.
Fig. 5a shows that in the first state of the first mode, the switches of switch paths SWHA and SWO1 may be closed to connect the first input to a selective boost node N1, which is connected to the driver output node 402, such that in this example the output voltage Vout is equal to +vs. In addition, in this first state, the switch of the switch path SWLB is closed to connect the first capacitor 403H between the first voltage input terminal and the second voltage input terminal so as to charge the first capacitor to the voltage VS. The other switching paths are open and thus in effect float the second capacitor 403L and will maintain its charge.
Fig. 5b shows that in said second state of said first mode, the switches of the switch paths SWLA and SWO2 can be closed to connect the second input to a second selective boost node N2, which is connected to the driver output node 402, so that in this example the voltage at the driver output node is equal to 0V. In addition, in this second state, the switch of the switch path SWHB is closed to connect the second capacitor 403L between the first voltage input terminal and the second voltage input terminal so as to charge the second capacitor to the voltage VS. The other switching paths are turned off and thus, in effect, the first capacitor 403L is floated and will maintain its previous charge.
In operation in the first mode of operation, the switch driver may thus be controlled to alternate between the first state and the second state with an appropriate duty cycle to provide an output voltage having an average value in the range of 0V to VS via the duty cycle.
Fig. 6a and 6b illustrate operation in the second mode. In this second mode, the switch driver may be controlled to assume a first state to provide a voltage at the output node 402 equal to +2vs, and a second state to provide a voltage at the output node 402 equal to +vs.
Fig. 6a shows that in the first state of the second mode, the switch of switch path SWHB may be closed to connect the first input to the selective boost node N1 node via the first capacitor 403H, and the switch of switch path SWO1 is closed to connect the first selective boost node to the driver output node 402. In use, the first capacitor 403H will be charged to the input voltage VS during a different state (i.e., one of the second state of the second mode or one of the other modes of operation). In this first state of the second mode, the first capacitor is connected with its positive plate coupled to the selective boost node N1 and thus the output node 402 such that the voltage Vout at the output node is equal to +2vs.
In the first state of the second mode, the switch of the switch path SWLA is also closed to connect the second capacitor 403L between the first voltage input and the second voltage input in order to charge the second capacitor to the voltage VS.
Fig. 6b shows that in said second state of said second mode, the switches of the switch paths SWHA and SWO1 can be closed to connect the first input to a first selective boost node N1, which is connected to the output node 402, so that in this example the output voltage is equal to +vs. In addition, in this second state, the switch of the switch path SWLB is closed to connect the first capacitor 403H between the first voltage input terminal and the second voltage input terminal, so as to (re) charge the first capacitor to the voltage VS. The other switching paths are turned off and thus, in effect, the second capacitor 403L is floated and will maintain its previous charge.
Fig. 7a and 7b illustrate operation in the third mode. In this third mode, the switch driver may be controlled to assume a first state to provide a voltage at the output node 402 equal to 0V, and a second state to provide a voltage at the output node 402 equal to-VS.
Fig. 7a shows that in the first state of the third mode, the switches of switch paths SWLA and SWO2 can be closed to connect the second input to a second selective boost node N2, which is connected to the output node 402, so in this example the output voltage is equal to 0V. In addition, in this first state, the switch of the switch path SWHB is closed to connect the second capacitor 403L between the first voltage input terminal and the second voltage input terminal so as to charge the first capacitor to the voltage VS. The other switching paths are turned off and thus the first capacitor 403H is effectively floated and will maintain any previous charge.
Fig. 7b shows that in the second state of the third mode, the switch of switch path SWLB may be closed to connect the second input to the second selective boost node via a second capacitor 403L, and switch path SWO2 is closed to connect the second selective boost node to the driver output node 402. As described above, in use, the second capacitor 403L is charged to an input voltage, in this example equal to VS, in one of the other states (i.e. one of the states of the first state or one of the other modes of operation of the third mode) and in this second state of the third mode, the second capacitor is connected with its negative plate coupled to the second selective boost node N2 and hence the output node 402 such that the voltage Vout at the output node is equal to-VS.
In this second state of the third mode, the switch of the switch path SWHA is also closed to connect the first capacitor 403H between the first voltage input and the second voltage input in order to charge the first capacitor to the voltage VS.
It will thus be appreciated that the switch driver 401 is capable of operating in three different modes of operation to provide an output voltage that is variable within a voltage range equal to 3VS (i.e., between a low voltage-VS and a high voltage +2vs). This can be considered as an output voltage symmetrical about the midpoint +0.5vs.
It will be appreciated that providing the same output voltage range using the conventional driver depicted in fig. 1 would require the input voltages VH-VL to be equal to 3VS. Embodiments of the present disclosure may thus use lower input voltages than the conventional approach of fig. 1 to provide a given output drive voltage range, thus reducing supply voltage requirements.
In each of the second and third modes of operation, one of the capacitors 403H or 403L is coupled in series with the output node 402 in one of the states. Capacitors 403H and 403L may be selected to have the following capacitance values: sufficient to allow the required load current without any significant voltage drop during the switching cycle. The capacitance of the capacitor 403H or 403L may also be selected to provide a suitably low effective impedance (considered as a switched capacitor resistor for driving the load). In some cases, where the load is primarily capacitive, the capacitance of capacitor 403H or 403L may be relatively large compared to the capacitance of load 101.
It will be noted that in this first mode of operation, in the first state, the output node 402 is connected to the supply voltage VS through the switches of the associated switching path, and the capacitors 403H and 403L are not connected in series between the first input and the output node, and thus the output voltage is actually provided directly by the supply voltage VS. This is optimal for highly reactive load impedances where peak currents occur at or near voltage zero crossings.
In each of the operating modes, the first capacitor and the second capacitor are charged to the same voltage, which in this example is an input voltage equal to VS, in an alternating state of the duty cycle. The first and second capacitors 403H and 403L are not used to contribute to the output voltage in this first mode of operation, however, operation in the first mode pre-charges the capacitors to the correct voltage level for operation in the other modes of operation. Likewise, in the second mode of operation, the second capacitor 403L is not used to contribute to the output voltage but is pre-charged to be ready for use in the third mode of operation, and in the third mode of operation, the first capacitor 403H is not used to contribute to the output voltage but is pre-charged to be ready for use in the second mode of operation. The switch driver can thus easily switch between different modes of operation simply by controlling which switches of the switch path are open and closed.
It will be noted that the first capacitor 403H is therefore only used to facilitate the output voltage in the second mode to positively boost the voltage at the selective boost node N1 to +2vs, and the second capacitor is only used in the third mode of operation to negatively boost the voltage at the second selective boost node N2 to-VS. If either of these modes of operation is not required in a particular implementation, the relevant one of the first or second capacitors 403H or 403L may be omitted and the output stage operated in only the other two modes.
Referring again to fig. 4, to control the switching operation to implement the different modes of operation, the driver circuit may include a controller 404. The controller may receive the input signal Sin and determine an appropriate operation mode based on the input signal Sin and generate a switch control signal Scon for controlling the relevant switches of the switch path. The controller 404 may generate the switch control signal to alternate between the associated first state and second state at an appropriate duty cycle (in view of switching the switching voltage of the output node between the associated modes of operation) to provide the desired average output voltage.
The driving circuit may be implemented in a single ended configuration using a switch driver such as that depicted in fig. 4, i.e. one switch driver is configured to drive one side of the load and the other side of the load is tied to a fixed voltage, which may be equal to +vs/2, for example.
However, in some implementations, the driver circuit may include two switch drivers arranged to drive the load in the BTL configuration. Fig. 8 depicts a drive circuit 800 having respective first and second switch drivers 401-1 and 401-2 for driving a load in a BTL arrangement, according to one embodiment. Each of the switch drivers 401-1 and 401-2 may be a switch driver such as that depicted in fig. 4. Each of the switch drivers 401-1 and 401-2 may thus include a respective first capacitor and second capacitor (which allows the operating mode and duty cycle of the switch drivers 401-1 and 401-2 to be controlled independently of each other).
In the example of fig. 8, two switch drivers 401-1 and 401-2 are provided with the same voltage inputs VinH and VinL as each other (and thus each of the switch drivers 401-1 and 401-2 receives the same input voltage). This arrangement is operable to generate a drive voltage across the load 101 up to a maximum magnitude of substantially 3 (VinH-VinL) (i.e., three times the input voltage Vin) by: the switch driver on one side of the load is operated in the second mode to provide an output voltage of 2VinH-VinL, while the switch driver on the other side of the load is operated in the third mode to provide an output voltage of 2 VinL-VinH.
FIG. 8 depicts that each switch driver 401-1 and 4021-2 may be controlled by a respective controller 404-1 and 404-2, but it will be appreciated that at least some of the functionality of the controllers 404-1 and 404-2 may be shared.
Referring again to fig. 4, each of the switch paths of the switch driver 401 may include at least one suitable FET. In some applications, each switch path may include a single FET switch. However, in some applications, at least some of the switching paths may be implemented by two or more FETs in series, particularly for any switching path that may experience higher voltage stresses in use in the off or open state that may be greater than the voltage tolerance of a single FET.
For example, referring back to fig. 5a and 5b, in the first state of the first mode, the voltage at the selective boost node N1 is +vs, the voltage at the midpoint node N3 is 0V, and the voltage at the selective boost node N2 is equal to-VS (because the positive plate of the second capacitor 403L is coupled to 0V). The magnitude of the voltage difference across open switch paths SWHB and SWLA is thus equal to VS, but the magnitude of the voltage difference across switch path SWO2 is 2VS. In the second state of the first mode, the negative plate of the first capacitor 403H is coupled to the input voltage VS, and thus the voltage at node N1 is equal to +2vs, while the voltage at node N3 is +vs and the voltage at node N2 is 0V. In this state, the magnitude of the voltage difference across non-conductive switch paths SWHA and SWLB is equal to VS, but the magnitude of the voltage difference across switch path SWO1 is 2VS.
In the second mode of operation depicted in fig. 6a and 6b, the voltage at the selective boost node N1 is +2vs in the first state and +vs in the second state, the voltage at the selective boost node N2 is 0V in the first state and-VS in the second state, and the voltage at the midpoint node N3 is +vs in the first state and 0V in the second state. In this mode of operation, the magnitude of the voltage difference across switch path SWO2 is thus equal to 2VS, while the magnitude of the voltage difference across the other switch paths in the two states is at most equal in magnitude to VS. Likewise, in the third mode of operation depicted in fig. 7a and 7b, the voltages at nodes N1, N2 and N3 vary in the same manner as in the second mode, but in this mode the switch path SWO2 remains closed. The voltage difference across switch path SWO1 is thus equal in magnitude to 2VS, while the voltage difference across the other switch paths in both states is at most equal in magnitude to VS.
Switch paths SWO1 and SWO2 (which may be referred to as output switch paths) connected to output node 402 may therefore experience greater voltage stress in the off state than other switch paths.
In some implementations, the switch driver may be implemented using FETs with drain-source voltage tolerances that are greater than the magnitude of the input voltage, e.g., the breakdown voltage may be greater than VS in the examples described above. However, it may not be practical or convenient to implement FETs with a voltage tolerance equal to 2 VS. For example, in some applications, the supply voltage VS may be around 20V, and FETs rated for operation at 20V may be implemented, but providing FETs with a voltage tolerance of 40V may not be practical.
In this example, the switch paths SWHA, SWHB, SWLA, SWLB can each be implemented using a single suitable FET. However, in use, when in the off state, the voltage difference across output switch paths SWO1 and SWO2 may exceed this voltage tolerance. In this case, the output switch paths SWO1 and SWO2 of the switch driver may be implemented by two or more FETs in series, as depicted in fig. 9.
FIG. 9 shows that the output switch path SWO1 may be implemented by two FETs 901H-1 and 902H-2 in series, and that the switch path SWO1 may be implemented by two FETs 901L-1 and 902L-2 in series. In use, when the associated switch path is in the off state, a voltage difference of magnitude 2VS will be applied across the two FETs in series, and each of the FETs in series connection may experience a voltage stress of magnitude VS.
In some applications, to ensure that the two FETs across the output path share voltage stress correctly, the voltage at the midpoint between the two FETs of the associated output path (i.e., the node between 901H-1 and 901H-2 and the node between 901L-1 and 901L-2, respectively) may be controlled to a desired voltage when the associated output path is in the off state. The voltages at such nodes may be controlled by a bias controller such that the voltage stress across each of FETs 901H-1 and 901H-2 or FETs 901L-1 and 901L-2 is substantially equal. The voltages at these nodes of the associated output paths may be controlled in a variety of ways by a suitable bias controller, but in some embodiments, transistors 902H and 902L may be connected between midpoint node N3 and the respective nodes between FETs of output switch paths SWO1 and SWO 2. In use, when the associated switch path is in an off state, either transistor 902H or 902L may be turned on. This will cause the node between the FETs of output switch path SWO1 or SWO2 to be regulated to a voltage differing from the output voltage by VS, thus ensuring that the magnitude of the voltage stress across each of FETs 901H-1 and 901H-2 or FETs 901L-1 and 901L-2 is substantially VS. The transistors 902H and 902L may be implemented as relatively small devices because they only need to handle a relatively small amount of current during transitions.
Fig. 9 shows that the other switching paths SWHA, SWHB, SWLA, SWLB are each implemented using a single FET, and thus the implementation of fig. 9 provides the desired switching path using eight FETs.
Referring again to fig. 4, as discussed above, the switch driver 401 is capable of operating in three modes. In a first mode, which may be considered a non-boost mode of operation, capacitors 403H and 403L are not used to contribute to the voltage at output node 402, and output node 402 is alternately connected to either the high-side voltage VinH or the low-side voltage VinL in a similar manner to a conventional switch driver. In a second mode of operation (second mode), which may be considered a positive boost mode of operation, the voltage at the selective boost node N1 may be alternately boosted to vinh+vin, or connected only to VinH. In the third mode, the voltage at node selective boost node N2 may alternately be boosted or changed to VinL-Vin, or connected only to VinL.
Capacitors 402H and 402L along with switch paths SWHA, SWHB, SWLA and SWLB can thus be considered to collectively provide an initial selective boost stage of the switch driver, with switch paths SWO1 and SWO2 providing an output path stage.
In some embodiments, the switch driver may include one or more additional selective boost stages to allow for another variation in the voltage supplied to the output node, and thus allow for more modes of operation and/or a wider output voltage range at a given input voltage. The switch driver may thus be a multi-stage switch driver.
In some examples, one or more additional boost stages may have the same general operational structure as described with reference to fig. 4 and 5 a-7 b.
Fig. 10 illustrates an example of a multi-stage switch driver 1000 with multiple selective boost stages according to one embodiment. Fig. 10 shows an example with two selective boost stages 1001 and 1002 and an output path stage 1003, but it will be appreciated that one or more other selective boost stages may be added in other implementations.
In this implementation, the first selective boost stage 1001 has similar components identified by the same reference numerals as discussed above with respect to fig. 4. The second selective boost stage 1002 has similar components identified by similar references suffixed with a "2".
In the example of fig. 10, the voltages at the selective boost nodes N1 and N2 of the first selective boost stage 1001 are supplied as the respective high-side and low-side voltages VH2 and VL2 of the subsequent selective boost stage 1001. Assuming that the capacitors 403H and 403L of the first stage 1001 are each charged to the input voltage Vin (=vinh-VinL) and that these capacitors are connected in series between N1 and N2, it will be appreciated that the voltage difference between VH2 and VL2 will be equal to 2Vin in use.
The switch driver 1000 of fig. 10 is operable to provide the same outputs of the first, second and third modes described above, but is additionally operable to provide additional boost modes, which may be referred to as positive and negative double boost modes.
To provide an output of the first mode (i.e., the non-boost operating mode), the first stage 1001 and the output stage 1003 may operate together in the same manner as the two states of the first mode described with respect to fig. 5a and 5b, while the second stage 1002 is switched in both of the same two states at the same time. This will alternately connect the output node 402 to the voltage inputs VinH and VinL while charging the capacitors 403H and 403L of the first stage to the input voltage Vin and the capacitors 403H-2 and 403L-2 of the second stage to 2Vin.
To provide an output of the second mode, the first stage 1001 and the output stage 1003 may be operated in two states of the second mode described with reference to fig. 6a and 6 b. This provides the desired voltage level at node N1. Switch path SWHA-2 may remain closed to connect node N1 to output node 402 in order to provide the desired output voltage. Switch path SWLB-2 may also be closed to keep capacitor 403H charged. Similarly, to provide the output of the third mode, the first stage 1001 and the output stage 1003 may operate in both states of the third mode described with reference to fig. 7a and 7b to provide the desired voltage level at node N2, with the switch path SWL2-2 of the second stage closed and the switch path SWHB-2 closed to charge the capacitor 403L 2.
To provide an additional double boost mode, the first stage 1001 may operate in two states of the second mode or the third mode while the second stage 1002 is operated in the same state. For positive double boost mode, the output node will therefore vary between vinh+vin and vinh+3vin. For negative double boost mode, the output node will therefore vary between VinL-Vin and vin+3vin.
Thus, if the input voltages VinH and VinL are the positive supply voltages VS and ground 0V, respectively, the switch driver 1000 of FIG. 10 may be selectively operable to provide outputs in the range +4VS to +2VS, +2Vs to +VS, +VS to 0V, 0V to-VS, and-VS to-3 VS.
Additional boost stages may be included as needed to allow additional boosting of the output voltage. However, it will be appreciated that the effective input voltage of each stage is twice the input voltage of the preceding stage, and that the voltage range of the additional boost mode is thus doubled at each stage. This may mean that for some modes of operation, the difference between the switching voltages in the relevant modes may be relatively high, wherein the associated problems of the switches result in relatively high current rates. Moreover, the voltage stored by the capacitor of the later boost stage may be relatively large, which may result in relatively large voltage stresses for some components.
Fig. 11 illustrates another example of a switch driver 1100 with multiple selective boost stages. Fig. 11 shows an example with two selective boost stages 1101 and 1102 and an output path stage 1003, but it will be appreciated that one or more other selective boost stages may be added in other implementations.
The switch driver 1100 has similar components as the switch driver 1000 discussed with respect to fig. 10, but in the embodiment of fig. 11, the second stage receives the voltage at node N3 of the first stage 1101 in addition to the voltages VH2 and VL2 from the selective boost nodes N1 and N2 of the first stage being supplied as inputs to the second stage. The voltage at node N3 is the midpoint voltage VM between the voltages of the selective boost nodes N1 and N2, and is therefore always lower than the voltage at node N1 by the voltage Vin and higher than the voltage at node N2 by the voltage Vin. The midpoint voltage VM is used to selectively charge the capacitors 403H and 403L such that these capacitors are charged to a voltage equal to Vin.
The switch driver 1000 of fig. 10 is operable to provide the same outputs of the first, second, and third modes described above, but is additionally operable to provide additional boost modes in which the voltage may be additionally positively or negatively boosted by a voltage equal to the magnitude of Vin.
Thus, if the input voltages VinH and VinL are the positive supply voltages VS and ground 0V, respectively, the switch driver 1100 of FIG. 11 may be selectively operable to provide outputs in the range +3VS to +2VS, +2Vs to +VS, +VS to 0V, 0V to-VS, and-VS to-2 VS.
Additional boost stages may be included as needed to allow additional boosting of the output voltage.
Thus, in general, embodiments of the present disclosure relate to a switch driver adapted to drive an output transducer, the switch driver being operable to provide a drive signal having an average voltage within a defined output voltage range (e.g., between a low side voltage VL and a high side voltage VH). The switch driver is capable of operating in a plurality of different modes, wherein in each of the modes the driver output node switches between two switching voltages with a controlled duty cycle, wherein the switching voltages are different in each mode, and the switching voltages in each mode provide only a portion, i.e. a subset, of the defined output voltage range.
In at least some embodiments, the switch driver may include at least one selective boost stage having first and second inputs for receiving a high side input voltage and a low side input voltage and including first and second capacitors and a switch path network. The switch path network may include a switch path for connecting the first capacitor in series between the first input and the first selective boost node, and a switch path for connecting the first input directly to the first selective boost node (i.e., not via the first capacitor or the second capacitor). The first circuit mode may thus be selectively driven to a high side input voltage substantially equal to the high side input voltage or boosted by the voltage of the first capacitor.
The switch path network may also include a switch path for connecting the second capacitor in series between the second input and the second selective boost node, and a switch path for connecting the second input directly to the second selective boost node (i.e., not via the first capacitor or the second capacitor). The second selective boost may thus be selectively driven to a low side input voltage substantially equal to the low side input voltage or negative boosted by the voltage of the second capacitor.
The switch driver may further include an output stage having an output path for selectively connecting the output node of the driver to either the first circuit node or the second circuit node of the selective boost stage.
In each of the modes of operation, the switch driver is controllable to change between at least a first state in which the first capacitor is charged and a second state in which the second capacitor is charged to provide a different switching voltage.
At least some embodiments relate to a switch driver for switching a driver output node between switch voltages, wherein the switch driver includes a first capacitor and a second capacitor that may each be selectively charged to a defined voltage level, which may be, for example, equal to an input voltage. The switch driver is configured such that the first capacitor and the second capacitor are selectively connectable to provide a voltage boost for the switch voltage. In at least some embodiments, a first capacitor can be selectively connected to provide positive voltage boosting, i.e., boosting the associated switching voltage to a higher voltage, and a second capacitor can be selectively connected to provide negative voltage boosting, i.e., boosting the associated switching voltage to a lower voltage. Embodiments are thus also related to a switch driver circuit comprising a first capacitor and a second capacitor for positive voltage boosting and negative voltage boosting, respectively.
Embodiments also relate to a driver circuit comprising two switch drivers configured to provide an output drive signal for driving a bridged load.
As mentioned, the switch driver may be adapted to drive the output transducer. In some implementations, the output transducer may be an audio output transducer, such as a loudspeaker or the like. The output transducer may be a haptic output transducer. In a certain implementation, the output transducer may be driven in series with an inductor, i.e. there may be an inductor in the output path between the output node of the switch driver and the load. In some implementations, the transducer may be a piezoelectric or ceramic transducer.
Implementations may be implemented as an integrated circuit. Embodiments may be implemented in a host device, particularly a portable and/or battery powered host device, such as a mobile computing device (e.g., a laptop, notebook, or tablet computer), or a mobile communication device, such as a mobile phone (e.g., a smartphone). The device may be a wearable device, such as a smart watch. The host device may be a game console, a remote control device, a home automation controller or household appliance, a toy, a machine such as a robot, an audio player, a video player. It will be appreciated that embodiments may be implemented as part of a system provided in a household appliance or in a vehicle or interactive display. A host device incorporating the above embodiments is also provided.
The skilled person will appreciate that some aspects of the above described apparatus and method (e.g. aspects of controlling the switch control signals to implement different modes) may be embodied as processor control code, for example, on a non-volatile carrier medium such as a magnetic disk, CD-ROM or DVD-ROM, a programmed memory such as read only memory (firmware) or on a data carrier such as an optical or electrical signal carrier. For some applications, the implementation may be implemented on a DSP (digital signal processor), an ASIC (application specific integrated circuit), or an FPGA (field programmable gate array). Thus, the code may comprise conventional program code or microcode, or code for example, to set up or control an ASIC or FPGA. The code may also include code for dynamically configuring a reconfigurable device, such as a reconfigurable array of logic gates. Similarly, the code may include code for a hardware description language (such as Verilog TM Or VHDL (very high speed integrated circuit hardware description language)). The skilled person will appreciate that the code may be distributed between a plurality of coupled components in communication with each other. The implementation may also be implemented using code running on a field (re) programmable analog array or similar device to configure analog hardware, as appropriate.
It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. The word "comprising" does not exclude the presence of elements or steps other than those listed in a claim, and "a" or "an" does not exclude a plurality, and a single feature or other element may fulfill the functions of several elements recited in the claims. Any reference numerals or signs in the claims shall not be construed as limiting their scope.

Claims (23)

1. A driver circuit comprising a first switch driver for generating a first drive signal, the first switch driver comprising:
a first input node and a second input node for connection to respective high-side and low-side voltages defining an input voltage;
a capacitor node for connection to a first capacitor and a second capacitor;
a driver output node for outputting the first drive signal; and
a switch path network;
Wherein the switch path network is configured such that, in use:
each of the first capacitor and the second capacitor is selectively connectable in series between the first input node and the second input node to charge to the input voltage;
the first input node can be selectively coupled to a first selective boost node through a path including the first capacitor in series or through a path bypassing the first capacitor;
the second input node can be selectively coupled to a second selective boost node through a path including the second capacitor in series or through a path bypassing the second capacitor; and
the driver output node is selectively coupleable to the first selectively boost node or the second selectively boost node;
wherein the first switch driver is selectively operable in a plurality of different modes of operation, wherein in each of the modes of operation the driver output node switches between two switching voltages, and the switching voltages are different in each of the modes.
2. The driver circuit of claim 1, wherein the first switch driver is selectively operable in any two or more of the following modes:
A first mode in which the two switching voltages are the high side voltage and the low side voltage;
a second mode in which the two switch voltages are the high-side voltage and a boosted high-side voltage that is greater than the high-side voltage by an amount substantially equal to the input voltage; and
a third mode in which the two switch voltages are the low side voltage and a boosted low side voltage that is lower than the low side voltage by an amount substantially equal to the input voltage.
3. The driver circuit of claim 2, wherein in the first mode, the first switch driver is operable in two switch states, the two switch states comprising:
a first state of the first mode, wherein the first input node is coupled to the first selectively boost node through the path bypassing the first capacitor, the driver output node is connected to the first selectively boost node, and the first capacitor is connected between the first selectively boost node and the second input node; and
a second state of the first mode, wherein the second input node is coupled to the second selectively boost node through the path bypassing the second capacitor, the driver output node is connected to the second selectively boost node, and the second capacitor is connected between the first selectively boost node and the second input node.
4. The driver circuit of claim 2, wherein in the second mode, the first switch driver is operable in two switch states, the two switch states comprising:
a first state of the second mode, wherein the first input node is coupled to the first selectively boost node through the path including the first capacitor in series, the driver output node is connected to the first selectively boost node, and the second capacitor is connected between the first selectively boost node and the second input node; and
a second state of the second mode, wherein the first input node is coupled to the first selectively boost node through the path bypassing the first capacitor, the driver output node is connected to the first selectively boost node, and the first capacitor is connected between the first selectively boost node and the second input node.
5. The driver circuit of claim 2, wherein in the third mode, the first switch driver is operable in two switch states, the two switch states comprising:
A first state of the third mode, wherein the second input node is coupled to a second selective boost node through the path bypassing the second capacitor, the driver output node is connected to the second selective boost node, and the second capacitor is connected between the first selective boost node and the second input node; and
a second state of the third mode, wherein the second input node is coupled to the second selective boost node through the path including the second capacitor in series, the driver output node is connected to the second selective boost node, and the first capacitor is connected between the first selective boost node and the second input node.
6. The driver circuit of claim 1, wherein the capacitor nodes comprise first and second capacitor nodes for connection to opposite sides of the first capacitor and third and fourth capacitor nodes for connection to opposite sides of the second capacitor, and wherein the first capacitor node is connected to the first selective boost node and the fourth capacitor node is connected to the second selective boost node.
7. The driver circuit of claim 6, wherein the second capacitor node and the third capacitor node are connected to each other.
8. The driver circuit of claim 6, wherein the switch path network comprises:
a first input switch path for connecting the first input node to the first selective boost node;
a second input switch path for connecting the first input node to the second capacitor node;
a third input switch path for connecting the second input node to the third capacitor node;
a fourth input switch path for connecting the second input node to the second selectively boost node.
9. The driver circuit of claim 6, wherein each of the first, second, third, and fourth input switch paths includes a respective FET switch.
10. The driver circuit of claim 1, wherein the switch path network comprises a first output switch path for connecting the driver output node to the first selective boost node, and a second output switch path for connecting the driver output node to the second selective boost node.
11. The driver circuit of claim 10, wherein each of the first output path and the second output path comprises a plurality of FET switches in series.
12. The driver circuit of claim 11, further comprising a bias controller for each of the first output switch path and the second output switch path, each bias controller configured to control a bias voltage between two of the plurality of FETs of the associated first output switch path or second output switch path when the associated one of the first output switch path or second output switch path is non-conductive.
13. The driver circuit of claim 12, wherein the bias controller for the first output switch path comprises a transistor for selectively connecting a midpoint node between the first capacitor and the second capacitor to the associated one of the first output switch path or the second output switch path at a point between the two FETs.
14. The driver circuit of claim 1, wherein, in use, the first and second selectively boost nodes comprise output nodes of a first boost stage, and the switch driver circuit comprises at least one additional boost stage,
Wherein each additional boost stage comprises a first additional capacitor and a second additional capacitor, and the switched path network is operable such that the first additional capacitor and the second additional capacitor are selectively connectable in series in or bypassed in a connection between respective first and second voltage inputs to respective first and second selectively boost nodes of the additional boost stages and the additional boost stages; and is also provided with
Wherein each additional boost stage is configured to receive at its first and second inputs the voltages at the first and second selective boost nodes of the previous boost stage; and is also provided with
Wherein the switch path network is configured to selectively connect the output driver node to a selective boost node of a last one of the additional boost stages.
15. The driver circuit of claim 14, wherein each additional boost stage is further configured to receive a midpoint voltage from a previous boost stage at a third input node, the midpoint voltage being a midpoint between the voltages at the first and second selective boost nodes of the previous boost stage, and wherein the additional boost stage is operable to selectively connect the first additional capacitor between the first and third input nodes of that additional boost stage to charge the first capacitor and to selectively connect the second additional capacitor between the third and second input nodes of that additional boost stage to charge the second additional capacitor.
16. The driver circuit of claim 1, further comprising a controller configured to selectively control the first switch driver to controllably vary the operating mode and the duty cycle with which the driver output node switches between associated switching voltages having a certain duty cycle.
17. The driver circuit of claim 1, further comprising a second switch driver for generating a second drive signal, the driver circuit configured to drive a load using the first and second drive signals in a bridged load configuration.
18. The driver circuit of claim 17, wherein the second switch driver has the same structure as the first switch driver and is operable in the same manner as the first switch driver.
19. The driver circuit of claim 1, further comprising a load configured to be driven by the first drive signal.
20. The driver circuit of claim 19, wherein the load is connected to the driver output node of the first switch driver via a series inductor.
21. The driver circuit of claim 19, wherein the load is at least one of: an audio output transducer; a haptic output transducer; piezoelectric transducers and ceramic transducers.
22. A switch driver for generating a drive signal, the switch driver comprising:
a first voltage input node and a second voltage input node, the first voltage input node and the second voltage input node for receiving a first voltage input and a second voltage input;
a capacitor node for connection to a first capacitor and a second capacitor;
a driver output node for outputting the first drive signal; and
a switch path network;
the switch driver is operable in use to:
selectively driving a first selectively boost node to the first voltage input or the first voltage input positively boosted by a voltage of the first capacitor;
selectively driving a second selectively boost node to the second voltage input or the second voltage input negatively boosted by a voltage of the second capacitor; and
Connecting the driver output node to a selected one of the first selective boost node and the second selective boost node;
wherein the first switch driver is selectively operable in a plurality of different modes of operation, wherein in each of the modes of operation the driver output node switches between two switching voltages, and the switching voltages are different in each of the modes.
23. A switch driver for generating a drive signal for driving a load within a defined output voltage range, the switch driver comprising:
a first voltage input node and a second voltage input node for receiving respective high-side and low-side voltage inputs defining an input voltage;
a capacitor node for connection to at least one capacitor;
an output node for outputting the drive signal; and
a switch path network;
wherein the switch driver is operable to generate a driver signal by selectively operating in one of a plurality of different modes, wherein in each of the modes the driver output node switches between two switching voltages with a controlled duty cycle, wherein the switching voltages are different in each mode and the switching voltages in each mode provide only a portion of the defined output voltage range.
CN202180056053.3A 2020-08-13 2021-07-29 Driver circuit Pending CN116097560A (en)

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US202063065051P 2020-08-13 2020-08-13
US63/065,051 2020-08-13
US202163146093P 2021-02-05 2021-02-05
US63/146,093 2021-02-05
US17/314,890 US11684950B2 (en) 2020-08-13 2021-05-07 Driver circuitry and operation
US17/314,917 2021-05-07
US17/314,890 2021-05-07
US17/314,917 US11277129B2 (en) 2020-08-13 2021-05-07 Driver circuitry and operation
US17/343,479 2021-06-09
US17/343,479 US11606642B2 (en) 2020-08-13 2021-06-09 Driver circuits
US17/349,536 US11368151B2 (en) 2020-08-13 2021-06-16 Driver circuitry and operation
US17/349,536 2021-06-16
GB2109569.0 2021-07-02
GB2109569.0A GB2598038B (en) 2020-08-13 2021-07-02 Driver circuits
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